TW200713331A - DLL driver control circuit - Google Patents

DLL driver control circuit

Info

Publication number
TW200713331A
TW200713331A TW095123974A TW95123974A TW200713331A TW 200713331 A TW200713331 A TW 200713331A TW 095123974 A TW095123974 A TW 095123974A TW 95123974 A TW95123974 A TW 95123974A TW 200713331 A TW200713331 A TW 200713331A
Authority
TW
Taiwan
Prior art keywords
dll
signal
control circuit
driver
dll driver
Prior art date
Application number
TW095123974A
Other languages
Chinese (zh)
Other versions
TWI309837B (en
Inventor
Kyung-Hoon Kim
Original Assignee
Hynix Semiconductor Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hynix Semiconductor Inc filed Critical Hynix Semiconductor Inc
Publication of TW200713331A publication Critical patent/TW200713331A/en
Application granted granted Critical
Publication of TWI309837B publication Critical patent/TWI309837B/en

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4076—Timing circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G11C7/222—Clock generating, synchronizing or distributing circuits within memory device
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
    • H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/22—Control and timing of internal memory operations
    • G11C2207/2227—Standby or low power modes

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Dram (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)

Abstract

A Delay Locked Loop (DLL) driver control circuit is capable of reducing an amount of current consumption by preventing the output of unnecessary clocks. The DLL driver control circuit includes a DLL driver for driving a DLL clock and a DLL driver controller for generating a control signal to control an operation of the DLL driver in response to a signal having information associated with an active mode. The DLL driver controller is provided with a counter for counting the DLL clock to produce a countth a setting value having a plurality of bits and generating an activated equal signal if the two values are the same, and an SR latch for accepting the equal signal and the signal having the information associated with the active mode to provide the control signal.
TW095123974A 2005-09-29 2006-06-30 Dll driver control circuit TWI309837B (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR20050091650 2005-09-29
KR1020050125353A KR100753100B1 (en) 2005-09-29 2005-12-19 Delay locked loop in semiconductor memory device

Publications (2)

Publication Number Publication Date
TW200713331A true TW200713331A (en) 2007-04-01
TWI309837B TWI309837B (en) 2009-05-11

Family

ID=37959238

Family Applications (1)

Application Number Title Priority Date Filing Date
TW095123974A TWI309837B (en) 2005-09-29 2006-06-30 Dll driver control circuit

Country Status (3)

Country Link
KR (1) KR100753100B1 (en)
CN (1) CN1941172B (en)
TW (1) TWI309837B (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI384758B (en) * 2008-11-06 2013-02-01 Hynix Semiconductor Inc Semiconductor memory device and method for generating output enable signal
TWI401693B (en) * 2009-01-05 2013-07-11 Nanya Technology Corp Voltage providing circuit, and signal delaying system utilizing the voltage providing circuit

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100935602B1 (en) * 2008-06-24 2010-01-07 주식회사 하이닉스반도체 Clock Driver and Semiconductor Memory Apparatus having the Same
CN102081965B (en) * 2011-02-21 2013-04-10 西安华芯半导体有限公司 Circuit for generating inner write clock of dynamic random access memory (DRAM)
US11004499B1 (en) * 2020-05-08 2021-05-11 Winbond Electronics Corp. Latency control circuit and method
TWI732558B (en) * 2020-05-18 2021-07-01 華邦電子股份有限公司 Delay-locked loop device and operation method thereof

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100333708B1 (en) * 1999-12-24 2002-04-22 박종섭 Delay Locked Loop reducing power consumption

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI384758B (en) * 2008-11-06 2013-02-01 Hynix Semiconductor Inc Semiconductor memory device and method for generating output enable signal
TWI401693B (en) * 2009-01-05 2013-07-11 Nanya Technology Corp Voltage providing circuit, and signal delaying system utilizing the voltage providing circuit

Also Published As

Publication number Publication date
KR100753100B1 (en) 2007-08-31
CN1941172A (en) 2007-04-04
KR20070036560A (en) 2007-04-03
CN1941172B (en) 2011-11-23
TWI309837B (en) 2009-05-11

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Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees