TW200707191A - Data processing system, cache system and method for issuing a request on an interconnect fabric without reference to a lower level cache based upon a tagged cache state - Google Patents

Data processing system, cache system and method for issuing a request on an interconnect fabric without reference to a lower level cache based upon a tagged cache state

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Publication number
TW200707191A
TW200707191A TW095110312A TW95110312A TW200707191A TW 200707191 A TW200707191 A TW 200707191A TW 095110312 A TW095110312 A TW 095110312A TW 95110312 A TW95110312 A TW 95110312A TW 200707191 A TW200707191 A TW 200707191A
Authority
TW
Taiwan
Prior art keywords
cache
target address
lower level
interconnect fabric
request
Prior art date
Application number
TW095110312A
Other languages
English (en)
Other versions
TWI391821B (zh
Inventor
Guy L Guthrie
Aaron C Sawdey
William J Starke
Jeffrey A Stuecheli
Original Assignee
Ibm
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibm filed Critical Ibm
Publication of TW200707191A publication Critical patent/TW200707191A/zh
Application granted granted Critical
Publication of TWI391821B publication Critical patent/TWI391821B/zh

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0811—Multiuser, multiprocessor or multiprocessing cache systems with multilevel cache hierarchies
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0815—Cache consistency protocols
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0815—Cache consistency protocols
    • G06F12/0831—Cache consistency protocols using a bus scheme, e.g. with bus monitoring or watching means
TW095110312A 2005-03-31 2006-03-24 在互連結構上發佈請求而無參照基於標籤快取狀態的低階快取之處理單元及資料處理系統與方法 TWI391821B (zh)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US11/095,734 US7536513B2 (en) 2005-03-31 2005-03-31 Data processing system, cache system and method for issuing a request on an interconnect fabric without reference to a lower level cache based upon a tagged cache state

Publications (2)

Publication Number Publication Date
TW200707191A true TW200707191A (en) 2007-02-16
TWI391821B TWI391821B (zh) 2013-04-01

Family

ID=37030379

Family Applications (1)

Application Number Title Priority Date Filing Date
TW095110312A TWI391821B (zh) 2005-03-31 2006-03-24 在互連結構上發佈請求而無參照基於標籤快取狀態的低階快取之處理單元及資料處理系統與方法

Country Status (4)

Country Link
US (1) US7536513B2 (zh)
JP (1) JP4928812B2 (zh)
CN (1) CN100428195C (zh)
TW (1) TWI391821B (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI797347B (zh) * 2018-07-27 2023-04-01 英商Ａｒｍ股份有限公司 使用儲存在記憶體系統中的記憶體保護表的記憶體保護單元以控制對記憶體的存取的裝置、方法和電腦程式

Families Citing this family (53)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7454578B2 (en) * 2005-02-10 2008-11-18 International Business Machines Corporation Data processing system and method for predictively selecting a scope of broadcast of an operation utilizing a location of a memory
US7415030B2 (en) * 2005-02-10 2008-08-19 International Business Machines Corporation Data processing system, method and interconnect fabric having an address-based launch governor
US7454577B2 (en) * 2005-02-10 2008-11-18 International Business Machines Corporation Data processing system and method for efficient communication utilizing an Tn and Ten coherency states
US7474658B2 (en) 2005-02-10 2009-01-06 International Business Machines Corporation Data processing system, method and interconnect fabric supporting concurrent operations of varying broadcast scope
US7366844B2 (en) * 2005-02-10 2008-04-29 International Business Machines Corporation Data processing system and method for handling castout collisions
US8214600B2 (en) 2005-02-10 2012-07-03 International Business Machines Corporation Data processing system and method for efficient coherency communication utilizing coherency domains
US7467323B2 (en) * 2005-02-10 2008-12-16 International Business Machines Corporation Data processing system and method for efficient storage of metadata in a system memory
US7389388B2 (en) * 2005-02-10 2008-06-17 International Business Machines Corporation Data processing system and method for efficient communication utilizing an in coherency state
US7584329B2 (en) * 2005-02-10 2009-09-01 International Business Machines Corporation Data processing system and method for efficient communication utilizing an Ig coherency state
US8140770B2 (en) 2005-02-10 2012-03-20 International Business Machines Corporation Data processing system and method for predictively selecting a scope of broadcast of an operation
US8230178B2 (en) * 2005-02-10 2012-07-24 International Business Machines Corporation Data processing system and method for efficient coherency communication utilizing coherency domain indicators
US7536513B2 (en) 2005-03-31 2009-05-19 International Business Machines Corporation Data processing system, cache system and method for issuing a request on an interconnect fabric without reference to a lower level cache based upon a tagged cache state
US7237070B2 (en) * 2005-04-19 2007-06-26 International Business Machines Corporation Cache memory, processing unit, data processing system and method for assuming a selected invalid coherency state based upon a request source
US20060259695A1 (en) * 2005-05-16 2006-11-16 Texas Instruments Incorporated Visualizing contents and states of hierarchical storage systems across multiple cores
US7444494B2 (en) * 2005-05-31 2008-10-28 International Business Machines Corporation Data processing system and method for predictively selecting a scope of broadcast of an operation utilizing a history-based prediction
US7380102B2 (en) * 2005-09-27 2008-05-27 International Business Machines Corporation Communication link control among inter-coupled multiple processing units in a node to respective units in another node for request broadcasting and combined response
US7818388B2 (en) * 2005-10-07 2010-10-19 International Business Machines Corporation Data processing system, method and interconnect fabric supporting multiple planes of processing nodes
US7512742B2 (en) * 2006-01-17 2009-03-31 International Business Machines Corporation Data processing system, cache system and method for precisely forming an invalid coherency state indicating a broadcast scope
US8495308B2 (en) * 2006-10-09 2013-07-23 International Business Machines Corporation Processor, data processing system and method supporting a shared global coherency state
US8205024B2 (en) * 2006-11-16 2012-06-19 International Business Machines Corporation Protecting ownership transfer with non-uniform protection windows
US7890704B2 (en) * 2006-12-19 2011-02-15 International Business Machines Corporation Implementing an enhanced hover state with active prefetches
US7680985B2 (en) * 2007-06-28 2010-03-16 International Business Machines Corporation Method and apparatus for accessing a split cache directory
US20090006753A1 (en) * 2007-06-28 2009-01-01 David Arnold Luick Design structure for accessing a cache with an effective address
US20090006754A1 (en) * 2007-06-28 2009-01-01 Luick David A Design structure for l2 cache/nest address translation
US20090006803A1 (en) * 2007-06-28 2009-01-01 David Arnold Luick L2 Cache/Nest Address Translation
US7937530B2 (en) * 2007-06-28 2011-05-03 International Business Machines Corporation Method and apparatus for accessing a cache with an effective address
US20090089510A1 (en) * 2007-09-28 2009-04-02 Mips Technologies, Inc. Speculative read in a cache coherent microprocessor
US8347037B2 (en) * 2008-10-22 2013-01-01 International Business Machines Corporation Victim cache replacement
US8209489B2 (en) * 2008-10-22 2012-06-26 International Business Machines Corporation Victim cache prefetching
US8868838B1 (en) * 2008-11-21 2014-10-21 Nvidia Corporation Multi-class data cache policies
US8499124B2 (en) * 2008-12-16 2013-07-30 International Business Machines Corporation Handling castout cache lines in a victim cache
US8225045B2 (en) * 2008-12-16 2012-07-17 International Business Machines Corporation Lateral cache-to-cache cast-in
US8489819B2 (en) * 2008-12-19 2013-07-16 International Business Machines Corporation Victim cache lateral castout targeting
US8949540B2 (en) * 2009-03-11 2015-02-03 International Business Machines Corporation Lateral castout (LCO) of victim cache line in data-invalid state
US8327073B2 (en) * 2009-04-09 2012-12-04 International Business Machines Corporation Empirically based dynamic control of acceptance of victim cache lateral castouts
US8347036B2 (en) * 2009-04-09 2013-01-01 International Business Machines Corporation Empirically based dynamic control of transmission of victim cache lateral castouts
US8312220B2 (en) * 2009-04-09 2012-11-13 International Business Machines Corporation Mode-based castout destination selection
US8667227B2 (en) * 2009-12-22 2014-03-04 Empire Technology Development, Llc Domain based cache coherence protocol
US9189403B2 (en) * 2009-12-30 2015-11-17 International Business Machines Corporation Selective cache-to-cache lateral castouts
US9411728B2 (en) 2011-12-23 2016-08-09 Intel Corporation Methods and apparatus for efficient communication between caches in hierarchical caching design
US9588889B2 (en) * 2011-12-29 2017-03-07 Intel Corporation Domain state
US9201792B2 (en) * 2011-12-29 2015-12-01 Intel Corporation Short circuit of probes in a chain
US9785568B2 (en) * 2014-05-19 2017-10-10 Empire Technology Development Llc Cache lookup bypass in multi-level cache systems
KR102312336B1 (ko) * 2014-07-29 2021-10-14 삼성전자주식회사 데이터 공유 방법 및 이를 위한 장치
US9665489B2 (en) * 2015-02-11 2017-05-30 Qualcomm Incorporated Methods of selecting available cache in multiple cluster system
KR20170056782A (ko) * 2015-11-13 2017-05-24 에스케이하이닉스 주식회사 메모리 시스템 및 메모리 시스템의 동작방법
US20170212840A1 (en) * 2016-01-21 2017-07-27 Qualcomm Incorporated Providing scalable dynamic random access memory (dram) cache management using tag directory caches
US10262721B2 (en) * 2016-03-10 2019-04-16 Micron Technology, Inc. Apparatuses and methods for cache invalidate
US10846235B2 (en) * 2018-04-28 2020-11-24 International Business Machines Corporation Integrated circuit and data processing system supporting attachment of a real address-agnostic accelerator
CN111767536B (zh) * 2019-04-01 2024-03-22 中国农业大学 一种抵抗处理器投机访问漏洞的cache防护方法及装置
US11163700B1 (en) 2020-04-30 2021-11-02 International Business Machines Corporation Initiating interconnect operation without waiting on lower level cache directory lookup
US11360906B2 (en) * 2020-08-14 2022-06-14 Alibaba Group Holding Limited Inter-device processing system with cache coherency
GB2607939A (en) 2021-06-17 2022-12-21 Morganic Solutions Ltd A flexible metal faced composite mould tool

Family Cites Families (31)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5113514A (en) * 1989-08-22 1992-05-12 Prime Computer, Inc. System bus for multiprocessor computer system
US5826052A (en) * 1994-04-29 1998-10-20 Advanced Micro Devices, Inc. Method and apparatus for concurrent access to multiple physical caches
US5852716A (en) 1996-07-02 1998-12-22 Sun Microsystems, Inc. Split-SMP computer system with local domains and a top repeater that distinguishes local and global transactions
US6374330B1 (en) * 1997-04-14 2002-04-16 International Business Machines Corporation Cache-coherency protocol with upstream undefined state
US6115795A (en) * 1997-08-06 2000-09-05 International Business Machines Corporation Method and apparatus for configurable multiple level cache with coherency in a multiprocessor system
US6701416B1 (en) * 1998-02-17 2004-03-02 International Business Machines Corporation Cache coherency protocol with tagged intervention of modified values
US6347361B1 (en) * 1998-02-17 2002-02-12 International Business Machines Corporation Cache coherency protocols with posted operations
US6192451B1 (en) * 1998-02-17 2001-02-20 International Business Machines Corporation Cache coherency protocol for a data processing system including a multi-level memory hierarchy
US6240490B1 (en) * 1998-07-20 2001-05-29 International Business Machines Corporation Comprehensive multilevel cache preloading mechanism in a multiprocessing simulation environment
US6397303B1 (en) * 1999-06-24 2002-05-28 International Business Machines Corporation Data processing system, cache, and method of cache management including an O state for memory-consistent cache lines
US6341331B1 (en) * 1999-10-01 2002-01-22 International Business Machines Corporation Method and system for managing a raid storage system with cache
US6606676B1 (en) 1999-11-08 2003-08-12 International Business Machines Corporation Method and apparatus to distribute interrupts to multiple interrupt handlers in a distributed symmetric multiprocessor system
US6385702B1 (en) * 1999-11-09 2002-05-07 International Business Machines Corporation High performance multiprocessor system with exclusive-deallocate cache state
TW463089B (en) * 2000-04-18 2001-11-11 Rdc Semiconductor Co Ltd Build-in micro controller architecture and method that are able to planned as master and cache memory
US6636949B2 (en) * 2000-06-10 2003-10-21 Hewlett-Packard Development Company, L.P. System for handling coherence protocol races in a scalable shared memory system based on chip multiprocessing
JP2002032265A (ja) * 2000-07-14 2002-01-31 Hitachi Ltd キャッシュ・アクセス制御方式およびデータ処理システム
US6629210B1 (en) * 2000-10-26 2003-09-30 International Business Machines Corporation Intelligent cache management mechanism via processor access sequence analysis
US6662275B2 (en) * 2001-02-12 2003-12-09 International Business Machines Corporation Efficient instruction cache coherency maintenance mechanism for scalable multiprocessor computer system with store-through data cache
US6754782B2 (en) 2001-06-21 2004-06-22 International Business Machines Corporation Decentralized global coherency management in a multi-node computer system
US6901485B2 (en) * 2001-06-21 2005-05-31 International Business Machines Corporation Memory directory management in a multi-node computer system
US6662277B2 (en) * 2001-07-31 2003-12-09 Hewlett-Packard Development Company, L.P. Cache system with groups of lines and with coherency for both single lines and groups of lines
US6658539B2 (en) * 2001-10-16 2003-12-02 International Business Machines Corporation Super-coherent data mechanisms for shared caches in a multiprocessing system
US6785774B2 (en) 2001-10-16 2004-08-31 International Business Machines Corporation High performance symmetric multiprocessing systems via super-coherent data mechanisms
US6704844B2 (en) * 2001-10-16 2004-03-09 International Business Machines Corporation Dynamic hardware and software performance optimizations for super-coherent SMP systems
US7100001B2 (en) 2002-01-24 2006-08-29 Intel Corporation Methods and apparatus for cache intervention
US7054999B2 (en) * 2002-08-02 2006-05-30 Intel Corporation High speed DRAM cache architecture
US7096323B1 (en) 2002-09-27 2006-08-22 Advanced Micro Devices, Inc. Computer system with processor cache that stores remote cache presence information
CN1499382A (zh) * 2002-11-05 2004-05-26 华为技术有限公司 廉价冗余磁盘阵列系统中高效高速缓存的实现方法
GB2403560A (en) 2003-07-02 2005-01-05 Advanced Risc Mach Ltd Memory bus within a coherent multi-processing system
US7484044B2 (en) * 2003-09-12 2009-01-27 Intel Corporation Method and apparatus for joint cache coherency states in multi-interface caches
US7536513B2 (en) 2005-03-31 2009-05-19 International Business Machines Corporation Data processing system, cache system and method for issuing a request on an interconnect fabric without reference to a lower level cache based upon a tagged cache state

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI797347B (zh) * 2018-07-27 2023-04-01 英商Ａｒｍ股份有限公司 使用儲存在記憶體系統中的記憶體保護表的記憶體保護單元以控制對記憶體的存取的裝置、方法和電腦程式

Also Published As

Publication number Publication date
JP2006285992A (ja) 2006-10-19
US7536513B2 (en) 2009-05-19
JP4928812B2 (ja) 2012-05-09
CN1841342A (zh) 2006-10-04
CN100428195C (zh) 2008-10-22
US20060224833A1 (en) 2006-10-05
TWI391821B (zh) 2013-04-01

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