TW200707160A - Circuit and method for generating programmable clock signals with minimum skew - Google Patents

Circuit and method for generating programmable clock signals with minimum skew

Info

Publication number
TW200707160A
TW200707160A TW094127002A TW94127002A TW200707160A TW 200707160 A TW200707160 A TW 200707160A TW 094127002 A TW094127002 A TW 094127002A TW 94127002 A TW94127002 A TW 94127002A TW 200707160 A TW200707160 A TW 200707160A
Authority
TW
Taiwan
Prior art keywords
clock
circuit
deskewer
clock signals
programmable clock
Prior art date
Application number
TW094127002A
Other languages
Chinese (zh)
Other versions
TWI316655B (en
Inventor
Rong-Chuan Tsai
Original Assignee
Winbond Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Winbond Electronics Corp filed Critical Winbond Electronics Corp
Priority to TW94127002A priority Critical patent/TWI316655B/en
Publication of TW200707160A publication Critical patent/TW200707160A/en
Application granted granted Critical
Publication of TWI316655B publication Critical patent/TWI316655B/en

Links

Landscapes

  • Semiconductor Integrated Circuits (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)

Abstract

A programmable clock deskewer generates an output clock with minimal clock skew. This is accomplished by means of a single series path coupling the input clock to the output clock. The programmable clock deskewer includes: an output clock generator, responsive to the input clock and control information, to generate the deskewed output clock; and a controller, responsive to the input clock, to generate the control information for controlling the frequency of the deskewed output clock. The programmable clock deskewer may be used to implement a clock tree with various clock outputs for a system on chip integrated circuit.
TW94127002A 2005-08-09 2005-08-09 Circuit and method for generating programmable clock signals with minimum skew TWI316655B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
TW94127002A TWI316655B (en) 2005-08-09 2005-08-09 Circuit and method for generating programmable clock signals with minimum skew

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW94127002A TWI316655B (en) 2005-08-09 2005-08-09 Circuit and method for generating programmable clock signals with minimum skew

Publications (2)

Publication Number Publication Date
TW200707160A true TW200707160A (en) 2007-02-16
TWI316655B TWI316655B (en) 2009-11-01

Family

ID=45073268

Family Applications (1)

Application Number Title Priority Date Filing Date
TW94127002A TWI316655B (en) 2005-08-09 2005-08-09 Circuit and method for generating programmable clock signals with minimum skew

Country Status (1)

Country Link
TW (1) TWI316655B (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI460573B (en) * 2009-02-02 2014-11-11 Asustek Comp Inc Computer system and overclocking method thereof
TWI551056B (en) * 2011-03-07 2016-09-21 國立交通大學 A programmable clock generator for being used in dynamic-voltage-and-frequency-scaling (dvfs) operated in sub- and near-threshold region

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI460573B (en) * 2009-02-02 2014-11-11 Asustek Comp Inc Computer system and overclocking method thereof
TWI551056B (en) * 2011-03-07 2016-09-21 國立交通大學 A programmable clock generator for being used in dynamic-voltage-and-frequency-scaling (dvfs) operated in sub- and near-threshold region

Also Published As

Publication number Publication date
TWI316655B (en) 2009-11-01

Similar Documents

Publication Publication Date Title
TW200731261A (en) Circuit and method for outputting data in semiconductor memory apparatus
TW200625051A (en) Switching power supply control
WO2007149212A3 (en) Rfid device with first clock for data acquisition and/or calibration of second clock
TW200737726A (en) Delay locked loop circuit and semiconductor integrated circuit device
TW201130229A (en) Delay locked loop and method of driving delay locked loop
TW200704563A (en) Signal generating apparatus for a bicycle control device
TW200728747A (en) Semiconductor integrated circuit, and designing method and testing method thereof
WO2004010579A8 (en) Apparatus and method for duty cycle correction
SG134277A1 (en) A variable power adaptive transmitter
TW200419910A (en) Method and device for generating a clock signal having predetermined clock signal properties
TW200703014A (en) System and method of adjusting output voltage of a transmitter based on error rate
GB0806138D0 (en) Crystal oscillator clock circuits
TW200727584A (en) Signal generating system and pulse generator
WO2007099579A8 (en) Ram macro and timing generating circuit for same
WO2008027792A3 (en) Power line communication device and method with frequency shifted modem
TW200737732A (en) Method and apparatus for generating output signal
TW200707160A (en) Circuit and method for generating programmable clock signals with minimum skew
TW200629031A (en) Operating current modifiying device and method thereof
DE50213877D1 (en) Control and / or regulation system with fieldbus
TWI268410B (en) Circuit and method for generating a clock signal
DE10318603B4 (en) Input reception circuit for weak high speed signal for generating several output signals, which can be processed at lower detecting speed
WO2009031191A1 (en) Clock output circuit
TW200715716A (en) DLL circuit having two input standard clocks, clock signal generation circuit having the DLL circuit and clock signal generation method
ATE347203T1 (en) TECHNIQUES FOR CONTROLLING A SIGNAL SAMPLING POINT
TWI266485B (en) Multi-phase clock generator and generating method for network controller