TW200707160A - Circuit and method for generating programmable clock signals with minimum skew - Google Patents
Circuit and method for generating programmable clock signals with minimum skewInfo
- Publication number
- TW200707160A TW200707160A TW094127002A TW94127002A TW200707160A TW 200707160 A TW200707160 A TW 200707160A TW 094127002 A TW094127002 A TW 094127002A TW 94127002 A TW94127002 A TW 94127002A TW 200707160 A TW200707160 A TW 200707160A
- Authority
- TW
- Taiwan
- Prior art keywords
- clock
- circuit
- deskewer
- clock signals
- programmable clock
- Prior art date
Links
Landscapes
- Semiconductor Integrated Circuits (AREA)
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Abstract
A programmable clock deskewer generates an output clock with minimal clock skew. This is accomplished by means of a single series path coupling the input clock to the output clock. The programmable clock deskewer includes: an output clock generator, responsive to the input clock and control information, to generate the deskewed output clock; and a controller, responsive to the input clock, to generate the control information for controlling the frequency of the deskewed output clock. The programmable clock deskewer may be used to implement a clock tree with various clock outputs for a system on chip integrated circuit.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
TW94127002A TWI316655B (en) | 2005-08-09 | 2005-08-09 | Circuit and method for generating programmable clock signals with minimum skew |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
TW94127002A TWI316655B (en) | 2005-08-09 | 2005-08-09 | Circuit and method for generating programmable clock signals with minimum skew |
Publications (2)
Publication Number | Publication Date |
---|---|
TW200707160A true TW200707160A (en) | 2007-02-16 |
TWI316655B TWI316655B (en) | 2009-11-01 |
Family
ID=45073268
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW94127002A TWI316655B (en) | 2005-08-09 | 2005-08-09 | Circuit and method for generating programmable clock signals with minimum skew |
Country Status (1)
Country | Link |
---|---|
TW (1) | TWI316655B (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI460573B (en) * | 2009-02-02 | 2014-11-11 | Asustek Comp Inc | Computer system and overclocking method thereof |
TWI551056B (en) * | 2011-03-07 | 2016-09-21 | 國立交通大學 | A programmable clock generator for being used in dynamic-voltage-and-frequency-scaling (dvfs) operated in sub- and near-threshold region |
-
2005
- 2005-08-09 TW TW94127002A patent/TWI316655B/en active
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI460573B (en) * | 2009-02-02 | 2014-11-11 | Asustek Comp Inc | Computer system and overclocking method thereof |
TWI551056B (en) * | 2011-03-07 | 2016-09-21 | 國立交通大學 | A programmable clock generator for being used in dynamic-voltage-and-frequency-scaling (dvfs) operated in sub- and near-threshold region |
Also Published As
Publication number | Publication date |
---|---|
TWI316655B (en) | 2009-11-01 |
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