TW200703627A - Non-volatile memory and fabricating method thereof - Google Patents

Non-volatile memory and fabricating method thereof

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Publication number
TW200703627A
TW200703627A TW094122514A TW94122514A TW200703627A TW 200703627 A TW200703627 A TW 200703627A TW 094122514 A TW094122514 A TW 094122514A TW 94122514 A TW94122514 A TW 94122514A TW 200703627 A TW200703627 A TW 200703627A
Authority
TW
Taiwan
Prior art keywords
doped region
gate structure
substrate
volatile memory
fabricating method
Prior art date
Application number
TW094122514A
Other languages
Chinese (zh)
Other versions
TWI270978B (en
Inventor
Chih-Cheng Liu
Original Assignee
Powerchip Semiconductor Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Powerchip Semiconductor Corp filed Critical Powerchip Semiconductor Corp
Priority to TW94122514A priority Critical patent/TWI270978B/en
Application granted granted Critical
Publication of TWI270978B publication Critical patent/TWI270978B/en
Publication of TW200703627A publication Critical patent/TW200703627A/en

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  • Non-Volatile Memory (AREA)
  • Semiconductor Memories (AREA)

Abstract

A non-volatile memory is constructed by at least a substrate, a first doped region, a second doped region, a third doped region, a first gate structure, a second gate structure, a first lightly doped region, and a second lightly doped region. The first, the second and the third doped regions are located in the substrate, and the second doped region is located between the first and the third doped regions. The first gate structure is located on the substrate between the first and the second doped region, and the second gate structure is located on the substrate between the second and the third doped region. The first lightly doped region is located in the substrate beneath the first gate structure adjacent to the first doped region, and the second lightly doped region is located in the substrate beneath the second gate structure adjacent to the third doped region.
TW94122514A 2005-07-04 2005-07-04 Non-volatile memory and fabricating method thereof TWI270978B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
TW94122514A TWI270978B (en) 2005-07-04 2005-07-04 Non-volatile memory and fabricating method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW94122514A TWI270978B (en) 2005-07-04 2005-07-04 Non-volatile memory and fabricating method thereof

Publications (2)

Publication Number Publication Date
TWI270978B TWI270978B (en) 2007-01-11
TW200703627A true TW200703627A (en) 2007-01-16

Family

ID=38430326

Family Applications (1)

Application Number Title Priority Date Filing Date
TW94122514A TWI270978B (en) 2005-07-04 2005-07-04 Non-volatile memory and fabricating method thereof

Country Status (1)

Country Link
TW (1) TWI270978B (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI462297B (en) * 2011-03-09 2014-11-21 Asahi Kasei Microdevices Corp Semiconductor device and method for manufacturing semiconductor device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI462297B (en) * 2011-03-09 2014-11-21 Asahi Kasei Microdevices Corp Semiconductor device and method for manufacturing semiconductor device
US9048252B2 (en) 2011-03-09 2015-06-02 Asahi Kasei Microdevices Corporation Semiconductor device and method for manufacturing semiconductor device

Also Published As

Publication number Publication date
TWI270978B (en) 2007-01-11

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Legal Events

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MM4A Annulment or lapse of patent due to non-payment of fees