TW200633092A - Chip with dummy bump - Google Patents

Chip with dummy bump

Info

Publication number
TW200633092A
TW200633092A TW094107671A TW94107671A TW200633092A TW 200633092 A TW200633092 A TW 200633092A TW 094107671 A TW094107671 A TW 094107671A TW 94107671 A TW94107671 A TW 94107671A TW 200633092 A TW200633092 A TW 200633092A
Authority
TW
Taiwan
Prior art keywords
chip
dummy bump
substrate
passivation layer
circuit region
Prior art date
Application number
TW094107671A
Other languages
Chinese (zh)
Other versions
TWI306636B (en
Inventor
Chun-Yu Lee
Tsung-Yu Lin
Chhien-Liang Chen
Hui-Chang Chen
Original Assignee
Au Optronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Au Optronics Corp filed Critical Au Optronics Corp
Priority to TW094107671A priority Critical patent/TWI306636B/en
Publication of TW200633092A publication Critical patent/TW200633092A/en
Application granted granted Critical
Publication of TWI306636B publication Critical patent/TWI306636B/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

A chip with dummy bump. The chip comprises a substrate, a plurality of bump, a passivation layer and a dummy bump structure. The substrate comprises a circuit region. The bumps are formed on the substrate and adjacent to the circuit region. The passivation layer is formed on the substrate, and the dummy bump structure is formed on the passivation layer and disposed on the circuit region.
TW094107671A 2005-03-14 2005-03-14 Chip with dummy bump TWI306636B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
TW094107671A TWI306636B (en) 2005-03-14 2005-03-14 Chip with dummy bump

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW094107671A TWI306636B (en) 2005-03-14 2005-03-14 Chip with dummy bump

Publications (2)

Publication Number Publication Date
TW200633092A true TW200633092A (en) 2006-09-16
TWI306636B TWI306636B (en) 2009-02-21

Family

ID=45071440

Family Applications (1)

Application Number Title Priority Date Filing Date
TW094107671A TWI306636B (en) 2005-03-14 2005-03-14 Chip with dummy bump

Country Status (1)

Country Link
TW (1) TWI306636B (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109216308A (en) * 2017-07-03 2019-01-15 南茂科技股份有限公司 Bump process and flip chip structure

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109216308A (en) * 2017-07-03 2019-01-15 南茂科技股份有限公司 Bump process and flip chip structure
CN109216308B (en) * 2017-07-03 2020-06-30 南茂科技股份有限公司 Bump process and flip chip structure

Also Published As

Publication number Publication date
TWI306636B (en) 2009-02-21

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Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees