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Application filed by Univ Nat Sun Yat SenfiledCriticalUniv Nat Sun Yat Sen
Priority to TW94104710ApriorityCriticalpatent/TWI267780B/en
Publication of TW200630872ApublicationCriticalpatent/TW200630872A/en
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Publication of TWI267780BpublicationCriticalpatent/TWI267780B/en
This invention presents a low power digital multiplier design by taking advantage of a 2-dimensional bypassing method. The proposed bypassing cells constituting the multiplier will be skipped such that redundant signal transitions can be avoided, when any horizontally partial product or any vertical operand is zero. Hence, it is a 2-dimensional dynamic bypassing method which detects the nullity in the row direction and the column direction.
TW94104710A2005-02-172005-02-17Power-aware multiplier design using 2-dimensional dynamic bypassing
TWI267780B
(en)