TW200629728A - Low-power high-performance storage circuitry and related methods - Google Patents
Low-power high-performance storage circuitry and related methodsInfo
- Publication number
- TW200629728A TW200629728A TW095115181A TW95115181A TW200629728A TW 200629728 A TW200629728 A TW 200629728A TW 095115181 A TW095115181 A TW 095115181A TW 95115181 A TW95115181 A TW 95115181A TW 200629728 A TW200629728 A TW 200629728A
- Authority
- TW
- Taiwan
- Prior art keywords
- drain
- source
- node
- nmos transistor
- transistor
- Prior art date
Links
Landscapes
- Logic Circuits (AREA)
- Electronic Switches (AREA)
- Static Random-Access Memory (AREA)
Abstract
An integrated circuit comprising a first NMOS transistor; a first PMOS transistor; a second NMOS transistor; a second PMOS transistor; a first bias voltage node coupled to a first source/drain of the first NMOS transistor; a second bias voltage node coupled to a first source/drain of the second PMOS; a third bias voltage node coupled to a gate of the first PMOS transistor; a fourth bias voltage node coupled to a gate of the second NMOS transistor; a pull-up node coupling a second source/drain of the first NMOS transistor to a first source/drain of the first PMOS transistor; a pull-down node coupling a second source/drain of the second PMOS transistor to a first source/drain of the second NMOS transistor; an input node; a storage node coupling a second source/drain of the first PMOS transistor to a second source/drain of the second NMOS transistor; an output node; an input switch coupled to controllably communicate an input data value from the input node to a gate of the first NMOS transistor and to a gate of the second PMOS transistor; and an output switch coupled to controllably communicate a stored data value from the storage node to the output node.
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
PCT/US2003/009599 WO2003083872A2 (en) | 2002-03-27 | 2003-03-27 | Low-power high-performance memory cell and related methods |
Publications (2)
Publication Number | Publication Date |
---|---|
TW200629728A true TW200629728A (en) | 2006-08-16 |
TWI276305B TWI276305B (en) | 2007-03-11 |
Family
ID=38623136
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW092122109A TWI274346B (en) | 2003-03-27 | 2003-08-12 | Low-power high-performance storage circuitry and related methods |
TW095115181A TWI276305B (en) | 2003-03-27 | 2003-08-12 | Low-power high-performance storage circuitry and related methods |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW092122109A TWI274346B (en) | 2003-03-27 | 2003-08-12 | Low-power high-performance storage circuitry and related methods |
Country Status (1)
Country | Link |
---|---|
TW (2) | TWI274346B (en) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7242626B2 (en) * | 2005-05-06 | 2007-07-10 | Freescale Semiconductor, Inc. | Method and apparatus for low voltage write in a static random access memory |
US11961567B2 (en) | 2021-09-21 | 2024-04-16 | PUFsecurity Corporation | Key storage device and key generation method |
-
2003
- 2003-08-12 TW TW092122109A patent/TWI274346B/en not_active IP Right Cessation
- 2003-08-12 TW TW095115181A patent/TWI276305B/en not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
TW200419575A (en) | 2004-10-01 |
TWI274346B (en) | 2007-02-21 |
TWI276305B (en) | 2007-03-11 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
MM4A | Annulment or lapse of patent due to non-payment of fees |