TW200629280A - On-chip data grouping and alignment - Google Patents

On-chip data grouping and alignment

Info

Publication number
TW200629280A
TW200629280A TW094147838A TW94147838A TW200629280A TW 200629280 A TW200629280 A TW 200629280A TW 094147838 A TW094147838 A TW 094147838A TW 94147838 A TW94147838 A TW 94147838A TW 200629280 A TW200629280 A TW 200629280A
Authority
TW
Taiwan
Prior art keywords
alignment
ability
data grouping
chip data
data sectors
Prior art date
Application number
TW094147838A
Other languages
Chinese (zh)
Inventor
Sergey Anatolievich Gorobets
Original Assignee
Sandisk Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sandisk Corp filed Critical Sandisk Corp
Publication of TW200629280A publication Critical patent/TW200629280A/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
    • G06F12/023—Free address space management
    • G06F12/0238—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
    • G06F12/0246—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory in block erasable memory, e.g. flash memory
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/04—Addressing variable-length words or parts of words
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G11C16/102—External programming circuits, e.g. EPROM programmers; In-circuit programming or reprogramming; EPROM emulators
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1006—Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/12—Group selection circuits, e.g. for memory block selection, chip selection, array selection

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Memory System Of A Hierarchy Structure (AREA)

Abstract

The invention describes the method for regrouping data read from multi-sector pages inside a memory chip. As a result, garbage collection operation time greatly reduces and overall system performance increases. Architectural features include the ability to selectively transfer individual data sectors of a page between on-chip registers and the ability to realign data sectors within a register.
TW094147838A 2004-12-30 2005-12-30 On-chip data grouping and alignment TW200629280A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US11/026,549 US7212440B2 (en) 2004-12-30 2004-12-30 On-chip data grouping and alignment

Publications (1)

Publication Number Publication Date
TW200629280A true TW200629280A (en) 2006-08-16

Family

ID=36215818

Family Applications (1)

Application Number Title Priority Date Filing Date
TW094147838A TW200629280A (en) 2004-12-30 2005-12-30 On-chip data grouping and alignment

Country Status (8)

Country Link
US (2) US7212440B2 (en)
EP (2) EP1839155A2 (en)
JP (1) JP2008527586A (en)
KR (1) KR101060089B1 (en)
CN (1) CN101142564B (en)
IL (1) IL184301A0 (en)
TW (1) TW200629280A (en)
WO (1) WO2006074086A2 (en)

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EP2256637A1 (en) 2010-12-01
WO2006074086B1 (en) 2007-01-18
US20060149890A1 (en) 2006-07-06
CN101142564B (en) 2011-12-14
WO2006074086A3 (en) 2006-10-26
US20070159885A1 (en) 2007-07-12
KR101060089B1 (en) 2011-08-29
KR20070102507A (en) 2007-10-18
US7502259B2 (en) 2009-03-10
IL184301A0 (en) 2007-10-31
US7212440B2 (en) 2007-05-01

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