TW200627606A - Chip scale package and method for manufacturing the same - Google Patents

Chip scale package and method for manufacturing the same

Info

Publication number
TW200627606A
TW200627606A TW094102163A TW94102163A TW200627606A TW 200627606 A TW200627606 A TW 200627606A TW 094102163 A TW094102163 A TW 094102163A TW 94102163 A TW94102163 A TW 94102163A TW 200627606 A TW200627606 A TW 200627606A
Authority
TW
Taiwan
Prior art keywords
contact pads
circuit layer
patterned circuit
scale package
chip scale
Prior art date
Application number
TW094102163A
Other languages
Chinese (zh)
Other versions
TWI305401B (en
Inventor
Jun-Young Yang
You-Ock Joo
Dong-Pil Jung
Original Assignee
Advanced Semiconductor Eng
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Semiconductor Eng filed Critical Advanced Semiconductor Eng
Priority to TW094102163A priority Critical patent/TWI305401B/en
Publication of TW200627606A publication Critical patent/TW200627606A/en
Application granted granted Critical
Publication of TWI305401B publication Critical patent/TWI305401B/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods

Landscapes

  • Wire Bonding (AREA)

Abstract

A chip scale package includes a patterned circuit layer attached to the active surface of a semiconductor chip through an anisotropic conductive adhesive layer such that contact pads on a lower surface of the patterned circuit layer are electrically coupled to corresponding bonding pads on the semiconductor chip. The patterned circuit layer has a plurality of openings formed therein at locations corresponding to the contact pads such that each of the contact pads has a portion exposed from an upper surface of the patterned circuit layer through the corresponding opening. A plurality of metal bumps are respectively disposed in the openings and mounted to the exposed portions of the contact pads for making external electrical connection. The present invention further provides a method for manufacturing the chip scale package at the wafer-level.
TW094102163A 2005-01-25 2005-01-25 Chip scale package and method for manufacturing the same TWI305401B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
TW094102163A TWI305401B (en) 2005-01-25 2005-01-25 Chip scale package and method for manufacturing the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW094102163A TWI305401B (en) 2005-01-25 2005-01-25 Chip scale package and method for manufacturing the same

Publications (2)

Publication Number Publication Date
TW200627606A true TW200627606A (en) 2006-08-01
TWI305401B TWI305401B (en) 2009-01-11

Family

ID=45071138

Family Applications (1)

Application Number Title Priority Date Filing Date
TW094102163A TWI305401B (en) 2005-01-25 2005-01-25 Chip scale package and method for manufacturing the same

Country Status (1)

Country Link
TW (1) TWI305401B (en)

Also Published As

Publication number Publication date
TWI305401B (en) 2009-01-11

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