TW200623335A - Method and system for correcting soft errors in memory circuit - Google Patents

Method and system for correcting soft errors in memory circuit

Info

Publication number
TW200623335A
TW200623335A TW094146957A TW94146957A TW200623335A TW 200623335 A TW200623335 A TW 200623335A TW 094146957 A TW094146957 A TW 094146957A TW 94146957 A TW94146957 A TW 94146957A TW 200623335 A TW200623335 A TW 200623335A
Authority
TW
Taiwan
Prior art keywords
memory circuit
soft errors
soft error
correcting
correcting soft
Prior art date
Application number
TW094146957A
Other languages
English (en)
Other versions
TWI295086B (en
Inventor
Chien-Hua Huang
Original Assignee
Taiwan Semiconductor Mfg Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Taiwan Semiconductor Mfg Co Ltd filed Critical Taiwan Semiconductor Mfg Co Ltd
Publication of TW200623335A publication Critical patent/TW200623335A/zh
Application granted granted Critical
Publication of TWI295086B publication Critical patent/TWI295086B/zh

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1006—Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/31816—Soft error testing; Soft error rate evaluation; Single event testing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/38—Response verification devices
    • G11C29/42—Response verification devices using error correcting codes [ECC] or parity check
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/52—Protection of memory contents; Detection of errors in memory contents
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C2029/0409—Online test

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Static Random-Access Memory (AREA)
TW094146957A 2004-12-30 2005-12-28 Method and system for correcting soft errors in memory circuit TWI295086B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US11/026,354 US7644341B2 (en) 2004-12-30 2004-12-30 Method and system for correcting soft errors in memory circuit

Publications (2)

Publication Number Publication Date
TW200623335A true TW200623335A (en) 2006-07-01
TWI295086B TWI295086B (en) 2008-03-21

Family

ID=36642106

Family Applications (1)

Application Number Title Priority Date Filing Date
TW094146957A TWI295086B (en) 2004-12-30 2005-12-28 Method and system for correcting soft errors in memory circuit

Country Status (2)

Country Link
US (1) US7644341B2 (zh)
TW (1) TWI295086B (zh)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7550858B1 (en) * 2005-07-19 2009-06-23 Xilinx, Inc. Random sequence generation using alpha particle emission
US8122320B2 (en) * 2008-01-22 2012-02-21 Qimonda Ag Integrated circuit including an ECC error counter
US9208024B2 (en) 2014-01-10 2015-12-08 Freescale Semiconductor, Inc. Memory ECC with hard and soft error detection and management
US10719461B2 (en) * 2018-08-07 2020-07-21 Western Digital Technologies, Inc. Solid state device with distributed bit buckets
US10956262B2 (en) * 2019-03-14 2021-03-23 Micron Technology, Inc. Deferred error code correction with improved effective data bandwidth performance

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01183000A (ja) * 1988-01-14 1989-07-20 Mitsubishi Electric Corp 誤り訂正回路を有する半導体メモリ装置
US5307356A (en) * 1990-04-16 1994-04-26 International Business Machines Corporation Interlocked on-chip ECC system
JP2002056671A (ja) * 2000-08-14 2002-02-22 Hitachi Ltd ダイナミック型ｒａｍのデータ保持方法と半導体集積回路装置
US6463001B1 (en) * 2000-09-15 2002-10-08 Intel Corporation Circuit and method for merging refresh and access operations for a memory device
US6779076B1 (en) * 2000-10-05 2004-08-17 Micron Technology, Inc. Method and system for using dynamic random access memory as cache memory
US6493836B2 (en) * 2000-11-30 2002-12-10 Compaq Information Technologies Group, L.P. Method and apparatus for scheduling and using memory calibrations to reduce memory errors in high speed memory devices
US6792567B2 (en) * 2001-04-30 2004-09-14 Stmicroelectronics, Inc. System and method for correcting soft errors in random access memory devices
US7051264B2 (en) * 2001-11-14 2006-05-23 Monolithic System Technology, Inc. Error correcting memory and method of operating same
US6838331B2 (en) * 2002-04-09 2005-01-04 Micron Technology, Inc. Method and system for dynamically operating memory in a power-saving error correction mode
US6649456B1 (en) * 2002-10-16 2003-11-18 Taiwan Semiconductor Manufacturing Company SRAM cell design for soft error rate immunity
JP4418153B2 (ja) * 2002-12-27 2010-02-17 株式会社ルネサステクノロジ 半導体装置
US7447950B2 (en) * 2003-05-20 2008-11-04 Nec Electronics Corporation Memory device and memory error correction method
US20050283566A1 (en) * 2003-09-29 2005-12-22 Rockwell Automation Technologies, Inc. Self testing and securing ram system and method
JP4102313B2 (ja) * 2004-02-05 2008-06-18 株式会社東芝 半導体集積回路装置
JP4191100B2 (ja) * 2004-06-18 2008-12-03 エルピーダメモリ株式会社 半導体記憶装置

Also Published As

Publication number Publication date
TWI295086B (en) 2008-03-21
US20060150062A1 (en) 2006-07-06
US7644341B2 (en) 2010-01-05

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Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees