TW200620096A - Variable group associativity branch target address cache delivering multiple target address per cache line - Google Patents
Variable group associativity branch target address cache delivering multiple target address per cache lineInfo
- Publication number
- TW200620096A TW200620096A TW094126567A TW94126567A TW200620096A TW 200620096 A TW200620096 A TW 200620096A TW 094126567 A TW094126567 A TW 094126567A TW 94126567 A TW94126567 A TW 94126567A TW 200620096 A TW200620096 A TW 200620096A
- Authority
- TW
- Taiwan
- Prior art keywords
- cache
- target address
- branch
- associativity
- different
- Prior art date
Links
Landscapes
- Memory System Of A Hierarchy Structure (AREA)
- Advance Control (AREA)
Abstract
A branch prediction apparatus having two two-way set associative cache memories each indexed by a lower portion of an instruction cache fetch address is disclosed. The index selects a group of four entries, one from each way of each cache. Each entry stores a single target address of a different previously executed branch instruction. For some groups, the four entries cache target addresses for one branch instruction in each of four different cache lines, to obtain four-way group associativity; for other groups, the four entries cache target addresses for one branch instruction in each of two different cache lines and two branch instructions in a third different cache line, to effectively obtain three-way group associativity, depending on the distribution of the branch instructions in the program The apparatus trades off associativity for number of predictable branches per cache line on an index-by-index basis to efficiently use storage space.
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US59886804P | 2004-08-04 | 2004-08-04 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| TW200620096A true TW200620096A (en) | 2006-06-16 |
| TWI303777B TWI303777B (en) | 2008-12-01 |
Family
ID=36923343
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| TW94126567A TWI303777B (en) | 2004-08-04 | 2005-08-04 | Branch prediction apparatus, method for single target address, and computer program product |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN100388187C (en) |
| TW (1) | TWI303777B (en) |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101887358B (en) * | 2009-05-19 | 2014-06-25 | 威盛电子股份有限公司 | Device and method suitable for a microprocessor |
| TWI579695B (en) | 2011-12-28 | 2017-04-21 | 瑞昱半導體股份有限公司 | Method for cleaning cache of processor and associated processor |
| CN106406823B (en) * | 2016-10-10 | 2019-07-05 | 上海兆芯集成电路有限公司 | Branch predictor and method for operating branch predictor |
| CN106843812A (en) * | 2016-12-23 | 2017-06-13 | 北京北大众志微系统科技有限责任公司 | A kind of method and device for realizing the prediction of indirect branch associated software |
| US11642768B2 (en) * | 2020-07-15 | 2023-05-09 | Snap-On Incorporated | Dead blow hammer head |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6470438B1 (en) * | 2000-02-22 | 2002-10-22 | Hewlett-Packard Company | Methods and apparatus for reducing false hits in a non-tagged, n-way cache |
| US20020194462A1 (en) * | 2001-05-04 | 2002-12-19 | Ip First Llc | Apparatus and method for selecting one of multiple target addresses stored in a speculative branch target address cache per instruction cache line |
| US7165168B2 (en) * | 2003-01-14 | 2007-01-16 | Ip-First, Llc | Microprocessor with branch target address cache update queue |
| US7406569B2 (en) * | 2002-08-12 | 2008-07-29 | Nxp B.V. | Instruction cache way prediction for jump targets |
| US7185186B2 (en) * | 2003-01-14 | 2007-02-27 | Ip-First, Llc | Apparatus and method for resolving deadlock fetch conditions involving branch target address cache |
| US7152154B2 (en) * | 2003-01-16 | 2006-12-19 | Ip-First, Llc. | Apparatus and method for invalidation of redundant branch target address cache entries |
-
2005
- 2005-08-04 TW TW94126567A patent/TWI303777B/en active
- 2005-08-04 CN CNB2005100919093A patent/CN100388187C/en active Active
Also Published As
| Publication number | Publication date |
|---|---|
| TWI303777B (en) | 2008-12-01 |
| CN1821953A (en) | 2006-08-23 |
| CN100388187C (en) | 2008-05-14 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| EP1624369A3 (en) | Apparatus for predicting multiple branch target addresses | |
| US7822926B2 (en) | Cache memory | |
| TW200620096A (en) | Variable group associativity branch target address cache delivering multiple target address per cache line | |
| US20050132141A1 (en) | Cache system | |
| WO2007143508A3 (en) | Sliding-window, block-based branch target address cache | |
| CN105893269A (en) | Memory management method used in Linux system | |
| US9396117B2 (en) | Instruction cache power reduction | |
| US20090249036A1 (en) | Efficient method and apparatus for employing a micro-op cache in a processor | |
| US9734059B2 (en) | Methods and apparatus for data cache way prediction based on classification as stack data | |
| EP1439460A3 (en) | Apparatus and method for invalidation of redundant entries in a branch target address cache | |
| GB201303300D0 (en) | Data Processing | |
| CN105393210B (en) | Memory cell and method for handling data storage reference | |
| US10558578B2 (en) | Servicing CPU demand requests with inflight prefetches | |
| TW200834306A (en) | Configurable cache for a microprocessor | |
| TW200604797A (en) | Cache memory prefetcher | |
| GB2577023A (en) | Translation support for a virtual cache | |
| GB2377298A (en) | Method for controlling cache system comprising direct-mapped cache and fully-associative buffer | |
| DE102013202995A1 (en) | Energy savings in branch forecasts | |
| DE602004025556D1 (en) | Maintain caching coherence for direct access (DMA), completion of a task, synchronization | |
| GB2582451A (en) | Concurrent prediction of branch addresses and update of register contents | |
| CN103902502B (en) | A kind of extendible separate type isomery thousand core system | |
| US20050160228A1 (en) | Equipment and method for cache replacement | |
| US20080114939A1 (en) | Cache accessing using muTAGs | |
| GB201018013D0 (en) | Provision of access control data within a data processing system | |
| EP2017737A1 (en) | Cache memory |