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Priority claimed from US10/711,939external-prioritypatent/US7119390B2/en
Application filed by Promos Technologies IncfiledCriticalPromos Technologies Inc
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Publication of TWI246184BpublicationCriticalpatent/TWI246184B/en
Publication of TW200612550ApublicationCriticalpatent/TW200612550A/en
A dynamic random access memory (DRAM) cell is described, including a semiconductor pillar on a substrate, a capacitor on a lower portion of a sidewall of the pillar, and a vertical transistor on an upper portion of the sidewall of the pillar. The capacitor includes a first plate in the lower portion of the pillar, a second plate as an upper electrode at the periphery of the first plate, a third plate at the periphery of the second plate electrically connected with the first plate to form a lower electrode, and a dielectric layer separating the second plate form the first and the third plates. A DRAM array based on the DRAM cell and a method for fabricating the DRAM array are also described.
TW93132910A2004-10-142004-10-29Dynamic random access memory and fabrication thereof
TWI246184B
(en)
Semiconductor constructions, memory cells, DRAM arrays, electronic systems; methods of forming semiconductor constructions; and methods of forming DRAM arrays