TW200612539A - High density substrate for multi-chip package - Google Patents

High density substrate for multi-chip package

Info

Publication number
TW200612539A
TW200612539A TW093131282A TW93131282A TW200612539A TW 200612539 A TW200612539 A TW 200612539A TW 093131282 A TW093131282 A TW 093131282A TW 93131282 A TW93131282 A TW 93131282A TW 200612539 A TW200612539 A TW 200612539A
Authority
TW
Taiwan
Prior art keywords
chip
substrate
high density
mounting region
build
Prior art date
Application number
TW093131282A
Other languages
Chinese (zh)
Other versions
TWI242869B (en
Inventor
Chih-Pin Hung
Yi-Chuan Ding
Original Assignee
Advanced Semiconductor Eng
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Semiconductor Eng filed Critical Advanced Semiconductor Eng
Priority to TW93131282A priority Critical patent/TWI242869B/en
Application granted granted Critical
Publication of TWI242869B publication Critical patent/TWI242869B/en
Publication of TW200612539A publication Critical patent/TW200612539A/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors

Landscapes

  • Wire Bonding (AREA)

Abstract

A high density substrate for multi-chip package mainly includes a laminated substrate body and a build-up substrate portion. The substrate body has a first chip-mounting region and includes a plurality of first contact pads. The first contact pads are arranged around the first chip-mounting region for connection of bonding wires. The build-up substrate portion is integrated with the substrate body and has a second chip-mounting region. A plurality of second contact pads can be formed within the second chip-mounting region in high density for flip-chip bonding. Preferably, the build-up substrate portion compensates a recess or a cavity of the substrate body, so that the first and second chip-bonding regions are coplanar to cover a solder mask. Thus the high density substrate is excellent for packaging various type chips.
TW93131282A 2004-10-15 2004-10-15 High density substrate for multi-chip package TWI242869B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
TW93131282A TWI242869B (en) 2004-10-15 2004-10-15 High density substrate for multi-chip package

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW93131282A TWI242869B (en) 2004-10-15 2004-10-15 High density substrate for multi-chip package

Publications (2)

Publication Number Publication Date
TWI242869B TWI242869B (en) 2005-11-01
TW200612539A true TW200612539A (en) 2006-04-16

Family

ID=37022631

Family Applications (1)

Application Number Title Priority Date Filing Date
TW93131282A TWI242869B (en) 2004-10-15 2004-10-15 High density substrate for multi-chip package

Country Status (1)

Country Link
TW (1) TWI242869B (en)

Cited By (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8446000B2 (en) 2009-11-24 2013-05-21 Chi-Chih Shen Package structure and package process
US8541883B2 (en) 2011-11-29 2013-09-24 Advanced Semiconductor Engineering, Inc. Semiconductor device having shielded conductive vias
US8643167B2 (en) 2011-01-06 2014-02-04 Advanced Semiconductor Engineering, Inc. Semiconductor package with through silicon vias and method for making the same
US8692362B2 (en) 2010-08-30 2014-04-08 Advanced Semiconductor Engineering, Inc. Semiconductor structure having conductive vias and method for manufacturing the same
US8786060B2 (en) 2012-05-04 2014-07-22 Advanced Semiconductor Engineering, Inc. Semiconductor package integrated with conformal shield and antenna
US8786098B2 (en) 2010-10-11 2014-07-22 Advanced Semiconductor Engineering, Inc. Semiconductor element having conductive vias and semiconductor package having a semiconductor element with conductive vias and method for making the same
US8841751B2 (en) 2013-01-23 2014-09-23 Advanced Semiconductor Engineering, Inc. Through silicon vias for semiconductor devices and manufacturing method thereof
US8853819B2 (en) 2011-01-07 2014-10-07 Advanced Semiconductor Engineering, Inc. Semiconductor structure with passive element network and manufacturing method thereof
US8865520B2 (en) 2010-08-27 2014-10-21 Advanced Semiconductor Engineering, Inc. Carrier bonding and detaching processes for a semiconductor wafer
US8937387B2 (en) 2012-11-07 2015-01-20 Advanced Semiconductor Engineering, Inc. Semiconductor device with conductive vias
US8952542B2 (en) 2012-11-14 2015-02-10 Advanced Semiconductor Engineering, Inc. Method for dicing a semiconductor wafer having through silicon vias and resultant structures
US8963316B2 (en) 2012-02-15 2015-02-24 Advanced Semiconductor Engineering, Inc. Semiconductor device and method for manufacturing the same
US8975157B2 (en) 2012-02-08 2015-03-10 Advanced Semiconductor Engineering, Inc. Carrier bonding and detaching processes for a semiconductor wafer
US8987734B2 (en) 2013-03-15 2015-03-24 Advanced Semiconductor Engineering, Inc. Semiconductor wafer, semiconductor process and semiconductor package
US9007273B2 (en) 2010-09-09 2015-04-14 Advances Semiconductor Engineering, Inc. Semiconductor package integrated with conformal shield and antenna
US9024445B2 (en) 2010-11-19 2015-05-05 Advanced Semiconductor Engineering, Inc. Semiconductor device having conductive vias and semiconductor package having semiconductor device
US9089268B2 (en) 2013-03-13 2015-07-28 Advanced Semiconductor Engineering, Inc. Neural sensing device and method for making the same
US9153542B2 (en) 2012-08-01 2015-10-06 Advanced Semiconductor Engineering, Inc. Semiconductor package having an antenna and manufacturing method thereof
US9173583B2 (en) 2013-03-15 2015-11-03 Advanced Semiconductor Engineering, Inc. Neural sensing device and method for making the same
US9960121B2 (en) 2012-12-20 2018-05-01 Advanced Semiconductor Engineering, Inc. Semiconductor device having conductive via and manufacturing process for same
US9978688B2 (en) 2013-02-28 2018-05-22 Advanced Semiconductor Engineering, Inc. Semiconductor package having a waveguide antenna and manufacturing method thereof

Cited By (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8446000B2 (en) 2009-11-24 2013-05-21 Chi-Chih Shen Package structure and package process
US8865520B2 (en) 2010-08-27 2014-10-21 Advanced Semiconductor Engineering, Inc. Carrier bonding and detaching processes for a semiconductor wafer
US8692362B2 (en) 2010-08-30 2014-04-08 Advanced Semiconductor Engineering, Inc. Semiconductor structure having conductive vias and method for manufacturing the same
US9007273B2 (en) 2010-09-09 2015-04-14 Advances Semiconductor Engineering, Inc. Semiconductor package integrated with conformal shield and antenna
US8786098B2 (en) 2010-10-11 2014-07-22 Advanced Semiconductor Engineering, Inc. Semiconductor element having conductive vias and semiconductor package having a semiconductor element with conductive vias and method for making the same
US9024445B2 (en) 2010-11-19 2015-05-05 Advanced Semiconductor Engineering, Inc. Semiconductor device having conductive vias and semiconductor package having semiconductor device
US8643167B2 (en) 2011-01-06 2014-02-04 Advanced Semiconductor Engineering, Inc. Semiconductor package with through silicon vias and method for making the same
US8853819B2 (en) 2011-01-07 2014-10-07 Advanced Semiconductor Engineering, Inc. Semiconductor structure with passive element network and manufacturing method thereof
US8541883B2 (en) 2011-11-29 2013-09-24 Advanced Semiconductor Engineering, Inc. Semiconductor device having shielded conductive vias
US8975157B2 (en) 2012-02-08 2015-03-10 Advanced Semiconductor Engineering, Inc. Carrier bonding and detaching processes for a semiconductor wafer
US8963316B2 (en) 2012-02-15 2015-02-24 Advanced Semiconductor Engineering, Inc. Semiconductor device and method for manufacturing the same
US8786060B2 (en) 2012-05-04 2014-07-22 Advanced Semiconductor Engineering, Inc. Semiconductor package integrated with conformal shield and antenna
US9153542B2 (en) 2012-08-01 2015-10-06 Advanced Semiconductor Engineering, Inc. Semiconductor package having an antenna and manufacturing method thereof
US8937387B2 (en) 2012-11-07 2015-01-20 Advanced Semiconductor Engineering, Inc. Semiconductor device with conductive vias
US8952542B2 (en) 2012-11-14 2015-02-10 Advanced Semiconductor Engineering, Inc. Method for dicing a semiconductor wafer having through silicon vias and resultant structures
US9960121B2 (en) 2012-12-20 2018-05-01 Advanced Semiconductor Engineering, Inc. Semiconductor device having conductive via and manufacturing process for same
US8841751B2 (en) 2013-01-23 2014-09-23 Advanced Semiconductor Engineering, Inc. Through silicon vias for semiconductor devices and manufacturing method thereof
US9728451B2 (en) 2013-01-23 2017-08-08 Advanced Semiconductor Engineering, Inc. Through silicon vias for semiconductor devices and manufacturing method thereof
US9978688B2 (en) 2013-02-28 2018-05-22 Advanced Semiconductor Engineering, Inc. Semiconductor package having a waveguide antenna and manufacturing method thereof
US9089268B2 (en) 2013-03-13 2015-07-28 Advanced Semiconductor Engineering, Inc. Neural sensing device and method for making the same
US8987734B2 (en) 2013-03-15 2015-03-24 Advanced Semiconductor Engineering, Inc. Semiconductor wafer, semiconductor process and semiconductor package
US9173583B2 (en) 2013-03-15 2015-11-03 Advanced Semiconductor Engineering, Inc. Neural sensing device and method for making the same

Also Published As

Publication number Publication date
TWI242869B (en) 2005-11-01

Similar Documents

Publication Publication Date Title
TW200612539A (en) High density substrate for multi-chip package
WO2003105223A3 (en) Quad flat non-leaded package comprising a semiconductor device
TW200503209A (en) Semiconductor package
TW200629516A (en) Multichip leadframe package
TW429567B (en) Stack package and method of fabricating the same
GB2339334B (en) Chip size package and method of fabricating the same
TW200717769A (en) Multi-chip package structure
TW200620607A (en) Flip chip and wire bond semiconductor package
TW200746386A (en) System in package
TW200515557A (en) Semiconductor package, method for manufacturing the same and lead frame for use in the same
TW200729429A (en) Semiconductor package structure and fabrication method thereof
HK1124687A1 (en) Semiconductor component and method of manufacture
SG114474A1 (en) Semiconductor package having increased solder joint strength
TW200504963A (en) Multi-chip semiconductor package and manufacturing method thereof
TW200707676A (en) Thin IC package for improving heat dissipation from chip backside
US6903455B2 (en) Side braze packages
SG122884A1 (en) Semiconductor system with fine pitch lead fingers
WO2006050439A3 (en) Multichip semiconductor package
TW200511535A (en) Leadless semiconductor package and bump chip carrier semiconductor package
TW200711151A (en) Multi-chip package structure
TW200802771A (en) BGA package with leads on chip
TW200603355A (en) Chip-under-tape package and process for manufacturing the same
TWI256115B (en) Memory package
TW200623291A (en) Method for manufacturing multi-chip package having encapsulated bond-wires between stack chips
TW200504964A (en) Semiconductor chip package and method for making the same