TW200608481A - Methods and systems for a stress-free buff - Google Patents

Methods and systems for a stress-free buff

Info

Publication number
TW200608481A
TW200608481A TW094121619A TW94121619A TW200608481A TW 200608481 A TW200608481 A TW 200608481A TW 094121619 A TW094121619 A TW 094121619A TW 94121619 A TW94121619 A TW 94121619A TW 200608481 A TW200608481 A TW 200608481A
Authority
TW
Taiwan
Prior art keywords
stress
free
substrate
buff
systems
Prior art date
Application number
TW094121619A
Other languages
Chinese (zh)
Other versions
TWI306276B (en
Inventor
Andrew D Bailey Iii
Shrikant P Lohokare
Yun-Sang Kim
Simon Mcclatchie
Original Assignee
Lam Res Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US10/879,598 external-priority patent/US7129167B1/en
Application filed by Lam Res Corp filed Critical Lam Res Corp
Publication of TW200608481A publication Critical patent/TW200608481A/en
Application granted granted Critical
Publication of TWI306276B publication Critical patent/TWI306276B/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02041—Cleaning
    • H01L21/02057—Cleaning during device manufacture
    • H01L21/02068—Cleaning during device manufacture during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers
    • H01L21/02074—Cleaning during device manufacture during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers the processing being a planarization of conductive layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)

Abstract

A method of cleaning a substrate includes receiving a substrate and applying a stress-free cleaning process to the top surface of the substrate. The substrate includes a top surface that is substantially free of device dependent planarity nonuniformities and device independent planarity nonuniformities. The top surface also includes a first material and a device structure formed in the first material, the device structure being formed from a second material. The device structure has a device surface exposed. The device surface has a first surface roughness. A system for stress-free cleaning a substrate is also described.
TW094121619A 2004-06-28 2005-06-28 Methods and systems for a stress-free buff TWI306276B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US10/879,598 US7129167B1 (en) 2003-03-14 2004-06-28 Methods and systems for a stress-free cleaning a surface of a substrate

Publications (2)

Publication Number Publication Date
TW200608481A true TW200608481A (en) 2006-03-01
TWI306276B TWI306276B (en) 2009-02-11

Family

ID=36742910

Family Applications (1)

Application Number Title Priority Date Filing Date
TW094121619A TWI306276B (en) 2004-06-28 2005-06-28 Methods and systems for a stress-free buff

Country Status (3)

Country Link
KR (1) KR101149346B1 (en)
CN (1) CN100479104C (en)
TW (1) TWI306276B (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9211628B2 (en) * 2011-01-26 2015-12-15 Nexplanar Corporation Polishing pad with concentric or approximately concentric polygon groove pattern
CN104170064B (en) * 2012-03-30 2017-05-10 盛美半导体设备（上海）有限公司 Nozzle for stress-free electrochemical polishing

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003051481A (en) 2001-08-07 2003-02-21 Hitachi Ltd Manufacturing method for semiconductor integrated circuit device

Also Published As

Publication number Publication date
KR101149346B1 (en) 2012-05-30
CN100479104C (en) 2009-04-15
TWI306276B (en) 2009-02-11
KR20060048646A (en) 2006-05-18
CN1767155A (en) 2006-05-03

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Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees