TW200608467A - Method for fabricating semiconductor device - Google Patents
Method for fabricating semiconductor deviceInfo
- Publication number
- TW200608467A TW200608467A TW093124836A TW93124836A TW200608467A TW 200608467 A TW200608467 A TW 200608467A TW 093124836 A TW093124836 A TW 093124836A TW 93124836 A TW93124836 A TW 93124836A TW 200608467 A TW200608467 A TW 200608467A
- Authority
- TW
- Taiwan
- Prior art keywords
- semiconductor device
- stress
- fabricating semiconductor
- high stress
- layer
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title abstract 3
- 239000000969 carrier Substances 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823807—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
- H01L29/7843—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being an applied insulating layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/3115—Doping the insulating layers
- H01L21/31155—Doping the insulating layers by ion implantation
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Ceramic Engineering (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Formation Of Insulating Films (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
A method for fabricating semiconductor device is provided. A high stress layer formed above, below or on both side of the transistors of the semiconductor device is employed as a cap layer. A specific region is then defined through photo resistor mask, and the stress of the region is changed by ion implanting. Therefore, compressive stress and tensile stress occur on the high stress layer. According the disclosed method, the high stress layer may simultaneously improve the characteristics of the transistors formed on the same wafer. Further, the mobility of the carriers of the device is enhanced.
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
TW093124836A TWI234188B (en) | 2004-08-18 | 2004-08-18 | Method for fabricating semiconductor device |
US11/018,242 US7033899B2 (en) | 2004-08-18 | 2004-12-22 | Method of making semiconductor devices |
US11/300,481 US7347228B2 (en) | 2004-08-18 | 2005-12-15 | Method of making semiconductor devices |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
TW093124836A TWI234188B (en) | 2004-08-18 | 2004-08-18 | Method for fabricating semiconductor device |
Publications (2)
Publication Number | Publication Date |
---|---|
TWI234188B TWI234188B (en) | 2005-06-11 |
TW200608467A true TW200608467A (en) | 2006-03-01 |
Family
ID=35910154
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW093124836A TWI234188B (en) | 2004-08-18 | 2004-08-18 | Method for fabricating semiconductor device |
Country Status (2)
Country | Link |
---|---|
US (2) | US7033899B2 (en) |
TW (1) | TWI234188B (en) |
Families Citing this family (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2006066611A (en) * | 2004-08-26 | 2006-03-09 | Toshiba Corp | Semiconductor device |
TWI241664B (en) * | 2005-01-14 | 2005-10-11 | Ind Tech Res Inst | Method for fabricating semiconductor device |
FR2890782B1 (en) * | 2005-09-14 | 2008-02-29 | St Microelectronics Crolles 2 | SEMICONDUCTOR DEVICE COMPRISING AT LEAST ONE MOS TRANSISTOR COMPRISING AN ETCH STOPPING LAYER AND CORRESPONDING FABRICATION METHOD. |
KR100865548B1 (en) * | 2006-12-28 | 2008-10-28 | 주식회사 하이닉스반도체 | Method for fabricating semiconductor device |
CN103183307B (en) * | 2011-12-28 | 2016-04-20 | 中国科学院微电子研究所 | Tensile stress LPCVD SiO 2the manufacture method of film |
US9049061B2 (en) * | 2012-03-21 | 2015-06-02 | The Institute of Microelectronics Chinese Academy of Science | CMOS device and method for manufacturing the same |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5556793A (en) * | 1992-02-28 | 1996-09-17 | Motorola, Inc. | Method of making a structure for top surface gettering of metallic impurities |
JPH0969494A (en) * | 1995-08-31 | 1997-03-11 | Texas Instr Japan Ltd | Manufacture of semiconductor device |
JPH113869A (en) * | 1997-06-11 | 1999-01-06 | Nec Corp | Semiconductor device and manufacture thereof |
TWI313059B (en) * | 2000-12-08 | 2009-08-01 | Sony Corporatio | |
JP3494638B2 (en) * | 2002-05-21 | 2004-02-09 | 沖電気工業株式会社 | Semiconductor device and method of manufacturing semiconductor device |
TW200520170A (en) * | 2003-06-06 | 2005-06-16 | Northrop Grumman Corp | Coiled memory device and method of making the same |
-
2004
- 2004-08-18 TW TW093124836A patent/TWI234188B/en not_active IP Right Cessation
- 2004-12-22 US US11/018,242 patent/US7033899B2/en not_active Expired - Fee Related
-
2005
- 2005-12-15 US US11/300,481 patent/US7347228B2/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
US20060094135A1 (en) | 2006-05-04 |
US20060040479A1 (en) | 2006-02-23 |
US7033899B2 (en) | 2006-04-25 |
TWI234188B (en) | 2005-06-11 |
US7347228B2 (en) | 2008-03-25 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
MM4A | Annulment or lapse of patent due to non-payment of fees |