TW200601553A - Memory device having sheided access lines - Google Patents
Memory device having sheided access linesInfo
- Publication number
- TW200601553A TW200601553A TW094115018A TW94115018A TW200601553A TW 200601553 A TW200601553 A TW 200601553A TW 094115018 A TW094115018 A TW 094115018A TW 94115018 A TW94115018 A TW 94115018A TW 200601553 A TW200601553 A TW 200601553A
- Authority
- TW
- Taiwan
- Prior art keywords
- sheided
- transistors
- memory device
- metal layer
- access lines
- Prior art date
Links
Landscapes
- Semiconductor Memories (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Non-Volatile Memory (AREA)
Abstract
An apparatus including, in one embodiment, a plurality of transistors each formed by: (1)at least a portion of one of a plurality of doped regions formed in a substrate; and (2)at least a portion of one of a plurality of first conductors each extending over one of the plurality of doped regions, the plurality of first conductors included in a first metal layer. A second metal layer includes a plurality of second conductors each interconnecting ones of the plurality of transistors. A third metal layer includes a plurality of bit lines each interconnecting ones of the plurality of transistors. A forth metal layer includes a plurality of word lines each interconnecting ones of the plurality of transistors.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US56965804P | 2004-05-10 | 2004-05-10 | |
| US11/007,375 US20050247981A1 (en) | 2004-05-10 | 2004-12-08 | Memory device having shielded access lines |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| TW200601553A true TW200601553A (en) | 2006-01-01 |
| TWI305045B TWI305045B (en) | 2009-01-01 |
Family
ID=35474103
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| TW94115018A TWI305045B (en) | 2004-05-10 | 2005-05-10 | Memory device having sheided access lines |
Country Status (3)
| Country | Link |
|---|---|
| JP (1) | JP2005328052A (en) |
| SG (1) | SG117524A1 (en) |
| TW (1) | TWI305045B (en) |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20090052262A1 (en) | 2006-02-08 | 2009-02-26 | Koji Nii | Semiconductor memory device |
| JP5061490B2 (en) * | 2006-04-06 | 2012-10-31 | ソニー株式会社 | Semiconductor device and manufacturing method thereof |
| US10497402B2 (en) | 2012-03-30 | 2019-12-03 | Taiwan Semiconductor Manufacturing Company, Ltd. | Apparatus for high speed ROM cells |
| US8743580B2 (en) | 2012-03-30 | 2014-06-03 | Taiwan Semiconductor Manufacturing Company, Ltd. | Apparatus for high speed ROM cells |
| US9576644B2 (en) | 2015-04-27 | 2017-02-21 | Taiwan Semiconductor Manufacturing Company, Ltd. | Integrated circuit chip having two types of memory cells |
-
2005
- 2005-03-16 SG SG200501611A patent/SG117524A1/en unknown
- 2005-05-10 JP JP2005137300A patent/JP2005328052A/en active Pending
- 2005-05-10 TW TW94115018A patent/TWI305045B/en active
Also Published As
| Publication number | Publication date |
|---|---|
| JP2005328052A (en) | 2005-11-24 |
| TWI305045B (en) | 2009-01-01 |
| SG117524A1 (en) | 2005-12-29 |
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