200588 經濟部屮央標準局CX工消费合作社印51 Λ fi η () 五、發明説明（） 本發明係有關於一種並聯式唯讀記憶體裝置特別是 指一種可利用複晶矽及埋層間之適當連接，配合資料碼之 植入位置，以簡化製积控制之具選擇線的髙密度並聯式唯 讀記憶體裝置。 傳桃光單式僅讀記憶體（MASK ROM )均以離子植入方 式來決定所櫧存的資料碼（C0IH:)。其細胞架構計分成並 聯式，串聯式及串聯益聯合併式。並聯式架構的優，點在於 資科碼離子植入步驟位於製造流租後段，故在使用者定義 .其資料碼至廠方交貨期間較短。但冈平均每兩個細胞即需 —個金屬接觸窗（MBTAL CONTACT)，以連接位元線（BIT I'INB )，使得等效細胞雨積（ΒΡΡ|，χΊΊνΒ ca|…S|zh:)増大 ，製造成本無法降低；申聯式及串聯並聯合併式可一机多 個細胞共用一個金屬接觸窗，两此等效細胞雨積較串聯式 小得多，但是冈爲資料碼離子植入步驟位於製租前段，交 貨期較並聯式長約兩倍。 以上三個傳統的光單式僅讀記憶體的細胞架構均需以 場區氧化層（pmj οχιιπ:)作爲細胞主動層（ACTivl·:)間的 隔離。但積體電路的佈局规則（u丫out 卜:）中，主動層 間距（ACΊΊVBP丨TCH)受限於場區氡化層產生的鳥嘴（Bmv S BRAK)，無法用最小尺寸來設計。例如在()_8微米的佈 局规則中，最小間距可達1,Η微米（0.8微米寬度+ ().«微 米距離），而主動層間距則需2,2微米（().8微米寬度+ 1,4 微米距離）兩者相差1.375倍。任何唯讀記憶體結構的最 佳化原則均相同，即密度最大，j_製程簡單，使良率提高 第03頁 本紙張尺度逍用中B B家橾準(CNS) ψ 4規格(210 X 2137公址) (請先閲讀背而之注意事項*项寫本页) 裝- 線. 200588 A (i It (i 經濟部屮央標準局员工消赀合作杜印製 五、發明説明（） 1 ,冈此許多廠家即相雉投入改良唯讀記憶體研發設計之行 中。 習用唯讀記憶體中，亦曾有一種髙密度之細胞結構設 計，請參聞第一圖，係一種習用高密度之唯讀記憶體之電 5 路結構圖，其中計埋層1 、3 、5間之絕緣，係藉由離子 植入區7而達成，此離子植入區7常丙爲植入後的擴散問 題，造成轉換閘（transfer gate)之寬度減小，甚而完全 爲離子擴散而切斷，闶此，在製积中之控制必須相當嚴格 .，否則良率會降低，同時，小的轉換閘寬度，將導致電流 10 變小，而影饗到存取迷率，JI-,金屬9之45度拉線處理方 式，增大了金屬在X軸佔用空間，將會降低唯讀記憶體密 度。 業界爲了降低位元線上之電容負載，皆以選擇線的方 式，以形成多個記憶區塊，選擇線上的絕緣方法有許多種 15 ，—種即如上述使用離子植入的方式爲之，但離子的擴散 控制不易，另一種則係使用習用場區氧化層作爲絕緣，但 產生的鳥嘴，造成密度的降低，及通道寬度的縮減，其只 不過爲商業償値上之考量，對於上所述及一些基本的問題 仍無法解決。 20 有艦於此，本發明人基於習用並聯式唯讀杞憶體之結 構，存取速度不穩定的問題，及製租控制的複雜积度限制 之下，難稱完善，致使並聯式唯讀記憶體之功效及性能無 法發揮，冈而本著創新突破，精益求精的研發精神，終於 研究出一種具選擇線的高密度並聯式唯讀記憶體裝置，俾 第頁 本紙張尺度通用中Η B家樣準(CNS) 規格（210X297公址） (請先間讀背而之注意事項再本頁) 裝. .1Τ* 線- 200588 Λ fi l\() 經濟部中央#準局员工消费合作社印製 五、發明説明（） 1 能彌補習用於上所述及之缺憾。 即，本發明之主要目的，在於提供一種具選擇線的高 密度並聯式唯讀記憶體裝置，其擁有並聯式的優點，交貨 期短，密度高，製租控制簡單，可使得製造良率亦極高 5 者。 緣是，爲達成上述之目的，本發明具選擇線的高密度 並聯式唯讀記憶體裝置，係爲一種具柱狀選擇線的'並聯式 僅讀記憶體細胞架構，其主要特徵，係爲該選擇線更包括 ，一複晶矽延伸區，其延伸至上述之金屬接觸區中，與該連 10 接埋層相連，該連接埋層亦包栝一延伸埋層區，延伸至其 上下方之記憶區塊，與該兩記愫區塊上，相鄰於該連接埋 層之兩選擇線之複晶矽相連，以形成轉換閘，配合資料碼 之植入位置，將部分不必要的轉換閘植入資料碼使其斷路 ，即可達成本發明製程控制十分簡單的主要目的。 15 本發明之其它目的、優點及特徵，可由以下較佳實施 例所作之詳細説明並配合圖示，而獲得進一步之瞭解。 第一围係一種習用高密度之唯讀記憶體之電路結構圖 Ο 第二圖係本發明具選擇線的高密度並聯式唯讀記檍體 20 裝置中埋層N+的佈局圖。 第三圖係本發明具選擇線的高密度並聯式唯讀記憶體 裝置中細胞電晶體的剖面結構圖。 第四圈係本發明具選擇線的高密度並聯式唯讀記憶體 裝置中埋層N+與複晶矽所構成並聯式細胞架構 第05頁 本紙5S：尺度逍用中a a家標準（CNS)肀4規格（210X297公釐） (請先間讀背而之注意事項再構寫本頁) 200588200588 Printed by CX Industrial and Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs 51 Λ fi η () V. Description of the invention () The present invention relates to a parallel read-only memory device, in particular, it can be used between polycrystalline silicon and buried layers. Appropriate connection, with the implantation position of the data code, to simplify the high-density parallel read-only memory device with selective lines for production control. Chuantaoguang's single-read only memory (MASK ROM) uses ion implantation to determine the stored data code (C0IH :). Its cell architecture is divided into parallel, tandem and tandem benefits. The advantage of the parallel architecture is that the Zike code ion implantation step is located in the back stage of manufacturing flow rent, so the period from the user-defined data code to the factory delivery is short. However, on average, every two cells need a metal contact window (MBTAL CONTACT) to connect the bit line (BIT I'INB), so that the equivalent cell rain product (ΒΡΡ |, χΊΊνΒ ca |… S | zh :) Larger, the manufacturing cost can not be reduced; Shenlian type and series parallel parallel type can share a metal contact window for multiple cells in one machine, the equivalent rain cell of the two cells is much smaller than that of the series type, but Gangwei is the data code ion implantation step Located in the front section of rent-making, the delivery time is about twice as long as the parallel type. The above three traditional optical single-read-only memory cell architectures need to use the field oxide layer (pmj οχιιπ :) as the isolation between the active layers of cells (ACTivl · :). However, in the layout rule of the integrated circuit (uyaout bu :), the active layer spacing (ACΊΊVBP 丨 TCH) is limited by the bird's beak (Bmv S BRAK) generated by the radon layer in the field area, and cannot be designed with the smallest size. For example, in the layout rule of () _8 microns, the minimum spacing can reach 1, Η microns (0.8 microns width + (). «Micron distance), while the active layer spacing needs 2,2 microns (() .8 microns width + 1,4 microns distance) The difference between the two is 1.375 times. The optimization principle of any read-only memory structure is the same, that is, the density is the largest, the j_ process is simple, and the yield is improved. The paper size of page 03 is used in the BB family standard (CNS) ψ 4 specifications (210 X 2137 (Public address) (please read the notes on the back of the first * item to write this page) Installed-line. 200588 A (i It (i Ministry of Economic Affairs, Bureau of Standards, Employee Consumers, cooperation, du printing 5, invention description () 1, Many manufacturers of this kind, Pheasant Pheasant, are investing in the development of improved read-only memory. In conventional read-only memory, there was also a high-density cell structure design, please refer to the first picture, which is a traditional high-density memory. The read-only memory electrical structure diagram of the 5-way, in which the insulation between the buried layers 1, 3, and 5 is achieved by the ion implantation area 7, which is often a diffusion problem after implantation , Causing the width of the transfer gate to be reduced, and even being completely cut off for ion diffusion. The control of the production must be quite strict. Otherwise, the yield will be reduced, and at the same time, the width of the small transfer gate, Will cause the current 10 to become smaller, which will affect the access fan rate, JI-, metal 9 to 45 degrees The wire processing method increases the space occupied by the metal on the X axis, which will reduce the density of the read-only memory. In order to reduce the capacitive load on the bit line, the industry uses the method of selecting lines to form multiple memory blocks. There are many kinds of insulation methods15, one is to use ion implantation as mentioned above, but the diffusion control of ions is not easy, and the other is to use the conventional field oxide layer as insulation, but the resulting bird's beak causes density The reduction of the width and the reduction of the width of the channel are just considerations for commercial compensation, and they still cannot solve the above-mentioned and some basic problems. 20 There are ships here, the inventor based on the traditional parallel type The structure of the system, the problem of unstable access speed, and the complexity of the rental control are difficult to be perfect, so that the efficiency and performance of the parallel read-only memory cannot be exerted, and in the spirit of innovation breakthroughs, excellence The spirit of research and development has finally developed a high-density parallel read-only memory device with a selection line, which is in accordance with the standard of the HB home standard (CNS) in the paper standard on the first page. (210X297 public address) (please read the back-to-back precautions and then this page) Installed. .1Τ * Line-200588 Λ fi l \ () Printed by the Ministry of Economic Affairs Central #Public Bureau Employee Consumer Cooperative V. Description of invention () 1 can make up for the shortcomings mentioned above. That is, the main purpose of the present invention is to provide a high-density parallel read-only memory device with a selection line, which has the advantages of parallel type, short delivery time, High density and simple rent control, which can make the manufacturing yield extremely high. The reason is that, in order to achieve the above purpose, the high-density parallel read-only memory device with a selection line of the present invention is a columnar The main feature of the selection line's parallel read-only memory cell architecture is that the selection line further includes a polycrystalline silicon extension area that extends into the metal contact area described above and is connected to the connection 10 buried layer The connection buried layer also includes an extended buried layer area, which extends to the upper and lower memory blocks, and is connected to the polysilicon adjacent to the two selection lines of the connection buried layer on the two memory blocks. In order to form a switching gate, with the implantation position of the data code, Unnecessary portions of code data allowed implant transfer gate circuit, the present invention is to achieve a simple process control is the main purpose. 15 Other objects, advantages and features of the present invention can be further understood by the detailed description made in the following preferred embodiments and the accompanying drawings. The first enclosure is a circuit structure diagram of a conventional high-density read-only memory. The second diagram is a layout diagram of a buried layer N + in a device of a high-density parallel read-only memory with select lines according to the present invention. The third figure is a cross-sectional structure diagram of a cell transistor in a high-density parallel read-only memory device with select lines of the present invention. The fourth circle is the parallel cell architecture formed by the buried layer N + and the polycrystalline silicon in the high-density parallel read-only memory device with selective lines of the present invention. Page 05: 5S: The standard aa family standard (CNS) 4Specifications (210X297mm) (Please read the notes before you write this page) 200588
Λ G HG 10 15 部 中 央 標 準 局 员 工 消 合 作 社 印 製 20 五、發明説明（） 的等效電路圖。 第五阖係本發明具選擇線的高密度並聨式唯讀記檍體 裝置中選擇線的佈局闽。 第六圖係本發明具選擇線的高密度並聯式唯讀記愫體 1 裝置中選擇練之等效電路圖。 第七圖係本發明具選擇線的高密度並聨式唯讀記憶體 裝置之等故電路圖。 ’ 笫八阅係本發明具選擇線的高密度並聯式唯讀記憶體 . 裝置經簡化後之電路圖。 第一表係本發明具選擇線的高密度並聯式唯讀記憶鱧 裝置讀取資料時訊號之狀態列表。 本發明採用埋層N+來形成細胞的汲極及源極，埋層N+ 由光阻定義形狀，再經砷（ARSBN 1C)植入形成，無需以場 區氧化層隔離，故間距可使用作局規則中最小尺寸來設計 ’以達到高細胞密度的g的，於此首先説明埋層N+並聯式 架構的佈局及工作原理，請參闖第二圖，係本發明具選擇 線的高密度並聯式唯讀記憶體裝置中埋層N+的佈局圖，其 中，ΊΊ是一個細胞電晶體；由丨儿·!及兩條縱向埋層…， 與WU —條橫向的複晶矽埋層（P()|/YiS丨丨/IC()N)垂直交又形 成。在第二闽中，標示A及B所在的埋層N+ ,即埋層N+與 複晶矽重疊的部分，是ΊΊ的没極與源極，標示〇的複晶矽 爲ΊΊ的閘極，埋層N+與複晶矽重疊處以氧化層隔絕避免 埋層叶與複晶矽短路，T1的剖雨結構如第三阖所示其中 複晶矽11係藉由氧化層1ϋ,使與埋層13隔離；第二圖中， _ 第頁 本《張尺度逍用中國B家標準(CNS) Ή規格（210X297公处） (請先閲讀背而之注意事吲再项寫木/|) 裝· 線. 200588 Λ fi \\β 五、發明説明（） (請先閱讀背而之注意事項"項寫本页) 1 細胞電晶體τι、T2及便以埋層N+與及BL2共同形成 並聯的架構。 細胞電晶體的臨界電壓由是否經過資料瑪硼植入決定 ，經資料碼硼植入的細胞電晶體，其臨界電壓高於電路中 5 的高電位，是爲"高臨界電壓"；若細胞電晶體未經資料 碼硼植入，則其臨界電壓會低於髙電位，但仍然髙於低電 位，是爲M低臨界電壓"。 ’ 請參閲第四圖，係本發明具選擇線的高密度並聯式唯 •讀記憶體裝置中埋層N+與複晶矽所構成並聨式細胞架構的 10 等效電路阐，在讀取'门所儲存之資料時，位元線BL1處於 低電位，即0伏特電位，而位元線ΒΙ/2處於高電位，BU 及14則需浮接（卜'LOATINO),同時字元線（WORD UN卜：） WIZ2及WL3需處於低電位，使得細胞電晶體Ί'2及T:；{關閉， 而T1所處之字元線WL1則爲高電位；若T1爲"低臨界電蜃" 15 ，則T1爲導通狀態，電流由丨化2流經ΊΊ再流入BL1 ,此時 Tt所儲存的資料爲，若ΊΊ爲高臨界電壓__ T1爲關閉 狀態，及BIZ2之間無電流通過，此時所儲存之資料 爲1Ί", 及BL4的浮接，可避免BL2經T4、t5的漏電 經濟部屮央標準局KX工消费合作社印製 流，而將資料"Γ誤讀爲"()"〇 20 由於埋層N+的薄片電阻（S Η K RT R卜XS丨ST A NC B)約爲fK) 至U)()欧姆，較金屬的薄片電限高數千倍，故須用金屬導 線與埋層N+並聯，以降低位元線的電阻負載，通常以16條 成W條字元線爲一區塊（BLOCK),區塊與區塊間做一金屬 接觸窗，使埋層N+與金屬導線並聯。 _ f U7頁 本紙張尺度逍用中8國家樣準(CNS) 規格(210x297公址) 經濟部屮央榣準局员工消f合作社印51 200588 五、發明説明（） 但，這樣的設計仍然會遭遇到兩個問題： (1) .每條埋層M+均需以金屬導線並聯，而金屬接觸窗的間 距較埋層M+爲大，將成爲提髙細胞密度的瓶頌。 (2) .應用於高容量的僅讀記憶器時，埋層將並聯數千個 細胞電晶體，因此埋層N+的接面電容(JUNCTION CA-PAC丨TANCB)相當大，電路執行迷度將受到相當大的影 響〇 , 本發明在金屬接觸窗與區塊間增設選擇線，使未被遘 •擇的區塊内的埋層N+與位元線隔絕，以大幅降低位元線的 電容負栽，請參閱第五圖，係本發明具選擇線的高密度並 聯式唯讀記憶體中遘擇線的佈局圏，並請配合參閱第六圈 ，係爲其等效電路圖。第五圖中，SU)爲選擇線，ΗΊΊ及 HT2兩個電晶體爲水平方向的選擇器；VT1爲垂直方向的 選擇器，ΡΊΊ及PT2則爲寄生的電晶體（PAIiASmc TRAM-SISTBR)，寄生電晶體的消除方法是利用資料碼硼植入時 ，.同及PT2作植入，使Ρ'ΓΙ 、PT2成爲"高臨界 電壓"的電晶體，形同斷路，寄生電晶體的硼植入佈局规 則與資料碼硼植入完全相同，故製租不受影響，相鄰的選 擇線SU的佈局係由SU)對X軸作鏡像（ίΛΙΙί(Η)ΙΟ，再往水 平方向平移兩個埋層Ν+間距而成|同時每隔一條埋層Ν+ , 方以金屬導線並聨，即金屬接觸窗個數爲埋層Ν+條數的一 半，冈此埋層Ν+間距可以最小尺寸來設計。 俾使貴審査委員能對本發明之資料存取動作，能有更 進一步之瞭解與確認，請參閱第七圖，係本發明具選擇線 _ 第U8頁 本紙張尺度遑用中8Β家標準(CNS)IfM規格(21〇χ297公址) (請先間讀背而之注意和項孙项寫本頁) '裝- 訂_ 200588 Λ Γ) η (> 五、發明説明（） 10 15 部 屮 央 樑 準 局 A 工 消合 作社 印 20 的高密度並聯式唯讀杞檍體裝置之等效電路圖，其中BU 、BI/2爲位元線，VG1 、VG2及VG3稱爲虚擬接地（VIRTUAL· GROUNIV), 每條位元 線可讀取四 机並聨細胞電 晶鞭所 儲存的資料，我們以位元線BL1讀取字元線Wl,7上ΊΊ、’丨7 、T:：{及T4四個細胞電晶體所儲存資料時，其動作如下迷： 1.讀取ΊΊ:位元線保持高電位，虚擬接地線VG1接地 ,V(;2、VQ及BL2浮接，ΊΊ所在的字元線 W L7保持高電位，其餘字元線保持低電位，遘 , 擇線SU)處於高電位，使SU)上的選擇器爲導 通狀態，其餘選擇線則保持低電位；此時，埋 層Ν+ΒΝϋ經由已導通的選擇器ST0與VG1接通 ，ΒΝ1則經由ST1與HU接通，由於選擇線 SU爲低電位，故BU與V(;l間不會經s’|'4導 通，換言之，細胞電晶體ΊΊ的汲極連接位元線 Βϋ，源極連接VG1而接地，其簡化後之電路 圖如第八闽所示，若ΊΊ爲"高臨界電壓"，則 資料爲Ί ，若Τ1爲"低臨界電壓_· ^則資料 爲"()"。 . 2 .讀取丨2:選擇線SIZZ處於高電位，$ 保待低電位，其 餘接法與讀取ΊΊ的接法相间，埋層Ν+ΒΝ2經由 ST5與BU接通，則經由ST4與VG1接诵 ，因此，細胞電晶體Τ2的及極被迷接至位元線 ,源極連接VG1 。 3.讀取虚掇接地線VG2接地，VG1浮接，選擇線、υ (請先閱讀背而之：^意^項再岈寫本灯) 線- 第頁 本紙》尺度边用中《國家楳#(CNS) f 4規格（2】0 X 297公;) 2〇〇588 Λ β η β 五、發明説明（） (請先閱請背而之注意事項孙项寫本頁) 1 處於高電位，保持低電位，其餘接法與讀 取ΊΊ的接法相同，埋層Ν+ΒΝ2經由ST5與队】 接通，BM3則經由STfi與VG2接通，細胞電晶 號丫3的现極被連接至位元|pU，源極連接 5 VG2 〇 4_讀取ΊΜ:虚擬接地線V{;2接地，v(;1浮接，其餘接法與 讀取ΊΊ的接法相同，埋層N+BN3經A S1'2與 接通，川4則經由ST3與V(;2接通，細胞 • 電晶體Ί'4的没極被連接至位元線,源極速 10 接VG2 〇 以上四侗動作整理後如表一，其中"Η"表高電位，而 "丨'"表低電位，至於"卜'__則表示浮接，歸納其結果得知， 選擇線SL2可讀取靠BU内侧的兩個細胞電晶體Τ2、Ί'3, 、SI'()則讀取BU外侧的兩個細胞電晶體以、，'4, ν(;1與 15 VG2擇其—接地，則決定BL1的左侧電晶體τΐ、Τ2被讀取 成右侧電晶嫌T3、T4被讀取。 經濟部屮央摞準局A工消t合作社印製 同爲該選擇線的設計，j_該選擇線机儿()-、SU中，在 某一存取時間中，只有其中一條選擇線爲·_Η··,使得在進 行存取動作時，具有一條遘擇線爲的杞愫區塊方會被 扣 啓動，其餘區塊則冈爲選擇器STn切斷而與位元線呈斷路 狀態，使得該存取位元線上之電容負載變小，存取速度冈 而加快。 而本發明之主要特徵，係於選擇線上所突伸至金屬接 觸窗下方N+埋層之複晶矽區域，以及相鄰金屬接觸窗下N+ 第i〇頁 本紙張尺度遑用中B Η家標準(CNS)甲4規格(210X297公*) 2〇〇588 Λ β |{() 五、發明説明（） 10 15 經 濟 部 屮 央 樣 準 局 工 消 费 合 作 社 印 製 20 方坦層延伸i上述邐擇皞上之坦層區域，請回頭參閱第五 圖；選禪線‘S丨所延伸出之複晶矽區域51,連接至金屬接 觸窗52下方之N+埋層5:：{，形成三個電晶體VT1、m及π、2 ，其中ΡΤ1及ΡΊ7藉由硼植入而形同斷路，不具任何作用 ,而與上述金屬接觸窗52相鄰之金屬接觸窗54,其下方之 Ν+埋層Η延伸至選擇線SU)之區域，亦形成兩電晶體ΗΤι 及HT2，上述經由特硃延伸設計所形成之電晶磕VT1、ΗΊΊ 及m，即爲轉換閘所形成之選擇器STn ,在製程控制上 ，不會冈爲資料碼硼植入後之擴散作用，造成選擇器VT1 、ΗΊΊ或HT2之通道寬度縮減，雖然因爲延伸部分，而在 圖示上略覺佔用面積增加，但實際上其與龐大的資料做存 空間相較，實微乎其微，並不會影響到儲存密度，反而藉 由上述延伸部分的設計，可使得製租上之控制簡化許多， 良率提高，不再冈爲設計上之不當，造成轉換閘之寬度大 小不一，小則使某部分記憶空間的資料存取連度減慢，大 則甚至導致無法£常作用，爲了提高記憶密度而造成如此 嚴重的結果，實爲不値。 職是，本發明具選擇線的高密度並聯式唯讀記憶體裝 置，藉所作之揭露，確能顯出以下優點：擁有高密度及並 聯式唯讀記憶的所有的優點，又冈其製积控制相當簡單， 故品質穩定，良率高。 綜上所述，本發明確可藉所揭羃之觀念，經實作確能 達到預期之目的，J·本案於申請前並未見於刊物成公開使 用，於同類產品中，堪稱首創，符合專利法所述新穎1實 本紙張尺度通用中a國家楳準(CNSMM規格(210X297公址） 裝· 訂_ 線 2〇〇58β Λ 6 It 6 五、發明説明（ 用之精神，並已達到產業上實施之階段，爰侬法提出發明 之專利申請，懇請惠予審査，並祈早賜發明專利爲禱。 惟，以上所述者，僅爲本發明之較佳實施例，大凡熟 悉此项技藝之人士，利用本發明之精神所做成之各種變化 ，仍應包含於本案牟利範園之内。 (請先閲讀背而之注&杯项孙填对木饤) 10 15 經濟部屮央榣準局貝工消伢合作杜印製 20 第頁 本紙張尺度边用中困國家《準(CNS) f 4規格（210X297公龙）Λ G HG 10 15 Printed by the Central Standards Bureau Staff and Consumers Cooperative Society 20. Equivalent circuit diagram of invention description (). The fifth aspect is the layout of the selection line in the high-density and read-only memory device with selection lines of the present invention. The sixth figure is the equivalent circuit diagram of the selective training in the high-density parallel-type read-only memory device 1 with the selection line of the present invention. The seventh figure is an equivalent circuit diagram of the high-density parallel read-only memory device with select lines of the present invention. The first eight readings are the high-density parallel read-only memory of the present invention with a selection line. The simplified circuit diagram of the device. The first table is a state list of signals when the high-density parallel read-only memory device with a selection line of the present invention reads data. In the present invention, the buried layer N + is used to form the drain and source of the cell. The buried layer N + is defined by the photoresist and then implanted with arsenic (ARSBN 1C). It does not need to be isolated by the field oxide layer, so the spacing can be used as a local The minimum size in the rules is designed to achieve high cell density g. Here we first explain the layout and working principle of the buried layer N + parallel architecture, please refer to the second figure, which is the high density parallel type of the present invention with a selection line The layout diagram of the buried layer N + in the read-only memory device, where ΊΊ is a cell transistor; by !! and two vertical buried layers ..., and WU—a horizontal polycrystalline silicon buried layer (P () | / YiS 丨 丨 / IC () N) Vertical intersection is formed again. In the second Fujian, the buried layer N + where A and B are located, that is, the part where the buried layer N + overlaps with the polycrystalline silicon is the source and the source of the ΊΊ, and the polycrystalline silicon marked 〇 is the gate of the ΊΊ, buried The overlap between layer N + and polycrystalline silicon is insulated with an oxide layer to avoid short circuit between the buried leaf and polycrystalline silicon. The rain-shedding structure of T1 is shown in the third section. Polycrystalline silicon 11 is isolated from buried layer 13 by oxide layer 1 ; The second picture, _ the first page of this book "Zhang Scale Xiao uses the Chinese B family standard (CNS) Ή specification (210X297 public office) (please read the notes on the back then write the wood / |) installation and line. 200588 Λ fi \\ β 5. Description of the invention () (please read the back-end notes " item to write this page) 1 Cell transistors τι, T2 and the buried layer N + and BL2 together form a parallel structure. The critical voltage of the cell transistor is determined by whether it is implanted with data boron. The critical voltage of the cell transistor implanted with data code boron is higher than the high potential of 5 in the circuit, which is "high critical voltage"; if If the cell transistor is implanted without the data code boron, the critical voltage will be lower than the high potential, but it is still low at the low potential, which is the M low critical voltage ". 'Please refer to the fourth figure, which is a 10 equivalent circuit diagram of the parallel cell structure formed by the buried layer N + and polycrystalline silicon in the high-density parallel read-only memory device of the present invention with a selection line. 'In the data stored in the gate, the bit line BL1 is at a low potential, that is, 0 volt potential, and the bit line BII / 2 is at a high potential, and BU and 14 need to be floating (Bu'LOATINO), while the word line ( WORD UN Bu :) WIZ2 and WL3 need to be at a low potential, so that cell transistors Ί'2 and T :; {off, and the word line WL1 where T1 is located is a high potential; if T1 is " low critical electromagnetism " 15, T1 is in the on state, and the current flows from Y2 to Y1 and then into BL1. At this time, the data stored in Tt is, if Y is the high critical voltage __ T1 is off, and there is no current between BIZ2 Through, the data stored at this time is 1Ί ", and the floating connection of BL4, can avoid BL2 printed by T4, t5 leakage of the Ministry of Economics, Central Standards Bureau KX Industrial and Consumer Cooperative printed stream, and misread the data " Γ " () " 〇20 Since the sheet resistance of the buried layer N + (S Η K RT R Bu XS 丨 ST A NC B) is about fK) to U) () Ohm, more metal The chip power limit is several thousand times higher, so it is necessary to use metal wires in parallel with the buried layer N + to reduce the resistance load of the bit line, usually 16 into W word lines as a block (BLOCK), block and block A metal contact window is formed between the buried layer N + and the metal wire in parallel. _ f U7 pages of this paper are used in the 8 National Sample Standards (CNS) specifications (210x297 public address). The Ministry of Economic Affairs, the Ministry of Economic Affairs, the Ministry of Economic Affairs, the Employee Service Cooperative Printed 51 200588 V. Description of the invention () However, this design will still be Encountered two problems: (1). Each buried layer M + needs to be connected in parallel with metal wires, and the distance between the metal contact windows is larger than the buried layer M +, which will become a bottleneck to increase the density of high cells. (2). When applied to a high-capacity read-only memory, the buried layer will be connected in parallel with thousands of cell transistors, so the junction capacitance of the buried layer N + (JUNCTION CA-PAC 丨 TANCB) is quite large, and the circuit implementation will be complicated. It is greatly affected. The invention adds a selection line between the metal contact window and the block to isolate the buried layer N + in the unselected block from the bit line to greatly reduce the negative capacitance of the bit line Please refer to the fifth figure, which is the layout of the selective lines in the high-density parallel read-only memory with selective lines of the present invention, and please refer to the sixth circle for their equivalent circuit diagrams. In the fifth picture, SU) is the selection line, the two transistors ΗΊΊ and HT2 are the selectors in the horizontal direction; VT1 is the selector in the vertical direction, ΡΊΊ and PT2 are the parasitic transistors (PAIiASmc TRAM-SISTBR), parasitic The elimination method of the transistor is to use the data code for boron implantation. The same as PT2 for implantation, so that Ρ'ΓΙ and PT2 become "high critical voltage" transistors, which are the same as open circuit, boron implantation of parasitic transistors The layout rule is exactly the same as the data code boron implantation, so the rental is not affected. The layout of the adjacent selection line SU is mirrored by the SU) on the X axis (ίΛΙΙί (Η) ΙΟ, and then translates two horizontally The buried layer N + spacing is formed | At the same time, every other buried layer N + is surrounded by metal wires, that is, the number of metal contact windows is half of the buried layer N +, and the buried layer N + spacing can be the smallest size To design, so that your review committee can access the data of the present invention for further understanding and confirmation, please refer to the seventh figure, which is the selection line of the present invention _ page U8 Standard (CNS) IfM specification (21〇χ297 public address) (please read back and forth Yihe Xiang Sun Xiang wrote this page) 'Set-up _ 200588 Λ Γ) η (> V. Description of invention) 10 15 High-density parallel-type read-only Qi of Liangyang Bureau of Industry and Commerce Co., Ltd. 20 Equivalent circuit diagram of the oscillating device, where BU, BI / 2 are bit lines, VG1, VG2 and VG3 are called virtual ground (VIRTUAL · GROUNIV), each bit line can read four machines and cell whip For the stored data, when we read the data stored on the four cell transistors on the word line W1,7 on the bit line BL1, ΊΊ, '丨 7, T :: {and T4, the action is as follows: 1. Take ΊΊ: the bit line remains high, the virtual ground line VG1 is grounded, V (; 2, VQ and BL2 are floating, the word line W L7 where ΊΊ is located remains high, and the remaining word lines remain low, select Line SU) is at a high potential, so that the selector on SU) is turned on, and the remaining selection lines are kept at a low potential; at this time, the buried layer N + BN is connected to VG1 through the turned-on selector ST0, and BN1 is passed through ST1 Connected to HU, because the selection line SU is at a low potential, so BU and V (; l will not be conducted through s '|' 4, in other words, the drain of the cell transistor ΊΊ Connect the bit line Bϋ, the source is connected to VG1 and grounded. The simplified circuit diagram is as shown in the eighth Fujian. If ΊΊ is " high critical voltage ", then the data is Ί, if Τ1 is " low critical voltage_ · ^ The data is " () ". 2. Reading 丨 2: Select line SIZZ is at high potential, $ to be kept at low potential, the rest of the connection method is different from the connection method of reading ΊΊ, buried layer Ν + ΒΝ2 When it is connected to BU via ST5, it is read to VG1 via ST4. Therefore, the sum of the cell transistor T2 is connected to the bit line, and the source is connected to VG1. 3. Read the virtual ground wire VG2 ground, VG1 floating, select the line, υ (please read the back first: ^ meaning ^ item and then write the lamp) line-the page of the paper "standard side use" 国 楳 # (CNS) f 4 specifications (2) 0 X 297 g;) 2〇〇588 Λ β η β V. Description of invention () (please read the notes to the contrary, please write this page by Sun Xiang) 1 at high potential, Keep the potential low, the remaining connection is the same as that of reading ΊΊ, the buried layer N + BN2 is connected to the team via ST5, BM3 is connected to VG2 via STfi, and the current electrode of the cell crystal Y3 is connected to Bit | pU, source connection 5 VG2 〇4_Read ΊΜ: virtual ground line V {; 2 ground, v (; 1 floating connection, the remaining connection is the same as the method of reading ΊΊ, buried layer N + BN3 After A S1'2 is turned on, Sichuan 4 is turned on via ST3 and V (; 2, the electrode of the cell • transistor Ί'4 is connected to the bit line, and the source speed is 10 connected to VG2. Four or more Dong actions are organized The following is shown in Table 1, where " Η " indicates a high potential, while " 丨 '" indicates a low potential, and " Bu' __ means floating, and the results are known. The selection line SL2 can be read by The two cell transistors inside the BU Τ2, Ί'3, and SI '() read the two cell transistors on the outside of the BU, and,' 4, ν (; 1 and 15 VG2 choose it-ground, then determine the left transistor τl, Τ2 of BL1 is It is read that the right side transistors T3 and T4 are read. Printed by the Ministry of Economic Affairs, the Central Bureau of Industry and Commerce, A Gongxiaot Cooperative, the same design for the selection line, j_the selection line machine ()-, SU In a certain access time, only one of the selection lines is · _Η ··, so that when the access operation is performed, the block with the selected line will be deactivated and the remaining blocks will be activated. The selector STn is cut off and is in a disconnected state with the bit line, so that the capacitive load on the access bit line becomes smaller and the access speed is accelerated. The main feature of the present invention is that the selection line protrudes to The polycrystalline silicon area of the N + buried layer under the metal contact window, and the N + page i〇 under the adjacent metal contact window. The size of the paper is in the middle of the B family standard (CNS) A 4 specification (210X297 public *) 2〇588 Λ β | {() Fifth, the description of the invention () 10 15 Printed by the Ministry of Economic Affairs, Pyongyang Provincial Bureau of Industry and Consumer Cooperatives 20 Fangtan layer extension i The above-mentioned choices Area, please refer back to the fifth picture; the polycrystalline silicon area 51 extending from the selected Zen line 'S 丨 is connected to the N + buried layer 5 under the metal contact window 52: {, to form three transistors VT1, m and π, 2, where PT1 and ΡΊ7 are similarly disconnected by boron implantation, without any effect, and the metal contact window 54 adjacent to the metal contact window 52 above, the N + buried layer H below it extends to the selection line SU ) Area, two transistors HT1 and HT2 are also formed. The above-mentioned electrical transistors VT1, ΗΊΊ and m formed by the special Zhu extension design are the selector STn formed by the switching gate. It is the diffusion effect of the data code after the implantation of boron, which causes the channel width of the selector VT1, ΗΊΊ or HT2 to be reduced. Although the occupied area is slightly increased on the icon due to the extension, it is actually stored with huge data. Compared with the space, it is very small, and it will not affect the storage density. Instead, the design of the above-mentioned extensions can make the control of rent-making more simplified, the yield is improved, and it is no longer due to improper design, resulting in the transfer gate. The width is different, small It will slow down the data access of a certain part of the memory space, and even cause it to become unusable. In order to increase the memory density, such a serious result is really not good. The title is that the high-density parallel read-only memory device with selective lines of the present invention, through the disclosure, can indeed show the following advantages: having all the advantages of high-density and parallel read-only memory, and its production The control is quite simple, so the quality is stable and the yield is high. In summary, the present invention can indeed achieve the intended purpose by implementing the concepts disclosed. J. This case was not seen in the publication before the application for public use. It is the first of its kind in the same kind of product, which is in line with The novel 1 described in the Patent Law. The standard paper size is generally used in a national standard (CNSMM specification (210X297 public address). Installation and ordering_line 2〇〇58β Λ 6 It 6 V. Description of invention (spirit used, and has reached the industry At the stage of implementation, the Yunnong Law filed a patent application for inventions, pleading for examination, and praying for the invention patent as a prayer. However, the above are only preferred embodiments of the present invention, and are generally familiar with this skill Those who use the spirit of the present invention to make various changes should still be included in the profit-making fan garden of this case. (Please read the note to the back & Cup item Sun fill to Mu Ji) 10 15 The Ministry of Industry and Fisheries cooperated with Du Du to print the 20th page of this paper, and used it in the middle of the troubled country, Standard (CNS) f 4 (210X297 male dragon)