TW200541026A - Light emitting diode package structure and manufacturing process thereof - Google Patents

Light emitting diode package structure and manufacturing process thereof Download PDF

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Publication number
TW200541026A
TW200541026A TW093115910A TW93115910A TW200541026A TW 200541026 A TW200541026 A TW 200541026A TW 093115910 A TW093115910 A TW 093115910A TW 93115910 A TW93115910 A TW 93115910A TW 200541026 A TW200541026 A TW 200541026A
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Taiwan
Prior art keywords
emitting diode
light
layer
ball
connection pads
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TW093115910A
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Chinese (zh)
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TWI243458B (en
Inventor
Cheng-Yi Liu
Shin-Jie Wang
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Univ Nat Central
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Publication of TW200541026A publication Critical patent/TW200541026A/en

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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector

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  • Led Device Packages (AREA)

Abstract

A light emitting diode package structure comprises a light emitting diode chip, a plurality of under bump metallurgy (UBM), a package substrate, a plurality of bonding pads, a plurality of bumps and a self-formed intermetallic compound is disclosed. The under bump metallurgy are disposed on the light emitting diode chip, and the material of the under bump metallurgy includes nickel at least. The bonding pads are disposed on the package substrate. The bumps are disposed between and electrically connect the under bump metallurgy and the bonding pads. The self-formed intermetallic compound is self-formed between the under bump metallurgy and the bumps through the reaction of the bumps and copper atom provided by the bonding pads. The self-formed intermetallic compound suits to control the spalling phenomenon of the under bump metallurgy and further maintains the photoelectric characters of the light emitting diode chip.

Description

200541026 五、發明說明(1) 發明所屬之拮彳 本發明是有關於一種發光二極體(Light Emitting Diode,LED)封裝結構及其製程,且特別是有關於一種採 用覆晶封裝(FI ip chip package)的發光二極體封裝結構 及其製程。 先前技術 由於發光二極體的發光效率不斷提升,使得發光二極 體在某些領域已漸漸取代日光燈與白熾燈泡,例如需要高 速反·應的掃描器燈源、液晶顯示器的背光源或前光源、汽 車的儀表板照明、交通號誌燈以及一般的照明裝置等。發 光二極體與傳統燈泡相較之下係具有絕對的優勢,例如體 積/、、壽命長、低電壓/電流驅動、不易破裂、不含水銀 (沒有污染問題)以及發光效率佳(省電)等特性。在各種發 光二極體元件中,尤以含丨丨族元素之化合物的發光二 極體元件,如含氮化鎵(GaN)、氮化鋁鎵(A1GaN)、氮化銦 鎵(GalnN)等的發光二極體元件最受矚目。三族氮化物為 一寬頻帶能隙之材料,其發光波長可以從紫外光一直涵蓋 至紅光,可說是幾乎涵蓋整個可見光的波段,所以在產業 上的應用非常廣泛。 圖1繪示為習知一種採用覆晶封裝之發光二極體封裝 結構的剖面示意圖。請參照圖i,發光二極體封裝結構i00 主要係由一發光二極體晶片U0、兩個球底金屬層(Under Bump Metallurgy’ UBMM20、一封裝基材 13〇、兩個連接 墊140 .及兩個凸塊150所構成。球底金屬層12〇配置於發光200541026 V. Description of the invention (1) The invention belongs to the present invention. The present invention relates to a light emitting diode (Light Emitting Diode, LED) packaging structure and its manufacturing process, and in particular to a method using a flip chip package (FI ip chip). package) light emitting diode packaging structure and its manufacturing process. In the prior art, due to the continuous improvement of the luminous efficiency of light-emitting diodes, light-emitting diodes have gradually replaced fluorescent lamps and incandescent bulbs in certain areas, such as scanner lights, LCD backlights or front light sources that require high-speed response. , Car dashboard lighting, traffic lights and general lighting. Compared with traditional light bulbs, light emitting diodes have absolute advantages, such as volume /, long life, low voltage / current drive, non-rupture, no mercury (no pollution problems), and good light emitting efficiency (power saving) And other characteristics. Among various light-emitting diode elements, especially light-emitting diode elements containing compounds of the 丨 丨 group element, such as gallium nitride (GaN), aluminum gallium nitride (A1GaN), indium gallium nitride (GalnN), etc. Of light-emitting diode elements. Group III nitride is a material with a wide band energy gap. Its emission wavelength can cover from ultraviolet light to red light. It can be said that it covers almost the entire visible light band, so it is widely used in industry. FIG. 1 is a schematic cross-sectional view showing a conventional light-emitting diode package structure using a flip-chip package. Please refer to FIG. I, the light emitting diode package structure i00 is mainly composed of a light emitting diode chip U0, two ball-bottom metal layers (Under Bump Metallurgy 'UBMM20, a packaging substrate 13, two connection pads 140, and Consists of two bumps 150. The ball-bottom metal layer 12 is arranged to emit light

13214twf.ptd 第7頁 200541026 五、發明說明(2) 二極體晶片110上,而遠拉勒 向連接墊140配置於封裝基材13 凸塊1 5 0則配置於球底今屬s】 u上 低至屬層1 2 0與連接墊1 4 〇之間。 在凸塊150之材當古& ^ 、 面,早期技術係採用錫錯n #, 而全球工業先進地區及岡宕焱7政y 士主入M 口鮮料’ 匕及困豕為了降低有毒金屬『 類、生物以及環境的表宝 ^ ^ , L 知』對人 骨口 ,不断致力降低錯在各種13214twf.ptd Page 7 200541026 V. Description of the invention (2) Diode wafer 110, and the far-latch connection pad 140 is arranged on the packaging substrate 13 The bump 1 5 0 is arranged on the bottom of the ball. This is s] u The upper part is as low as between the layer 120 and the connection pad 140. In the material of the bump 150, the early technology used tin error n #, and the advanced industrial areas of the world and the Gang Dang 焱 y y 入 masters into the M mouth fresh materials to reduce the toxicity The metal "Classic, biological and environmental watch treasures ^ ^, L know" to the human bones, and constantly strive to reduce mistakes in various

域應用的比例與使用量,因此凸塊15〇之材質亦以種二Y 鉛(lead free)銲料為趨勢。基於人類健康與全 的、 考量’日本與歐盟更訂定一明確的時間表來禁止:兄的 焊料·。根據日本MITI(Mini τ a a τ ^i^Ministry of Trade and Industry) 的規定,自2002年起,任何含鉛的電子產品禁止銷售至曰 本,而歐洲共同體系下的Eur〇pean c〇mmissi〇n則提案在 2007年以後,歐盟各國不生產任何含鉛的電子產品。很明 顯地’使用無錯焊料在電子產業已成為一必然之趨勢。 但是’在習知採用覆晶封裝之發光二極體封裝結構 中,無錯焊料的使用將會突顯出相當多的問題。在習知技 術中’球底金屬層120通常為鉻/銅/金(Cr/Cu/Au)三層薄 膜結構’或是鉻/鎳(Cr/Ni)之二層薄膜結構。當球底金屬 層120為鉻/銅/金時,凸塊150中的錫會與球底金屬層12〇 中的銅層反應形成銅-錫介金屬化合物(Cu-Sn intermetallic compound),而當球底金屬層120為鉻/錄 時,則凸塊1 5 0中的錫會與球底金屬層1 2 0中的鎳層反應形 成錫-鎳介金屬化合物(Sn-Ni intermetallic c ompound)。不論是銅-錫介金屬化合物或是錫-鎳介金屬 化合物,其與鉻層之介面上都有極高的介面能,故在對凸The proportion and amount of application in the field, so the material of the bump 150 is also a trend of two kinds of lead free solder. Based on human health and overall considerations, Japan and the EU have set a clear timetable to ban: Brother ’s solder. According to Japanese MITI (Mini τ aa τ ^ i ^ Ministry of Trade and Industry) regulations, since 2002, any lead-containing electronic products have been banned from being sold to Japan, and European c〇mmissi〇 under the European Common System. n proposals after 2007, EU countries will not produce any lead-containing electronic products. It is clear that the use of error-free solders has become an inevitable trend in the electronics industry. However, in the conventional light-emitting diode package structure using flip-chip packaging, the use of error-free solder will highlight quite a few problems. In the conventional technology, the 'ball-bottom metal layer 120 is usually a three-layer thin film structure of chromium / copper / gold (Cr / Cu / Au)' or a two-layer thin film structure of chromium / nickel (Cr / Ni). When the bottom metal layer 120 is chromium / copper / gold, the tin in the bump 150 will react with the copper layer in the bottom metal layer 120 to form a Cu-Sn intermetallic compound, and when When the ball-bottom metal layer 120 is chromium, the tin in the bump 150 will react with the nickel layer in the ball-bottom metal layer 120 to form a Sn-Ni intermetallic compound. Whether it is a copper-tin-based metal compound or a tin-nickel-based metal compound, the interface between it and the chromium layer has a very high interface energy.

13214twf.ptd 第8頁 200541026 五、發明說明(3) 塊1 5 0進行迴焊的過程中,4 人人M T銅—錫介金屬化合物或是錫-鎳 二至屬化合物會逐漸球化而離開鉻層表面並懸浮於凸塊 之中,此現象即為所謂的剝離現象(spa丨丨丨13214twf.ptd Page 8 200541026 V. Description of the invention (3) During the reflow process of block 150, 4 people MT copper-tin intermetallic compound or tin-nickel bimetallic compound will gradually spheroidize and leave The surface of the chromium layer is suspended in the bumps. This phenomenon is called the peeling phenomenon (spa 丨 丨 丨

Phen〇menon),而上述之剝離現象將會嚴重地影響到發光 一極體封裝結構中焊料接合的強度。 發明内客 又 ,發明的目的就是在提供_種發光二極體封裝結構, 適於抑制球底金屬層中的剝離現象。 •本發明的再一目的是提供—種發光二極體封裝製程, 以維護兀件接觸金屬的高反射率及良好的歐姆式接觸。 本發明提出-種發光二極體封裝結構,其係由一發光 :極體晶片、多個球底金屬層、—封裝基材、多個連接 、多個凸塊及一自生成介金屬化合物(self_f〇rmed intermetallic compound)所構成。 屬μ球ίί屬?ΐ置於發光二極體晶片上,且構成球底金 ::之材料至少包括錄。連接塾配置於封裝基材上。凸塊 酉己置於球底金屬層與連接墊間,以使球底金屬層與連接塾 ίΐ。1生成介金屬化合物係於球底金屬層與凸塊之 間精由連接墊所提供之銅原子而自行生成。 在:實施例中,發光二極體封裝結構例如更包括多個 ::’其为別配置於連接墊上。鎳層具有至少一開口,以 2接墊接觸凸塊。發光二極體晶片例如係由一基材及一 =導體層所構成。半導體層係以例如遙晶(epitaxy)的方 ^而形成於基材上。半導體層例如係由一第一型摻雜半導Phenomenon), and the above-mentioned peeling phenomenon will seriously affect the strength of the solder joint in the light emitting monolithic package structure. The inventor of the invention The purpose of the invention is to provide a kind of light emitting diode packaging structure, which is suitable for suppressing the peeling phenomenon in the metal layer under the ball. • Another object of the present invention is to provide a light-emitting diode packaging process to maintain the high reflectivity of the metal parts in contact with the metal and good ohmic contact. The invention proposes a light-emitting diode packaging structure, which is composed of a light-emitting diode chip, multiple ball-bottom metal layers, a packaging substrate, multiple connections, multiple bumps, and a self-generating intermetallic compound ( self_fommed intermetallic compound). Is a μ ball? The plutonium is placed on the light-emitting diode wafer, and the material constituting the gold base :: includes at least the recording. The connection pad is disposed on the packaging substrate. The bump 酉 has been placed between the bottom metal layer and the connection pad, so that the bottom metal layer and the connection 塾 ΐ. 1 The generation of the intermetallic compound is generated between the ball-bottom metal layer and the bumps by the copper atoms provided by the connection pads. In the embodiment, the light emitting diode packaging structure further includes, for example, a plurality of :: 's, which are separately arranged on the connection pads. The nickel layer has at least one opening and contacts the bump with 2 pads. The light emitting diode wafer is composed of, for example, a substrate and a conductive layer. The semiconductor layer is formed on the substrate in, for example, an epitaxy. Semiconductor layer

132l4twf.ptd 200541026 五、發明說明(4) 體層、-發光層以及一第二型摻雜半導體層所構成。第一 聖摻雜半v體層係位於基材上,而發光層係位於第一型摻 雜半導體層的部分區域上,且第二型摻雜半導體層係位於 發光層上。此外,未分佈有發光層之第一型摻雜半導體層 土 =及第了型摻雜半導體層上,例如分別配置有多個接觸 至層。Θ述之球底金屬層分別配置於各接觸金屬層上。 本發明再提出一種發光二極體封裝製程,其係先提供 光二極體晶片。接著形成多個球底金屬層於發光二極 體曰曰·片上。構成球底金屬層之材料至少包括鎳。之後提供 封裝基材,並形成多個連接墊於封裝基材上。接著步 銲料塊於球底金屬層與連接墊間,以使球底金屬層盥 f接墊電性連接。最後迴銲銲料塊以形成多個凸塊,同時 ^然生成一自生成介金屬化合物於球底金屬層與凸塊之 在本實施例中’於形成連接塾與形成焊料塊兩個步驟 f間,例如更分別形成一鎳層於連接墊上,且鎳層具 少一開口。 在上述兩實施例中,連接塾之材質例如係銅或銅人 t,銅合金例如有銅鉻合金、銅鎳合金或銅鎢合金等: 塊之材質例如係無鉛銲料或含錫銲料(Sn —rich)。 綜上所述,在本發明之發光二極體封裝結構及其製程 ,連接墊所提供之銅原子會與凸塊中的錫反應,而在迴 二過程十形成自生成介金屬化合物。藉由自生成介金属化 5物即可阻絕凸塊與球底金屬層之接觸,進而 現 132l4twf.Ptd 第10頁 200541026 五、發明說明(5) 象的發生。 為讓本發明之上述和其他目的、牲%』 易懂,下文特舉較佳實施例,並配合所附^ 4此更明顯 明如下。 回式’作詳細說 實施方式 圖2緣示為本發明一較佳實施例之發光二極 程的流程圖,圖3Α〜3F繪示為本發明—較佳奋 封衣W 二極體封裝製程的剖面流程_,圖4繪示為本〜二例之一發光 佳實.施例之發光二極體封裝結構的剖面示意圖' 另一較 請參照圖2,本實施例之發光二極體封裝製程主 =提供發光二極體晶片S1、形成球底金屬層以、提供。封 扁基材S3、形成連接墊S4、形成銲料塊S6以及迴銲銲料 同時自然生成自生成介金屬化合物S7等步驟。 ‘ 此外,在本實施例之形成連接墊S4與形成焊料塊%兩 個步驟之間,例如更包括形成鎳層於連接墊上S5。 請參照圖3 A,本實施例之發光二極體封裝製程係先提 供一發光二極體晶片2 1 0。發光二極體晶片21 〇例如係由基 材220及半導體層230所構成。其中,基材220的材質可以 j用藍寶石(sapphire)、碳化矽(Sic)或氮化鎵(GaN)等材 貝’但並不侷限於上述材質。 半導體層23 0例如係由摻雜半導體層232、發光層234 以及換雜半導體層236所構成,其形成方式例如係磊晶。 其中’摻雜半導體層232位於基材220上,發光層234例如 位於摻雜半導體層2 3 2的部分區域上,摻雜半導體層2 3 6則132l4twf.ptd 200541026 V. Description of the invention (4) A bulk layer, a light-emitting layer, and a second type doped semiconductor layer. The first holy doped semi-v-layer layer is located on the substrate, the light emitting layer is located on a partial region of the first type doped semiconductor layer, and the second type doped semiconductor layer is located on the light emitting layer. In addition, the first type doped semiconductor layer and the first type doped semiconductor layer where no light emitting layer is distributed, for example, a plurality of contact layers are respectively arranged. The spherical bottom metal layers described by Θ are disposed on the respective contact metal layers. The present invention further provides a light emitting diode packaging process, which first provides a light emitting diode wafer. Next, a plurality of ball-bottom metal layers are formed on the light-emitting diode. The material constituting the bottom metal layer includes at least nickel. Then, a packaging substrate is provided, and a plurality of connection pads are formed on the packaging substrate. The next step is a solder block between the ball-bottom metal layer and the connection pads, so that the ball-bottom metal layer and the pads are electrically connected. Finally, the solder bump is re-soldered to form a plurality of bumps, and at the same time, a self-generating intermetallic compound is generated between the ball-bottom metal layer and the bump. For example, a nickel layer is formed on the connection pad, and the nickel layer has one opening. In the above two embodiments, the material of the connecting ytterbium is, for example, copper or copper, and the copper alloy is, for example, copper-chromium alloy, copper-nickel alloy, or copper-tungsten alloy. rich). In summary, in the light-emitting diode packaging structure and the manufacturing process of the present invention, the copper atoms provided by the connection pad will react with the tin in the bump, and form a self-generating intermetallic compound in the second process. By the self-generating metallization, the contact between the bump and the metal layer at the bottom of the ball can be blocked, and then 132l4twf.Ptd page 10 200541026 V. Description of the invention (5) The occurrence of the phenomenon. In order to make the above and other objects and advantages of the present invention easy to understand, the preferred embodiments are exemplified below, and the following will be more clearly explained in conjunction with the attached ^ 4. Figure 2 shows the flow chart of the light-emitting diode of a preferred embodiment of the present invention in detail, and Figures 3A to 3F show the present invention—the preferred Fenfeng W diode packaging process. Sectional flow chart_, FIG. 4 shows one of the two examples of light-emitting diodes. The schematic cross-sectional view of the light-emitting diode package structure of the embodiment is another example. Please refer to FIG. 2 for the light-emitting diode package of this embodiment. The main process is to provide the light-emitting diode wafer S1, to form a ball-bottom metal layer, to provide. The steps of flattening the substrate S3, forming the connection pad S4, forming the solder bump S6, and reflowing the solder at the same time naturally generate the self-generating intermetallic compound S7. ‘In addition, between the two steps of forming the connection pad S4 and forming the solder bump% in this embodiment, for example, it further includes forming a nickel layer on the connection pad S5. Referring to FIG. 3A, the light emitting diode packaging process of this embodiment first provides a light emitting diode chip 2 1 0. The light-emitting diode wafer 21 0 is composed of, for example, a base material 220 and a semiconductor layer 230. The material of the substrate 220 may be sapphire, silicon carbide (GaN), or gallium nitride (GaN), but is not limited to the above materials. The semiconductor layer 230 is composed of, for example, a doped semiconductor layer 232, a light-emitting layer 234, and a hybrid semiconductor layer 236, and the formation method thereof is, for example, epitaxy. Wherein, the doped semiconductor layer 232 is located on the substrate 220, the light emitting layer 234 is located on a partial region of the doped semiconductor layer 2 3 2, and the doped semiconductor layer 2 3 6 is

^32l4twf.ptd 第11頁 200541026^ 32l4twf.ptd Page 11 200541026

位於發光層234上。摻雜半導體層2 32與摻雜半導體層236 係為不同型之摻雜半導體層。舉例來說,若摻雜半導體; 232為p型摻雜半導體層,則摻雜半導體層23 6即為n型摻ς 半導體層。反之,若摻雜半導體層232 gN型摻雜半導體, 層,則摻/雜半導體層236即為p型摻雜半導體層。發光層 234例如採用夕重畺子井(muih weH,mqw)結 在本實施例中,發光二極體晶片2丨〇例如更包括多個 接觸金屬層2 4 2, 2 4 4 (在此以兩個為例)。接觸金屬層2 4 2Located on the light-emitting layer 234. The doped semiconductor layer 232 and the doped semiconductor layer 236 are different types of doped semiconductor layers. For example, if a semiconductor is doped; 232 is a p-type doped semiconductor layer, the doped semiconductor layer 236 is an n-type doped semiconductor layer. Conversely, if the doped semiconductor layer 232 g is an N-type doped semiconductor layer, the doped / doped semiconductor layer 236 is a p-type doped semiconductor layer. The light-emitting layer 234 is, for example, a muih weH (mqw) junction. In this embodiment, the light-emitting diode wafer 2 includes, for example, a plurality of contact metal layers 2 4 2, 2 4 4 (herein Two as examples). Contact metal layer 2 4 2

位於未配置有發光層234之摻雜半導體層232上,而接觸金 屬層244位於摻雜半導體層236上。兩個接觸金屬層242, 244係μ用以加強歐姆接觸並做為電極,並以具有高反射率 ’材貝為佳。若接觸金屬層242所接觸之摻雜半導體層 為摻雜半導體層,則接觸金屬層242係以鈦/銘或鈦/銀 ^又層結構為佳。若接觸金屬層24 2所接觸之摻雜半導體 二為Ρ型摻雜半導體層,則接觸金屬層242係以鎳/鋁、 /或鎳/銀之雙層結構為佳。接觸金屬層244亦因接觸 =同型之摻雜半導體層可採用與接觸金屬層242對應之結On the doped semiconductor layer 232 where the light emitting layer 234 is not arranged, and the contact metal layer 244 is on the doped semiconductor layer 236. The two contact metal layers 242, 244 are used to strengthen the ohmic contact and serve as electrodes, and preferably have a high reflectivity material. If the doped semiconductor layer contacted by the contact metal layer 242 is a doped semiconductor layer, the contact metal layer 242 preferably has a titanium / metal or titanium / silver layer structure. If the doped semiconductor layer 2 contacted by the contact metal layer 24 2 is a P-type doped semiconductor layer, the contact metal layer 242 preferably has a double structure of nickel / aluminum or nickel / silver. The contact metal layer 244 can also adopt a junction corresponding to the contact metal layer 242 due to the contact = doped semiconductor layer of the same type.

Μ9田然,發光二極體晶片21 〇並不限定需使用接觸金屬 244,接觸金屬層242,244之主要作用係加強半導 ,層230與後續材料層的歐姆接觸。⑨了上述方式,例如 _ 接雜半導體層表面摻雜1^型元素,或在Ν型摻雜半導 豆曰、面摻雜Ρ型元素,也可達到加強半導體層23〇與後續M9 Tianran, the light-emitting diode wafer 21 is not limited to the use of contact metal 244. The main role of the contact metal layers 242, 244 is to strengthen the semiconductor, and the layer 230 is in ohmic contact with subsequent material layers. With the above methods, for example, the surface of the doped semiconductor layer is doped with a 1 ^ -type element, or the N-type doped semiconductor is doped, and the surface is doped with a P-type element. The semiconductor layer 23 and subsequent steps can also be strengthened.

132l4twf.ptd 第12頁 200541026 五、發明說明(7) 材料層之歐姆接觸的目的。 此外,發光二極體晶片2 1 0例如更包括一鈍化保護層 250,覆蓋半導體層230但暴露部分接觸金屬層242,244。 鈍化保護層2 5 0之材質例如係二氧化石夕、氮化紹或氮化 石夕。 接著請參照圖3B,形成兩個球底金屬層2 6 0,270於發 光二極體晶片2 1 0上。兩個球底金屬層2 6 0, 2 7 0分別配置 於兩個接觸金屬層242,244上,構成球底金屬層260,270 之材·料至少包括鎳。兩個球底金屬層26〇,270例如分別由 黏著層262,272、阻障層264,274與可焊金屬層 (solderable metal layer) 266,276 所構成。其中,黏著 層2 62,2 72之材質例如係鉻、鈦、鈦鎢合金或氮化鈕等, 阻障層264,274之材質例如係鎳、鉑、鈀(pd)或銅等。 接著請參照圖3C,提供一封裝基材28〇,其係 導與率路層284所構成。基板282之材質係以具有高 U路層m配置於基板282上,其材質係 之材貝,如銀或鋁等金屬為佳。 ,、 于羊 a伽,著清參照圖3D,於封裝基材280之線路声284卜π 士 兩個連接墊286,288,作兩去日84上形成 銅鎳合金或銅鎢合金等。連接墊以"2 °有銅鉻合金、 :子給後續形成在其上面之焊料,以使銲::用係提供銅 與鋼原子產生反應,並生成如圖3F之一自=過程 ㈢生成介金屬132l4twf.ptd Page 12 200541026 V. Description of the invention (7) Purpose of ohmic contact of material layer. In addition, the light emitting diode wafer 2 10 further includes, for example, a passivation protection layer 250 covering the semiconductor layer 230 but exposed portions contacting the metal layers 242, 244. The material of the passivation protective layer 2 50 is, for example, SiO2, Nitride or Nitride. Next, referring to FIG. 3B, two ball-bottom metal layers 2660,270 are formed on the light-emitting diode wafer 210. The two ball-bottom metal layers 2 60 and 2 70 are respectively disposed on the two contact metal layers 242 and 244, and the materials and materials constituting the ball-bottom metal layers 260 and 270 include at least nickel. The two ball-bottom metal layers 260, 270 are composed of, for example, adhesive layers 262, 272, barrier layers 264, 274, and solderable metal layers 266, 276, respectively. Among them, the materials of the adhesive layers 2 62, 2 72 are, for example, chromium, titanium, titanium tungsten alloy, or nitride buttons, and the materials of the barrier layers 264, 274 are, for example, nickel, platinum, palladium (pd), or copper. Referring next to FIG. 3C, a packaging substrate 28o is provided, which is composed of a conductive and rate path layer 284. The material of the substrate 282 is arranged on the substrate 282 with a high U-road layer m. The material of the substrate is preferably a metal such as silver or aluminum. With reference to FIG. 3D, Yu Yang a Jia, referring to FIG. 3D, two connection pads 286, 288 on the line 280 of the packaging substrate 280 are used to form a copper-nickel alloy or a copper-tungsten alloy on the two sides 84. The connection pad has copper-chromium alloy at 2 °, and the following solder is formed on the solder to make the soldering :: use the system to provide copper and steel atoms to react, and generate as shown in Figure 3F Intermetal

第13頁 200541026 五、發明說明(8) ----- 化ά物3 2 0自生成介金屬化合物3 2 0將於稍後說明。 接著請參照圖3Ε,形成兩個銲料塊312a,31“於球底 金屬層26 0,2 70或連接墊286,288上,並藉由銲料塊一 312a, 314a而電性連接二極體晶片21〇之球底金屬層26〇, 270與封裝基材280之連接墊286,288。銲料塊312a,31乜 之材質例如係無鉛銲料或含錫銲料。 接著請參照圖3F,對圖3£之銲料塊312a,314a進行迴 鋅以形成兩個凸塊3 1 2,3 1 4。在進行迴銲的同時,焊料與 連接·墊286,288所提供之銅原子就會反應生成一自生成^ 金屬化合物320,並漸漸地沈積於靠近球底金屬層26〇, 2 70之側。自生成介金屬化合物32〇例如是一種三元相銅一 鎳-錫。 由於自生成介金屬化合物3 2 〇具有阻絕反應的效果, 因此能阻擋球底金屬層260,270内之鎳與焊料接觸,進而 有效避免球底金屬層2 6 0,2 70的消耗而造成剝離現象。 請參照圖4,在圖3D與圖3E的兩個·步驟之間,更可形 成一鎳層290於連接墊286,288上,鎳層290具有至少一開 口 01 ’以暴露出連接墊286, 288。如此,即會產生如圖4Page 13 200541026 V. Description of the invention (8) ----- Chemical compound 3 2 0 Self-generating intermetallic compound 3 2 0 will be explained later. Next, referring to FIG. 3E, two solder bumps 312a, 31 "are formed on the ball-bottom metal layer 26 0, 2 70 or the connection pads 286, 288, and the diode chip is electrically connected through the solder bumps 312a, 314a. 21 ° ball bottom metal layers 26〇, 270 and the connection pads 286, 288 of the packaging substrate 280. The material of the solder blocks 312a, 31 乜 is, for example, lead-free solder or tin-containing solder. Next, please refer to FIG. 3F and FIG. The solder bumps 312a, 314a are back-zinced to form two bumps 3 1 2, 3 1 4. During the re-soldering, the copper atoms provided by the solder and the connection pads 286, 288 will react to form a self-generated ^ The metal compound 320 is gradually deposited on the side near the ball-bottom metal layer 260, 2 70. The self-generating intermetallic compound 32o is, for example, a ternary phase copper-nickel-tin. Since the self-generating intermetallic compound 3 2 〇It has the effect of blocking the reaction, so it can block the nickel in the ball-bottom metal layers 260 and 270 from contact with the solder, thereby effectively avoiding the depletion of the ball-bottom metal layers 2 60, 2 70. Please refer to FIG. Between the two steps of FIG. 3D and FIG. 3E, a nickel layer 290 can be further formed. On the connection pads 286, 288, the nickel layer 290 has at least one opening 01 'to expose the connection pads 286, 288. In this way, the result is as shown in Fig. 4

所示之發光二極體封裝結構3〇 〇a。鎳層29〇之厚度並未做 任何限制。鎳層2 90的作用在於避免連接墊286,288產生 氧化,同時也可以控制連接墊286, 288與凸塊312,314的 接觸面積。 最後請參照圖3 F與圖4,本發明之兩種發光二極體封 裝結構3 0 0, 3 0 0 a,主要皆由發光二極體晶片2丨〇、兩個球The light emitting diode package structure 300a is shown. The thickness of the nickel layer 29 is not limited in any way. The role of the nickel layer 2 90 is to prevent oxidation of the connection pads 286, 288, and also to control the contact area of the connection pads 286, 288 and the bumps 312, 314. Finally, please refer to FIG. 3F and FIG. 4. The two light-emitting diode packaging structures 3 0 0 and 3 0 0 a of the present invention are mainly composed of the light-emitting diode wafer 2 丨 0 and two balls.

200541026 五、發明說明(9) 底金屬層260, 270、一封梦| 288、兩個凸塊31 2, 3〗4及—^ & 士二兩個連接墊286, 成。其令,發光二極體封裝金屬化合物32〇所構 構30°更多了鎳尸〇,其餘二分則:同义發先二極體封裝結 形成= ’本發明之主要精神係 -自生成介金屬化合物m科塊’ i自然生成 象的.目的。 以達到抑制球底金屬層之剝離現 、纟示上所述,在本私 中,連接墊所提供tL:! 體封裝結構及其製程 反應,並形成自^成在進行迴銲時與凸塊中的錫 合物可阻絕凸塊鱼屬化合物。由於自生成介金屬化 之鎳就不會與凸:内:錫^之接觸’因此球底金屬層内 會因此被消耗掠, 、接反應,以確保球底金屬層不 雖然本笋明P而有效抑制球底金屬層的剝離現象。 限定本發明]紅/較佳實施例揭露如上,然其並非用以 和範圍内,當可】二、,此技藝者,在不脫離本發明之精神 範圍當視後i二φ i =之f動與潤飾,因此本發明之保護 甲明專利範圍所界定者為準。 13214twf.ptd 第15頁 200541026 圖式簡單說明 圖1繪示為習知一種採用覆晶封裝之發光二極體封裝 結構的剖面示意圖。 圖2繪示為本發明一較佳實施例之發光二極體封裝製 程的流程圖。 圖3A〜3F繪示為本發明一較佳實施例之發光二極體封 裝製程的剖面流程圖。 圖4繪示為本發明另一較佳實施例之發光二極體封裝 結構的剖面示意圖。 【圖·式標示說明】 I 0 0 :發光二極體封裝結構 II 0 :發光二極體晶片 1 2 0 :球底金屬層 1 3 0 :封裝基材 1 4 0 :連接墊 1 5 0 :凸塊 2 1 0 :發光二極體晶片 220 :基材 23 0 :半導體層 2 3 2、2 3 6 :摻雜半導體層 2 3 4 :發光層 242、244 :接觸金屬層 2 5 0 :純化保護層 2 6 0、2 7 0 ··球底金属層 2 62、272 :黏著層200541026 V. Description of the invention (9) The bottom metal layer 260, 270, a dream | 288, two bumps 31 2, 3, 4 and — ^ & As a result, the light-emitting diode encapsulated metal compound 32 ° is structured at 30 ° with more nickel corpuscles 0, and the remaining dichotomy is: synonymous first-diode package junction formation = 'the main spirit of the present invention-self-generated intermetal The compound m family blocks' i. Naturally generated image. Purpose. In order to suppress the peeling of the metal layer at the bottom of the ball, as shown above, in this case, the tL :! body packaging structure provided by the connection pad and its process reaction, and form a self-forming and bumps during reflow The tin compound can block the genus Bump. Since the self-generated metallized nickel will not be in contact with the convex: inside: tin ^, the ball bottom metal layer will be consumed and reacted to ensure that the ball bottom metal layer is not Effectively suppress the peeling of the ball bottom metal layer. Limiting the invention] The red / preferred embodiment is disclosed as above, but it is not intended to be used within the scope, when it can be used] Second, the artist will not deviate from the spirit of the present invention when i φ i = f Movement and retouching, therefore, the protection scope of Jiaming patent of the present invention shall prevail. 13214twf.ptd Page 15 200541026 Brief Description of Drawings Figure 1 shows a schematic cross-sectional view of a conventional light-emitting diode package structure using a flip-chip package. FIG. 2 is a flowchart of a light emitting diode packaging process according to a preferred embodiment of the present invention. 3A to 3F are cross-sectional flowcharts of a light emitting diode packaging process according to a preferred embodiment of the present invention. FIG. 4 is a schematic cross-sectional view of a light emitting diode package structure according to another preferred embodiment of the present invention. [Illustration of diagrams and expressions] I 0 0: Light-emitting diode package structure II 0: Light-emitting diode wafer 1 2 0: Ball-bottom metal layer 1 3 0: Packaging substrate 1 4 0: Connection pad 1 5 0: Bump 2 1 0: Light-emitting diode wafer 220: Substrate 23 0: Semiconductor layer 2 3 2, 2 3 6: Doped semiconductor layer 2 3 4: Light-emitting layer 242, 244: Contact metal layer 2 5 0: Purified Protective layer 2 6 0, 2 7 0 · Ball bottom metal layer 2 62, 272: Adhesive layer

13214twf.ptd 第16頁 200541026 圖式簡單說明 264、274 :阻障層 2 6 6、276 :可焊金屬層 2 8 0 :封裝基材 2 8 2 :基板 2 8 4 :線路層 286、288 :連接墊 2 9 0 :鎳層 30 0、30 0a :發光二極體封裝結構 •3 1 2、3 1 4 :凸塊 320 :自生成介金屬化合物 01 ··開口13214twf.ptd Page 16 200541026 Brief description of the drawings 264, 274: Barrier layer 2 6 6, 276: Solderable metal layer 2 8 0: Packaging substrate 2 8 2: Substrate 2 8 4: Circuit layer 286, 288: Connection pad 2 9 0: Nickel layer 30 0, 30 0a: Light emitting diode package structure • 3 1 2, 3 1 4: Bump 320: Self-generating intermetallic compound 01 ·· Opening

13214twf.ptd 第17頁13214twf.ptd Page 17

Claims (1)

200541026 六、申請專利範圍 1 · 一種發光二極體封裝結構’包括: 一發光二極體晶片; 多數個球底金屬層,配置於違發光二極體晶片上,構 成該些球底金屬層之材料至少包括錄’ 一封裝基材; 多數個連接墊,配置於該封裝基材上; 多數個凸塊,配置於該呰球底金屬層與該些連接墊 間,以使該些球底金屬層與該呰連接墊電性連接;以及 .一自生成介金屬化合物,該自生成介金屬化合物係於 該些球底金屬層與該些凸塊之間自行生成。 2 ·如申請專利範圍第1項所述之發光二極體封裝結 構’其中該些連接墊之材質包栝銅。 3 ·如申請專利範圍第1項所述之發光二極體封裝結 構’其中該些連接塾之材質包栝銅合金。 4 ·如申晴專利範圍第3項所述之發光一極體封裝結 構其中該些連接墊之材質包栝銅鉻合金、銅鎳合金盘銅 鎢合金其中之一。 、 〃 •士申清專利範圍第1項所述之發光一極體封装結 ^ ’更包括多數個鎳層,其分別配置於該些連接墊上,且 °亥些錄層具有至少一開口,以使該些連接墊接觸該此凸 塊。 一 6·如申請專利範圍第1項所述之發光二極體封裝結 其中硪些凸塊之材質包括無鉛銲料與含錫銲料其中之200541026 VI. Scope of patent application 1 · A light emitting diode package structure 'includes: a light emitting diode wafer; a plurality of ball-bottom metal layers arranged on the light-emitting diode wafer to form the ball-bottom metal layers. The material includes at least a packaging substrate; a plurality of connection pads disposed on the packaging substrate; a plurality of bumps disposed between the ball bottom metal layer and the connection pads so that the ball bottom metals A layer is electrically connected to the rhenium connection pad; and a self-generating intermetallic compound is generated between the ball-bottom metal layers and the bumps. 2 · The light emitting diode packaging structure described in item 1 of the scope of the patent application, wherein the material of the connection pads is copper. 3. The light-emitting diode packaging structure described in item 1 of the scope of the patent application, wherein the materials of the connection 栝 are copper alloy. 4 · The light-emitting diode package structure described in item 3 of Shenqing's patent scope, where the material of the connection pads is one of copper-chromium alloy, copper-nickel alloy disk, copper-tungsten alloy. 〃 • The light-emitting diode package junction described in item 1 of Shi Shenqing's patent scope includes a plurality of nickel layers, which are respectively disposed on the connection pads, and the recording layers have at least one opening to The connection pads are brought into contact with the bump. 1 · The light-emitting diode packaging junction as described in item 1 of the scope of the patent application, wherein the materials of the bumps include lead-free solder and tin-containing solder. 第18頁 200541026 六、申請專利範圍 谨利範圍第1項所述之發光二極體封 構,其中该發光二極體晶片包括: τ凌… 一基材;以及 一半導體層,配置於續其从L 、、 一型#雜丰導俨® 议1 土才上,該半導體層包括一第 孓杉雜丰V體層、一發光層以及一 弟 層,其中該第-型摻雜半導體層係位於;基‘:+卜體 光層係位於該第一型摻雜半導體層的部分^ 而,發 二型摻雜半導體層係位於該發光層上。 且邊第 爐Λ ΪΓ”利範圍第7項所述曰之發光二極體封裝結 之兮笛"^夕數個接觸金屬[配置於未分佈有該發光芦 之该ί —型掺雜半導體層上以及該第二歸雜半導=層 上,/、中該些球底金屬層分別配置於該些接觸金屬屏丄。 9· 一種發光二極體封裝製程,包括: 提供一發光二極體晶片; $成夕數個球底金屬層於該發光二極體晶, 該些球底金屬層之材料至少包括鎳;▲ 構成 提供一封裝基材; 形成多數個連接墊於該封裝基材上; 形成多數個銲料塊於該些球底金屬層與該些連接墊 間,以使該些球底金屬層與該些連接墊電性連接;以及 迴輝該些銲料塊以形成多數個凸塊,同時自然生成一 自生成介金屬化合物於該些球底金屬層與該些凸塊之間。 10·如申請專利範圍第9項所述之發光二極體封裝製 程’其中該些連接墊之材質包括銅。 I32l4twf.ptd 第19頁 200541026Page 18, 200541026 VI. Patent application scope The light-emitting diode encapsulation described in item 1 above, wherein the light-emitting diode wafer includes: τ… a substrate; and a semiconductor layer, which is arranged on the substrate. From L 、, 一 型 # 杂 丰 导 俨 ® 11, the semiconductor layer includes a first cedar heterofeng V body layer, a light emitting layer, and a younger layer, wherein the first-type doped semiconductor layer is located at ; ': + Bu the bulk light layer is located on the part of the first type doped semiconductor layer ^, and the second type doped semiconductor layer is located on the light emitting layer. And the side of the furnace Λ Ϊ Γ "" described in the seventh range of the light-emitting diode package junction quot ^ Xi several contact metals [arranged in the luminescent do not distribute the ί-type doped semiconductor On the layer and on the second impurity semiconductor layer =, the ball-bottom metal layers are respectively disposed on the contact metal screens. 9. A light-emitting diode packaging process including: providing a light-emitting diode A plurality of ball-bottom metal layers on the light-emitting diode crystal, and the materials of the ball-bottom metal layers include at least nickel; ▲ forming a package substrate; forming a plurality of connection pads on the package substrate Forming a plurality of solder bumps between the ball-bottom metal layers and the connection pads so that the ball-bottom metal layers are electrically connected to the connection pads; and returning the solder bumps to form a plurality of bumps At the same time, a self-generating intermetallic compound is naturally generated between the ball-bottom metal layers and the bumps. 10. The light-emitting diode packaging process described in item 9 of the scope of patent application, wherein the connection pads The material includes copper. I32l4twf.ptd Page 19 200541026 11 ·如申請專利範圍第9項所述之發光二極體封裝製 程,其中該些連接墊之材質包栝銅合金。 。1 2 ·如申請專利範圍第1丨項所述之發光二極體封裝製 私,其中该些連接墊之材質包栝銅鉻合金、銅鎳合金與鋼 鎢合金其中之一。 1 3 ·如申请專利範圍第9項所述之發光二極體封裝製 ^ 〃中在形成该些連接墊與形成該些焊料塊之間,更包 括分別形成一鎳層於該些連接墊上,且該些鎳層具有至少 一開.口。 1 4 ·如申請專利範圍第9項所述之發光二極體封裝製 耘’其中該些銲料塊之材質包括無鉛銲料與含錫銲料其中 之一 〇11 · The light emitting diode packaging process as described in item 9 of the scope of patent application, wherein the material of the connection pads is copper alloy. . 1 2 · The light-emitting diode package as described in item 1 of the patent application scope, wherein the material of the connection pads includes one of copper-chromium alloy, copper-nickel alloy, and steel-tungsten alloy. 1 3 · According to the light-emitting diode packaging system described in item 9 of the scope of patent application, between forming the connection pads and forming the solder bumps, it further includes forming a nickel layer on the connection pads, respectively. And the nickel layers have at least one opening. 1 4 · The light-emitting diode packaging system described in item 9 of the scope of the patent application, wherein the material of the solder bumps includes one of lead-free solder and tin-containing solder. 〇 第20頁Page 20
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI420695B (en) * 2008-10-21 2013-12-21 Advanced Optoelectronic Tech Compound semiconductor device package module structure and fabricating method thereof
TWI721340B (en) * 2018-12-04 2021-03-11 榮創能源科技股份有限公司 Led and a method for manufacturing the same

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI420695B (en) * 2008-10-21 2013-12-21 Advanced Optoelectronic Tech Compound semiconductor device package module structure and fabricating method thereof
TWI721340B (en) * 2018-12-04 2021-03-11 榮創能源科技股份有限公司 Led and a method for manufacturing the same

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