TW200540957A - An integrated electronic sensor - Google Patents

Abstract

A single chip wireless sensor (1) comprises a microcontroller (2) connected by a transmit/receive interface (3) to a wireless antenna (4). The microcontroller (2) is also connected to an 8kB RAM (5), a USB interface (6), an RS232 interface (8), 64kB flash memory (9), and a 32kHz crystal (10). The device (1) senses humidity and temperature, and a humidity sensor (11) is connected by an 18 bit A-to-D converter (12) to the microcontroller (2) and a temperature sensor (13) is connected by a 12 bit SAR A-to-D converter (14) to the microcontroller (2). The device (1) is an integrated chip manufactured in a single process in which both the electronics and sensor components are manufactured using standard CMOS processing techniques, applied to achieve both electronic and sensing components in an integrated process.

Description

200540957 IX. Description of the invention: [Technical field to which the invention belongs] The present invention relates to electronic sensors. [Previous Technology] One of the major driving forces in the electronics industry requires greater functional integration to make production more automated and reduce unit cost. Of course, an additional advantage is that the size is reduced and thus the circuit density is higher. More importantly, for battery applications, higher integration generally results in lower power due to reduced parasitic capacitance. However, in the field of sensors, and more specifically in the field of wireless sensors, greater integration has slowed down as microcontrollers, eight-to-zero converters (ADCs), memory, RF (RF) Transceiver and sensor components are integrated in an integrated sensor device. Seventy-two aa m must be _____.

Traditionally manufactured on ceramic or glass substrates and cannot be easily integrated into silicon

Usability in some types of sensor applications

Components and sensing components. However, the electricity-water vapor sensing dielectric is 100710.doc 200540957. This process is not suitable for a large number of semiconductor processes. The present invention addresses these issues. [Summary of the Invention] According to the present invention, an integrated sensor device is provided, which comprises:-a MOS circuit in a semiconductor substrate,-an interconnection level having an interconnecting conductor and an insulating dielectric, the levels being at The substrate and interconnect the MOS circuits, the interconnect levels are incorporated into a sensor with electrodes embedded in the interconnect dielectric, and the MOS circuits include One of the signals of the detector electrode processor. In a specific embodiment, the sensor includes a porous oxide to allow the sensed gas or moisture to enter. In another specific embodiment, the porous oxide is doped with carbon SiO 2. In another specific embodiment, the sensor is a capacitive sensor. In a specific embodiment, the sensor includes a passivation layer on the sensor electrodes. In another embodiment, the porous oxide is deposited on the purification layer, and the MOS circuit detects a change in a fringe field between the electrodes. In another specific embodiment, the intermediate layer includes a last name + stop layer 'and the purification layer has the same composition as the etch stop layer. In a specific embodiment, the purification layer is a Si3N4 component. In another specific embodiment, the passivation layer is recessed on the sensing electrodes 100710.doc 200540957. In another specific embodiment, a porous oxide film is formed in the depression. In another embodiment, the porous oxide is interposed between the electrodes and is exposed. In another embodiment, the MOS circuits are directly below the sensor at a vertical height. In another specific embodiment, the MOS circuits include a temperature sensor.

In a specific embodiment, the temperature sensor includes a pNp transistor. In another embodiment, the MOS circuit includes a microcontroller to process a gas or humidity signal from the gas or humidity sensor and a temperature signal from the temperature sensor to provide an enhanced output. In another embodiment, the enhanced output is a gas or humidity reading whose temperature is corrected. In a specific embodiment, the sensor comprises polyimide deposited on the electrodes. In the μn body embodiment, the deletion circuits include a -A to D converter connected between the sensor electrodes and the processor. In another specific embodiment, the A to D converter includes a dummy capacitor array with a -constant layout around active A to D converter capacitors. In one specific embodiment, a light emitting diode is further included. In another specific embodiment, the bipolar system is formed in a deep trench to the lateral lower interconnect level of the sensor electrodes. In another specific embodiment, the device includes a photodiode diode. 100710.doc 200540957 In the specific embodiment, the Xi-generation touch ★ »» i J ^ the polar body is in a deep trench in the lower interconnection level of one of the sensor electrodes. In another specific embodiment, the deletion circuits include a wireless device. 'In another specific implementation, the wireless transceiver it is preferred to communicate with other nodes in the network' and it includes a component for switching channel frequencies according to a low-frequency channel switching scheme immediately after detecting interference. In the 纟 -item embodiment, an interconnect level includes a low noise amplifier. Like in another embodiment, the low noise amplifier includes a strained region under a conductor. In another embodiment, the strained silicon is in one of the fifth or sixth interconnect levels on the substrate. 9 In one embodiment, the sensor includes a connection to an upper surface of the device. A detection element between each pad. In another embodiment, the element is a gas sensing film. In another specific embodiment, the component of the element is zinc oxide. In a specific embodiment, the component detects sound, and the MOS circuits include an audio processor for processing signals from the components. In another aspect of the present invention, there is provided a sensor device for producing any one of the above specific embodiments. The method includes the following steps:-manufacturing the MOS circuits in the substrate,

W-manufacturing the interconnect levels in a continuous manufacturing cycle according to the interconnect design to interconnect the MOS circuits, and-fabricating the sensor electrodes and dielectrics in a final interconnect level. 100710.doc 200540957 In a specific embodiment, the method is another step on the top interconnect level / children passivation layer. In another specific embodiment, the method ^ s ^ ^ ^ Λ 10,000 includes the following steps: a __stop layer is deposited on the interconnect layers, and the mother-dielectric layer, and on top of the cough A stop material is deposited on the interconnect level dielectric to provide a purification layer. In another embodiment, a porous oxide system is provided as a dielectric in the lower interconnect level, and a common oxygenated compound is used as a dielectric in the upper interconnect level.

In a specific embodiment, a strained low-noise amplifier is deposited in the upper interconnect layer of the anti-jitter antenna, the amplifier including a strained silicon region. [Embodiment] Gas / Humidity Sensing Apparatus · Imagine an Example Referring to FIG. 1, a single-chip wireless sensor includes a microcontroller 2 connected to a wireless antenna 4 through a transmitting / receiving interface 3. The microcontroller 2 also

It is connected to an 8kB RAM 5, a USB interface 6, an RS232 interface 8, a 64kB flash memory 9, and a 32kHz crystal 10. In this specific embodiment, the device 1 senses humidity and temperature, and a humidity sensor 1 is connected to the microcontroller 2 through an 8-bit A-to-D converter 12, and A temperature sensor 13 is connected to the microcontroller 2 through a 12-bit SAR A to D converter 14. The device 1 is a monolithic chip manufactured in a single process. In this single process, the electronic components and sensor components are manufactured by using standard CMOS processing technology. An integrated program obtains electronic components and sensing components. 100710.doc 200540957 Referring now to Figures 2, 3 (a), 3 (b), and 3 (c), the process 20 will be described in more detail, including steps 21-27. 21. Front-end processing A CMOS well, isolation oxidation, polycrystalline silicon, and implantation processing are performed on a silicon substrate 41 to form a MOS device, which is well known in CMOS processing. A pair of temperature-sensitive PNP transistors are also formed in the substrate to provide the sensor 1322. The lower interconnects and dielectric deposition form first, second and third interconnect levels 42. This includes three cycles of chemical vapor deposition (CVD) of a porous low & silicon dioxide dielectric 42 (a) and etching and copper plating operations to provide interconnect traces 42 (b). Each cycle ends by depositing an etch stop layer 42 (c) to limit the degree of etching in the next cycle. This etch stop material is silicon nitride ShN4. The dioxide; epsilon, the interconnect metal, and each cycle of etching stop forming a three-level stack 42 of the first interconnect. The use of a low κ dielectric allows lower capacitance to be used for faster signal transmission between components. 23. Upper interconnect and CVD dielectric deposition. Form fourth and fifth interconnect levels 43. There are two other dielectric deposition and metal interconnect plating cycles. However, in these two cycles, the dielectric is "ordinary" Si02 (non-porous) 43 (a) to obtain better structural strength to offset the porous dielectric in the lower levels 42 Weaker mechanical strength. Again 'the cycles include standard CMOS technology. The fifth level includes a heating element 43 (b), which has an internal temperature monitor for instantaneous temperature during instantaneous heating and purification of the humidity sensor ii 100710.doc -10-200540957 Surveillance. Furthermore, let η be called 1 and the part of the formation of the 4th and 5th levels of the Matz Temple. This procedure adds a thin metal plate for a capacitor section metal (CTM) with a thin layer in between (〇 4 μηι) dielectric material to form a mixed signal metal-insulator-metal (MI) capacitor for-the two A to D converters. 24 'SiO2 and cvD deposition at the sensing level form an interconnect / sensing layer 44. This is only the next repetition or cycle following the previous interconnection and plating cycle, and the dielectric is indeed the same as the dielectric used to directly and continuously climb the previous cycle, namely "normal" Si02. However, as an integrated part of the electroplating of the top interconnect layer 44, a humidity sensing capacitive mating finger (electrode) 45 and a reference capacitive mating finger (electrode) 46 are formed. The size and spacing of the fingers are selected to be suitable for the application. In this specific embodiment, the interval between the fingers 45 and 46 is 0.5 μm. Figure 3 (b) shows this configuration more clearly. Using an oxide dielectric constant of 3 · 9, this will result in the following capacitance: • C〇X = = ~ ^ 5 X10-6 ° = a_069F / m2 = 0.067 per actual capacitance The structure is approximately the size of a pad, allowing each finger to have a total length of 4000 μm. For a metal thickness of 1 μm, this results in a sensor capacitance of 0.276 pF. However, the capacitance between two closely spaced narrow conductors may be approximately greater than the value calculated from a simple parallel plate • greater than approximately 10% to 30%, due to edge components. 25. The deposition of the Si3N4 passivation layer is similar to the deposition of the traditional etch stop layer by CVD to deposit a 100710.doc 200540957. However, the purification layer protects and a water-gas barrier passivation layer 48 because the passivation layer 48 is also Si3N4. 48 is approximately 3 to 5 μm thick to provide a physical barrier to the device. 26. The passivation layer etched on the sensing electrodes is formed to a depth of one part of the purification layer 48 on the sensing electrodes 45 to leave a layer of about 0 μm deep on the sensing electrodes. 48 (a).

CVD deposition of 27 'porous oxide. It is seen that by CVD, the same material as that used as a dielectric in the first three layers is deposited in the recess formed in step 26. This system has “larger material area” -water vapor sensing film 49. The entry of gas or water vapor causes the dielectric constant of the porous dielectric substance to change. This causes a change in the capacitance of the lower sensing electrode 45. From the above, it is clear that the standard deep sub-micron CMOS processing technology is used, so that we can see fully integrated production. Using the same dielectric and interconnect metal layers, the sensing is performed simultaneously with the rest of the wafer. This "standard C deletion" method is advantageous for achieving this sensing and mass manufacturing. Previously, no obvious attempt has been made to this method, because there is a view that this sensor will require polymers, and gold or platinum plating and / or other non-standard materials', and these materials are in modern CMOS wafer Manufacturing plants will be regarded as pollutants "Si02-based components are obtained to reduce capacitance = development decomposes the internal lattice structure. This makes these compositions porous and adapted to water vapor or gas penetration. Moreover, in the sensor architecture, the silicon nitride (Si # 4) is subjected to CMOS processing to obtain an etch stop layer to serve as a barrier 100710.doc -12- 200540957 barrier layer to protect the integrated device. In the above specific embodiment, the layer is on the sensing component, and it acts as one of the barriers to the sensing of water vapor ingress, because such penetration may rot other electrodes in a high humidity environment. Therefore, the sensing is based on the use of spillover effects, as explained below. Use of the device 1 On the day of use, water vapor enters the film 49 so as to affect its dielectric constant, and thus affect the fringe field between the sensing fingers 45. This point is illustrated by a straight line 55 in Fig. 3 (c). This occurs even if the water vapor is blocked by the layer judgment and cannot reach the space between the sensor fingers 45. The sensor 1 relies on the edge component 55 of the field between the electrodes. For the illustrated 4000 μm, 〇27 pF structure, the edge assembly is approximately 25 to 50 fF. Because the eight-bit eight to zero converter is in close proximity (directly below the sensor), small capacitance changes can be detected even in the fringe field. Figure 4 shows this converter, where the sensing fingers 45 are Cs and the reference fingers 46 are Cr. These capacitors form the differential front end of a second-order oversampling sigma-delta modulator, thereby explaining the degree of integration of these sensors and converter components. Heart and Vs provide proportional and offset compensation. High resolution is achieved by using a sampling filter to balance the number of samples per second with the oversampling ratio. Referring to FIG. 5, in this specific embodiment, a porous material 50 is deposited (or printed) on top of the passivation layer 51 and eliminates an additional etching step. However, if the right purified thickness is, for example, 3 μιη, the interval between the sensor capacitor fingers 45 must be increased to about 5 μχη or more so that the edge capacitor components still present a measurable total capacitance ratio . For a 400 μm sensor structure, 100710.doc 13 200540957 the total capacitance is now reduced to about 27 fF, and the variable edge component is now in the 3 to 5 fF region. A humidity change of 1% or 2% now causes a capacitance change of less than a femto farad. This capacitance change can still be detected by a very oversampled differential sigma-delta high-resolution converter. 18-bit resolution is also provided-a large dynamic range, so that the converter can easily handle the highly variable and non-linear capacitor-to-humidity characteristics unique to different oxides, as well as different wafers and different batches Second and different hole sizes. Referring to FIG. 6, in this specific embodiment, standard CMOS processing is used without additional processing steps. Polyimide is commonly used as a "stress release" coating on silicon wafers. The location of the polyimide is generally determined by the slightly oversized version of one of the welding masks. In this example, the polyimide mask includes an additional opening to eliminate polyimide 60 from the reference capacitor. Because the polyimide is porous, the portion of the sensing capacitor now undergoes a small change in capacitance versus humidity. Referring to FIG. 7, in this specific example, a porous low-scale oxide dielectric is used in all interconnect levels of the device, so the sensor device has a gap between the capacitive mating fingers 71. Porous low-κ dielectric 70. By placing a "dummy" pad passivation opening on the sensor structure, the surface 72 on the sensing fingers 71 is exposed during the Zen pad #engraving to allow water vapor to enter the fingers Within the dielectric between objects. This leaves a passivation layer 73 on the entire area except the sensing capacitive fingers 71. One advantage of this embodiment is that it uses standard CMOS programs without any additional masking. However, it allows water and gas to reach these capacitive fingers 71. However, for many applications, this is not a problem, for example, a low humidity office 100710.doc -14- 200540957 office% 丨 the sensor in the brother only experienced a few milliseconds every few minutes Volt voltage. Figure 8 shows a simple fill configuration to close the single-chip wireless sensor. The sensor is adhered to a battery 80 by a conductive adhesive 81, and therefore has an envelope 82. A coil bobbin is used to keep the area on the sensing assembly clear. All other areas are enclosed by a package 82, which provides physical protection and protection of these wafers and battery terminals from corrosion or electrolyte degradation during continuous exposure to high humidity conditions. Except for an RF antenna wire 83, no metal is exposed anywhere. Alternate systems may not have any packaging if physical protection is less important and / or if response time to temperature changes is more important. Temperature sensor In addition to the metal heater temperature sensor 43 ^) described above, a substrate PNP temperature sensor 13 and an integrated part of the substrate 41 are formed, as shown in FIG. 3 (a). This depends on the well-known -2.2 mVMVbe unique to the base emitter junction. With a combination of humidity and temperature sensors in a device, an increased read value (ie, dew point) can be calculated by the microcontroller. These factors, together with the microcontroller 2 and the flash memory 9, allow the use of look-up tables to scale and calibrate to achieve an accuracy of 0.5. Within. Referring to Fig. 9, a 12-bit SAR converter 14 is shown. This converter measures the Vbe voltage of the PNP, or-as shown in the figure-the temperature-dependent resistance of a metal heater monitor in a bridge configuration. The converter achieves 12-bit resolution without any calibration circuitry, as explained below. Referring to Figure ⑺, the electrical valley device array that was converted to 14 with 100710.doc -15- 200540957 at the center of the hierarchy is at the center of this level, and t is surrounded by eight similar dummy arrays 90 to ensure that the layout is unchanged and the converter The core array valley transformer in 14 has excellent matching. The array is divided into seven upper-position elements and a 5-bit sub-DAC via a coupling capacitor Cc. This, together with a small unit capacitor size of 7x7 μηη, keeps the capacitance (Cs) of the entire array to about 8 pF, which is small enough to make it an on-chip buffer amplifier that can be illustrated efficiently. Driven, and small enough to minimize the overall mismatch due to gradients in oxide thickness or other processing parameters. At the sampling frequency of ΙΟΟΚΗζ, the kT / C noise figure is 14nV, which is much lower than the 12-bit lSB size that exists on metal 5 (fifth level). These capacitors have very small parasitic capacitance for the substrate. This simplifies the matching of the valley trough. The metal-insulator-metal (MIM) structures of these capacitors produce lower voltage and temperature coefficients and parasitic resistance. Flash microcontroller With 8-bit microcontroller 2 and 64KB flash memory 9 on the same chip as these sensors, it can significantly improve accuracy and functionality. This is due to instant continuous calibration or in-situ calibration for various temperature conditions. This amount of memory is also sufficient to accommodate the entire IEEE802 · 5 · 4 protocol and Zigbee software stack to perform key requirements for beacons, point-to-point, star and mesh networks, and modern wireless sensor networks. An on-chip regulator generates 1.2 V to activate most microcontrollers, memory blocks, and radio frequency transceivers manufactured on thin oxide minimum geometry devices. To help reduce power, the logic of the time interval counter and the interrupt logic of the microcontroller is implemented on a thick oxide 3.3 V transistor, as shown in Figure 11 100710.doc -16 · 200540957. This point indicates that when the chip is in the sleep or power-down mode, the regulator can be turned off to eliminate the DC bias current of the regulator. This, together with the near-zero subcritical leakage of the 3 V transistor, results in significant power savings and extended battery life. -Once waking up from power-down mode, the microcontroller also reduces noise and substrate crosstalk by operating the sensors, converters, and wireless transceivers in sequence.

Looking now at the wireless transceiver 3, and especially the low noise amplifier (LNA), the LNA is designed to have additional low power and low noise operation. This is achieved by using steel inductors on the fifth or sixth level and using strained silicon MOS devices for the front-end LNA, see Figure 12. This figure shows-a thin layer of rhenium germanium, on which there is a thin layer of rhenium, the thin strained stone layer HH has a higher carrier mobility than ordinary rhenium. The polycrystalline stone closed pole 102 forms a channel in the strained dream region. However, because germanium has a higher mobility ', most of the transistor current flows in which region of the subsurface, resulting in lower noise operation and higher gain. Therefore, for the same gain, the LNA can be biased to a lower current, thereby saving battery power. The resistance of copper is lower than that of Ming, which results in a higher Q factor (producing a car with the same connection) and increasing profit). The fifth or sixth level of copper is also thicker (low resistance) and more retreated from the substrate (smaller parasitic capacitance). Referring to FIG. 13, a frequency selection for the radio frequency transceiver 3 is shown. The device 1 forms a node in a point-to-point wireless network. This could be a simple point-to-point link or a star or mesh network. All nodes use a fixed frequency and the δH1 wireless interface 3 provides a slow frequency hopping solution to solve the dry work factor. All nodes initially operate the radio using the same frequency = 100710.doc -17- 200540957 3. —Dan—Transfer failure indication may have interference. The u says that the sun, the moon, the sun, the earth, and the earth; it must move to—different frequencies. Next, all the Lang points are synchronized. All nodes are pre-programmed with a hopping sequence for the frequency hopping scheme to be operated. Further, the nodes must be initialized to the same channel so that they can “jump”, which is generally implemented after installation or battery.

In more detail, after the installation (or battery replacement), the installer will manually put the node into "initialization" mode by pressing a button, for example. : After ‘this node turns on its receiver for a nearby node transmission (or master beacon) and“ listens ”, for example, on channel 0. If it does not receive any content after a suitable time (for example, a few seconds or minutes) (because the current channel may be blocked), then it steps down to the channel in order, and waits and crosses again:. Finally, by this method 'it should receive a message = or a data packet from a neighboring node', then it can re-synchronize its timer, request to skip the sequence to join the β-hai sequence, and enter sleep mode Until the next hop and transmission cycle. This initialization method means that the node must remain "on" only during installation to enter the king power receiving mode, and then it can return to sleep 99.9% of the time during the 1 to 3 years of use of the battery Mode (as defined in the 802.15.4 standard). Because the 8G2154 standard allows a sleep cycle of up to about 4 minutes, the node may be in full power reception mode during this duration. In practice, however, this situation is not possible because the installer will understand the cycle. The installer can roughly predict when the next beacon transmission is due by using a spectrum analyzer (or a wireless "sniffer" with 100710.doc -18- 200540957), and press " Initialize "button. Referring to FIG. 14, this figure shows an example of using the slow jump scheme. It is used on a long-distance (200 m) link 115 between two buildings 12 and 125 (using a 14 dBl directional antenna on a gateway node 126 connected to a computer 127). . A standard 802 · 15 · 4 Zigbee fixed channel star network, one of the nodes 121, is implemented in the first building 120. This situation makes it possible to install nodes from multiple vendors that can operate together in a star network factory monitoring application, and using this slow hopping algorithm on long-distance critical links has a greater risk of interference. Testing and Calibration Traditionally, this has been difficult for humidity sensors, which require special rooms with controlled humidity and consequently require special packaging disposal and electrical connections. In the present invention, since the entire humidity sensor is manufactured in a standard CMOS procedure, it can be tested and calibrated in a general wafer-level test before wafer shipment. This takes advantage of the fact that it is typically tied to a precise humidity level, such as 40% relative humidity, for operating wafer probers and factory test areas. This known value can be stored in the flash EEPROM memory on the chip for later use by the microcontroller to correctly calibrate the output value under software control, or it can be used in the chip. In a non-flash EEPROM version, the sensor is calibrated by blowing a polycrystalline fuse at 400/0 RH. For many applications, such as office air conditioning control around a set point (typically 40%), this i-point calibration may be sufficient. If greater accuracy is required over a wider range of humidity, a second calibration point may be required for 100710.doc -19- 200540957. This is accomplished by performing a "two-run" wafer probing in a closed chamber at 85% RH or in a dry nitrogen desiccant chamber (0.001% RH). Although these two operational wafer tests add some additional cost, they are significantly smaller than package-based tests. In another specific embodiment, as illustrated in FIG. 15, the position of one of the plurality of differential capacitors 132 of the 18-bit ΣΔ A to D converter 12 on the passivation layer m is shown in FIG. 15. , Deposit zinc oxide and iron oxide film 13. The oxides are synthesized by a sol-to-gel process and heated to about 120 ° C to 200 ° C. (:, And then deposited by hybrid inkjet deposition. The thin film means that small finger-sized spaces can be used in the sensor structure, and the high-resolution A to D converter means that small sensors can be used The structure also causes small detectable changes in the valley, even at room temperature operation.

FIG. 16 shows an alternative embodiment in which the iron oxide / zinc oxide i4Q system is deposited on the top oxide layer or passivation layer 141, but is directly connected to the electrodes 142 in the top metal layers, thereby forming a resistor The value of the resistor may be determined by the 8-bit converter as part of a bridge circuit. By using different materials instead of oxide 130 in FIG. 15, the device architecture and production sequence may be adapted for sensing different gases, such as using ε for hydrogen sensing, and using oxidation for s02, H2S # , Or use plasticized polyethylene for n02, and wo for isoτ. In each case, the incoming gas will be changed by adsorption, physical absorption or chemical absorption. 100710.doc -20- 200540957 changes the conductivity and dielectric constant of the sensing material. Therefore, the capacitive embodiment of FIG. 15 and the resistive embodiment of FIG. 16 may be used instead of or in combination with a tightly integrated high-resolution converter on the chip, thereby measuring a gas concentration with a very low ppm value. Audio sensor

Alternatively, a piezoelectric polymer can be used in the configuration shown in Figure 16 to obtain sound sensitivity. Conversion is mainly based on changes in conductivity. In this case, at the MOS circuit level, a bridge circuit having a buffer driving the 8-bit a to D converter is used to capture the audio signal. An audio sensor (microphone) is a useful emulation on a remote wireless node. For example, if a motor is running or if an alarm is sounding, it can be used for "listening". Due to the 0.1% duty cycle of IEEE802.15.4, it is necessary to configure this audio frequency. The maximum data rate of 250 Kb / s in the 802 · 15 · 4 2 · 4 band corresponds to 25〇b under the condition of 0.1% duty cycle. / sOne does not continue to change the #data rate. Uses a bit-variable-rate audio I-reducer block (VBR) to obtain a compression ratio of 15: 1 or better, resulting in a 375

The effective audio bit rate of Kb / s is sufficient to meet the low-level audio requirements of many industries. Optical sensor. The device may further include an optical emitter i 50 and a linear detector. Referring to FIG. 17, the depth of the anisotropic etching is exposed, thereby exposing a light of 2 μm × 500 μm, which is 1 51. At the end of the general process, all six or seven-layer polar body photo-sensors 151, a large pn junction (200 photons are collected and a corresponding Current). 100710.doc -21-200540957 In this specific embodiment, the job is also revealed-the porous dream area i50, this area] 50 is at the beginning of the procedure by 2 lines of electrochemical etching of the substrate in this specific area Instead. Passing current through this area makes this area act as a light-emitting diode (LED) due to the well-known luminous properties of Kong Xi, and the isolation trench placed around the delta area can make leakage Any current to the substrate is minimized and light efficiency is improved. The technique of performing electrical etch to form multiple cuts is well known to those skilled in the art, and this technique can be used in some CMOS programs, but it is not standard in most CMOS programs. An alternative structure is a doped polymer organic light emitting device. In the manner shown in FIG. 16, a hybrid inkjet printing was used to deposit a patterned light-emitting doped polymer film (such as a polyvinyl chloride (PVK) film) directly onto the electrode. The invention is not limited to the specific embodiments described but may vary in construction and detail. For example, conductors other than copper can be used for such interconnections, such as aluminum. Moreover, the sensor device may be a "peeled" version of one of the sensors, namely a "humidity to digital" sensor chip, which does not have a wireless or microcontroller or flash memory. In this case, the calibration of the A to D converter and the sensor is achieved by blowing the voltage reference circuit and various polycrystalline fuses in the capacitor array. It should be noted that testing does not need to include testing every code of the A to D conversion frame, thereby significantly simplifying testing and reducing costs. Moreover, in methods and devices other than those described in the above specific embodiments, one or more of the following features may be provided individually or in combination:-using strained silicon as a low noise amplifier, 100710.doc -22- 200540957-low frequency channel selection / skipping,-copying the SAR of the capacitor array,-porous silicon LED,-audio piezoelectric polymer microphone sensor,-audio compression and transmission under low load cycling conditions, -Microphone features. [Brief description of the formula] From the following descriptions of some embodiments will be made only in the phase_transition mode, and the present invention will be more clearly understood. In these drawings, Fig. 1 is the present invention- A block diagram of a single-chip wireless sensor device; Figure 2 is a flowchart illustrating a procedure for manufacturing the device; Figure 3 (a) is a cross-sectional view of the device, and Figure 2) is a plan view of a sensing electrode; Fig. 3 (a) shows an edge electrical fence between the electrodes; Fig. 4 (a) shows a schematic diagram of an eight to ten converter of the device; and Fig. 5 (a) shows a sensor assembly of an alternative embodiment ; Figures 6 and 7 are cross-sectional views of alternative sensor components; Figure 8 is a diagram of a filling configuration for the final package; Figure 9 is a -12-bit octal-to-zero converter for the sensor device Circuit diagram; Figure 10 is the layout of the capacitor array used in the SAR converter; Figure 1 is a block diagram of the microcontroller of the device; Figure 12 is a primary surface shown in a strained silicon transistor of the device Section view of current flow path; 100710.doc • 23- 200540957 Figure 13 illustrates nothing A diagram of frequency selection of a transceiver; FIG. 14 shows a communication scheme for a device of the present invention; FIG. 15 is a cross-sectional view of a gas sensing device; FIG. 16 is a schematic break of an audio sensor FIG. 17 is a cross-sectional view of an LED and a photodiode, which is a device according to a specific embodiment of the present invention. [Description of main component symbols]

1 Single-chip wireless sensor 2 Microcontroller 3 Transmit / receive interface 4 Wireless antenna 5 8kB RAM 6 USB interface 8 RS232 interface 9 64kB flash memory 10 32kHz crystal 11 Humidity sensor 12 A to D converter 13 Temperature Sensor 14 SAR A to D converter 41 Silicon substrate 42 Stack of interconnect levels 42 (a) Dielectric 42 (b) Interconnect trace 100710.doc -24- 200540957 42 (c) Etch stop layer 43 Fourth and fifth interconnect levels 43 (a) dielectric 43 (b) heating element 44 interconnect / sensing layer 45 humidity sensing capacitive mating finger (electrode) 46 reference capacitive mating finger (Electrode) 48 Passivation layer 48 (a) Thin Si3N4 layer 49 Water vapor sensing film 50 Porous material 51 Passivation layer 55 Line / edge component 60 Polyimide 70 Porous low-K dielectric 71 Capacitive mating finger 72 Sensing surface on finger 71 Purification layer 80 Battery 81 Conductive adhesive 82 Package 83 Radio frequency (RF) antenna wire 90 Dummy array 100 Silicon germanium thin layer 100710.doc -25- 200540957 101 Thin strained silicon layer 102 Polycrystalline silicon Gate 115 Long Link 120 Building 121 Node 125 buildings 126 gateway nodes 127 computers

130 Zinc oxide and iron oxide film 131 Passivation layer 132 Differential capacitor 140 Iron oxide / zinc oxide 141 Top oxide or passivation 142 Electrode in top metal layer 150 Optical emitter / porous silicon area 151 Detector 100710.doc- 26-

Claims (1)

200540957 10. Scope of patent application: 1 · An integrated sensor device, including: · a MOS circuit in a semiconductor substrate, an interconnection level, which has an interconnection conductor and an insulating dielectric, and the levels are on the substrate And interconnect the MOS circuits, the interconnect levels are incorporated into a sensor with electrodes embedded in the interconnect dielectric, and the MOS circuits include One of the signal processor electrodes. 2. An integrated sensor device as requested, wherein the sensor contains-a porous oxide to allow one of the sensed gases or moisture to enter. 3. The integrated sensor device as claimed in claim 1, wherein the sensor comprises-a porous oxide to allow a gas or moisture to be sensed to enter, and wherein the porous oxide is Si doped with carbon. . 4. If requested! The integrated sensor device, wherein the sensor is a capacitive sensor. "5 · 如 # Find the integrated sensor device of item 1, wherein the sensor includes a porous oxide to allow a gas or moisture to be sensed to enter, and wherein the sensor includes a The passivation layer on the sensor electrode. 6. The integrated sensor device as claimed in item 5, wherein the porous oxide is deposited on the passivation layer, and the Mos circuits detect that it is between the electrodes. The variation of the fringe field between them. 7. The integrated sensor device of item 5 includes a stop layer between the interconnect levels, and the composition of the passivation layer and the silver The engraving stop 100710.doc 200540957 is the same as the composition of the material. 8_ If the integrated sensor device of claim 5 'includes the engraving separation layer between these interconnection levels, and the purification layer has The composition is the same as the composition of the engraved stop material, and the passivation layer is composed of a small 4. 9. The integrated sensor device such as kiss 5 in which the passivation layer is on the sensing electrodes 10. The integrated sensor device as described in item 5 above, wherein the passivation layer is on the sensing electrodes. The upper system is a depression, and there is a porous oxide film in the depression. Η · As requested! The integrated sensor device, wherein the porous oxide is between the electrodes and is exposed. 12 · 如 叫The integrated sensor device of claim 1, wherein the circuits are located directly below the sensor at a vertical height. 13 · If the integrated sensor device of claim 1, wherein the M0s The circuit includes a temperature sensor. 14. The integrated sensor device of claim 1, wherein the MOS circuit includes a temperature sensor, and wherein the temperature sensor includes a pNp transistor. 15 The integrated sensor device of claim 1, wherein the 1408 circuits include a temperature sensor, and wherein the MOS circuits include a microcontroller for processing a gas from the gas or humidity sensor Or a humidity signal and a temperature signal from the temperature sensor to provide an enhanced output. 16 The integrated sensor device of claim 15, wherein the enhanced output is a temperature-corrected gas or humidity reading. Π. The integrated sensor device of claim 1, The sensor includes polyimide deposited on the sensing electrodes. 100710.doc 200540957 18. If requested, the integrated sensor device, wherein the MOS circuit includes a connection to the An 18-to-0 converter between the sensor electrode and the processor. 19. The integrated sensor device of item 18 as described, wherein the eight-to-D converter includes an active A-to-D converter. The capacitor has a dummy capacitor array with a constant layout. 20. The integrated sensor device as claimed, further comprising a light emitting diode. 21. For example, the integrated sensor device of claim 20, wherein the two-pole system is opened in a deep trench to one of the sensor electrodes, such as the sensor, and the lower horizontal interconnection level. 22. The integrated sensor device of claim 1, wherein the device comprises an optical valence detector diode. 23. The integrated sensor device of claim 22, wherein the bipolar system is in a deep trench and in a lateral lower interconnect level of one of the sensor electrodes. 24. The integrated sensor device of claim 1, wherein the mOs circuits include a wireless transceiver. 25. The integrated sensor device as claimed in claim 24, wherein the wireless transceiver is used to communicate with other nodes in a network, and includes a means for detecting a disturbance immediately based on a low frequency Channel switching scheme is a component to switch channel frequency. 26. The integrated sensor device of claim 24, wherein an interconnection level includes a low noise amplifier. 27. The integrated sensor device of claim 24, wherein an interconnect level includes a low noise amplifier, and wherein the low noise amplifier includes a strained silicon region under a conductor 100710.doc 200540957. 28. The integrated sensor device of claim 24, wherein an interconnection level includes a low-noise amplifier, and wherein the low-noise amplifier includes a strained silicon region under a conductor, and wherein the strained silicon is in One of the fifth or sixth interconnect levels on the substrate. 29. The integrated sensor device of claim 1, wherein the sensor includes a detection element connected between a plurality of pads on an upper surface of the device. 30. The integrated sensor device of claim 29, wherein the element is a gas sensing film. 31. The integrated sensor device according to claim 29, wherein the element is a gas-sensing film having an oxide composition. 32. The integrated sensor device of claim 29, wherein the component detects sound, and the MOS circuits include an audio processor for processing signals from the components. 33 ·: A method for producing a sensor device according to any one of the preceding claims, the method comprising the steps of: manufacturing the MOS circuits in a substrate, and manufacturing the MOS circuits in a continuous manufacturing cycle according to an interconnection design The method of isolating the interconnection levels to interconnect the MOS circuits, and manufacturing the sensor electronics in a final interconnection level as claimed in item 33, comprises an additional step of a -passivation layer. A method of depositing a series of items 33 on interconnect levels' which includes the following additional steps: depositing a top passivation layer and a passivation layer; depositing an etch on each dielectric 100710.doc 200540957 layer in the interconnect levels A stopper layer is deposited, and an etch stopper is deposited on the top interconnect level dielectric to provide the passivation layer. 36. The method of claim 3 3, the porous oxide of the dielectric, the dielectric of the dielectric. Where a method is provided in the lower interconnect level and a common oxide system is used as the upper interconnect level 37. The method of claim 33, wherein a strained low noise amplifier is deposited in an upper interconnect level, the amplifier comprising One strain silicon area. 100710.doc