200540633 九、發明說明： 【發明所屬之技術領域】 發明領域 流排運用技術。 本發明是關於電腦系統内之匯 【先前技術】 發明背景 測定匯流排運用之技術在電腦系統中對 供有用的資訊。然而，現今對於這樣的測定=的提 複雜的軟體及/或硬體。例如 」μ牽涉 10 15 20 Γ或邏輯分析器功能用《解:方產法生包在:=之機 作’以紀錄資料行動之流程，及測量此等使 ^之動 置的效能等。更進一步地，現八 ，/爪排之裝 械襄置通常利用固定的演算法;流排的機 變更而且可能會引起負載不平^仏機械裝置是不容易 的傳輸量同時會使其他 固定次序”機構内，一此f置、1置狀心。例如，在一” 排授與運作，例如，：ί Π一預先定義次序被-匯流 裝置等。然而，如果每!裝-第:裝置、及-第三 母時間内此匯流排授與此裝个相專於 將會引起負載不平衡。 的貝料傳达數置，這機構 【發明内容】 發明概要 本發明係有流排運用 指示在匯輯巾資料被傳送之期 技術。在一實施例中，一 傳送信號之工作週期也被用 早位時間Μ料親數量被決定。此 以剛定匯流排之運用，此外， 5 200540633 此匯流排運用技術被用以仲裁匯流排，以平衡匯流排負載 等。 圖式簡單說明 本發明係藉由附隨圖式所示之範例說明，但不應受限 5 於此等圖式，在各圖式中相同的標號係用來表示類似之元 件，且其中··第1圖顯示可實施本發明的實施例之系統； 第2圖顯示根據一實施例之用以說明依據資料傳送數 量提供匯流排運用之時序圖； 第3圖顯示根據一實施例之用以說明表示供多數裝置 10 匯流排之裝置用的資料傳送數量的信號產生的時序圖； 第4圖顯示一根據一實施例之可用以產生傳送信號之 直流(DC)成份的RC網路； 第5圖顯示用以根據傳送信號之工作週期說明匯流排 運用的圖式；以及 15 第6圖表示一範例電腦系統之圖式。 【實施方式】 較佳實施例之詳細說明 下列說明中用於作為解釋之目的，許多特定細節被提 出係用於對本發明提供完全的瞭解。然而，對於熟悉該項 20 技藝者所應知的是，不須這些說明細節即可施行本發明。 在其他實例中，為避免混淆本發明，習知的架構和裝置係 以方塊圖表不。 概述 第1圖顯示一可實施本發明之實施例之系統100,其包 括一處理器110、一橋接器120、及多數個裝置130。系統 6 25 200540633 100可被貫施在一晶片、晶片組的部件、或電腦系統的部件 等。 ’、、 通常設於電腦系統之處理器110係經由處理器匯流排 115而與橋接器120介接。 5 裝置I30可以是任何一種利用匯流排的裝置，例如， VGA(影像圖形陣列)卡、纖維通道裝置、scsi(小型電腦系 統介面）裝置、以及USB(通用串列匯流排）裝置等。 橋接器120橋接不同種類之匯流排的一 • 之匯流排的另一端，例如，包括匯流排115和125。依據不 10同情況，橋接器120會利用一匯流排與一或多數個裝置13〇 連接。在第1圖的範例中，橋接器12〇利用匯流排125(1)、 125(2)及125(3)來與VGA卡130⑴、纖維通道裝置13〇⑺、 及scsi裝置130(3)個別地連接。另外，橋接器12〇利用匯 流排125⑷來與SCSI裝置13〇⑷、纖維通道裳置13〇(5)、 15 USB裝i 13〇⑹、及基板管理控制器_c)i3〇⑺連接。橋 接器12〇可代表處理g 11〇動作以從裝置13〇開始資料傳 送及開始到裝置130之資料傳送及/或在裝置13〇間開始資 • 料傳送。、f 一實施例中，橋脑-包括一用於仲裁匯流 排之仲裁杰1210。第1圖顯示一用以圖示說明目的之橋接 器。然而，取決於實作成果，其可設置一個以上之橋接器 120 〇 匯流排，例如115 A 125，制於讓龍在系統1〇〇 ^其^件及/或可具體化系統_之電腦系統之裝置間傳 C之u又備這些匯流排的種類包含周邊組件互連(pCl)、辦 25強型PCI(PCI_X)、工業標準架構邪⑷，似擴充、内部積 體電路(I C)等。然而，本發明的實施例並不受限於這些匯 200540633 匯 用至其他種類的匯流排。裝置可在 根據資料傳送數目之匯流排運用技術 或每匯流排運用係根據資料傳送數量及/ 分等。在蚊的，㈣，微秒、秒、 處產生以及表亍每—㈣傳送在匯流排時鐘之升緣 時鐘信號作邏輯的信號係動作為高態及與匯流排 10 15 20 傳送時間與這段時間之資料傳送數量，= 傳送數量可利用夂接、止 母早位時間之資料 理器等之軟"及計數器及計時器、邏輯電路、處 : '、硬體中之一者或組合等不同的彳i彳tfn 二，當-計數器計算—時段内之脈衝運 位時間之傳送^日^ 間等。本發明在計算每單 件或其組合m 祕特錄體或硬體的特定部 麗130(7)提供每單位時間之資料傳送數量。 用 據勺流排的類型的情況而^ ’此傳送期間係根 據包括此牵涉資料傳送之裝置的，，備妥，，信號與此預備用以 開始的傳㈣域信號㈣來運算。例如，在PCI匯流排 裝置中’此要求資料傳送的裝置通常稱為啟動器裝置，其 開始一起始器備妥信號，，，例如信號IRDY。在回應上，此 目標裝置，當備妥時，判定一”目標備妥信號，，，例如信號 TRDT。因此，此傳送期間是一當此起始器備妥信號 與目標備妥信號TRDY均被判定之期間。任一地，對於isa 匯流排裝置而言，其只有使用一備妥信號，例如信號RDY， 此傳送期間是一當RDY信號被判定的期間。 8 25 200540633 第2圖顯示用於說明根據貧料傳送數量提供匯流排運 用之時序圖。基於方便說明之故，資料在橋接器12〇與VGA 裝置Π0(1)之間的PCI匯流排125(1)内傳送。 信號線210顯示匯流排時鐘信號CLK，其通常係利用 5 於系統，且為方便說明之故，一資料傳送在信號clk 之昇緣處產生。 信號線220顯示一 ”起始器”備妥信號iRDY，其係由橋 接器120判定以指示橋接器120已經備妥去進行傳送。在 此範例中，信號IRDY係判定為低態。 10 信號線230顯示一”目標”備妥信號TRDY，其係由目 標VGA裝置130(1)判定以指示VGA裝置130(1)對於資料 傳送已經備妥。在此範例中，信號TRDY係判定為低態。 4吕號線240顯示一指示資料傳送期間之時間之信號 TRANSFER，例如，在橋接器120與VGA裝置130(1)之間。 15為方便說明之故，信號TRANSFER係動作為高態，且在此 實施例中，其係從一以信號IRDY及TRDY做為輸入之邏 輯非或(NOR)閘產生。 信號線250顯示一信號TRanSFERNUM，其指示當信 號TRANSFER被判定時，在此時段之個別資料傳送。在一 20範例中’化號TRANSFERNUM係由一以信號TRANSFER 與CLK做為輸入之邏輯及（AND)閘產生。而且，信號 TRANSFERNUM中具有7個脈衝，因此在tRANSFEr之 時段具有7次傳送。200540633 IX. Description of the invention: [Technical field to which the invention belongs] Field of invention Streamline application technology. This invention relates to sinks in computer systems. [PRIOR ART] BACKGROUND OF THE INVENTION The technology used to determine the use of buses provides useful information in computer systems. However, today such assays involve complex software and / or hardware. For example, “μ” involves 10 15 20 Γ or the logic analyzer function uses the “solution: method of production method to enclose in: = 's operation' to record data flow, and measures the effectiveness of these moves. Furthermore, the current installation method of the claw row usually uses a fixed algorithm; the machine of the stream line is changed and the load may be uneven. 仏 The mechanical device is not easy to transmit and it will cause other fixed orders. " Within the organization, there are f and one center. For example, grant and operate in a row, for example: 一 a predefined sequence is-the convergence device, etc. However, if this bus is assigned to this device every time you install-the first device, and-the third time, it will cause load imbalance. This mechanism conveys the number of materials, this mechanism [Summary of the invention] Summary of the invention The present invention is a streamlined application technology to indicate the period of time when the repertoire data is transmitted. In one embodiment, a duty cycle of transmitting a signal is also determined by the number of data sources in the early bit time. This is to determine the use of the bus. In addition, 5 200540633 this bus application technology is used to arbitrate the bus to balance the bus load. Brief Description of the Drawings The present invention is illustrated by accompanying examples shown in the drawings, but should not be limited to these drawings. The same reference numerals in each drawing are used to indicate similar elements, and Figure 1 shows a system that can implement an embodiment of the present invention; Figure 2 shows a timing diagram illustrating the use of a bus based on the amount of data transferred according to an embodiment; and Figure 3 shows a timing diagram of an embodiment according to an embodiment A timing diagram illustrating the generation of signals representing the number of data transfers for the devices of the majority of the 10 buses; FIG. 4 shows an RC network that can be used to generate a direct current (DC) component of a transmission signal according to an embodiment; 5 The figure shows a diagram for explaining the use of the bus according to the duty cycle of the transmitted signal; and FIG. 6 shows a diagram of an example computer system. [Embodiment] Detailed description of the preferred embodiment In the following description, for the purpose of explanation, many specific details are provided to provide a complete understanding of the present invention. However, it should be known to those skilled in the art that the present invention can be carried out without these details. In other examples, to avoid obscuring the present invention, conventional architectures and devices are shown in block diagrams. Overview Figure 1 shows a system 100 capable of implementing an embodiment of the present invention, which includes a processor 110, a bridge 120, and a plurality of devices 130. System 6 25 200540633 100 can be implemented on a wafer, a chipset component, or a computer system component. The processor 110, which is usually provided in a computer system, interfaces with the bridge 120 via a processor bus 115. 5 Device I30 may be any device using a bus, such as a VGA (Image Graphics Array) card, a Fibre Channel device, a scsi (Small Computer System Interface) device, and a USB (Universal Serial Bus) device. The bridge 120 bridges the other end of one of the different types of buses, for example, including buses 115 and 125. Depending on the situation, the bridge 120 is connected to one or more devices 13 using a bus. In the example in FIG. 1, the bridge 120 uses the busbars 125 (1), 125 (2), and 125 (3) separately from the VGA card 130⑴, the fiber channel device 13⑺, and the scsi device 130 (3).地 连接。 Ground connection. In addition, the bridge 120 uses a bus 125⑷ to connect to a SCSI device 130⑷, a fiber channel device 13〇 (5), a 15 USB device i 13⑹, and a baseboard management controller_c) i303. The bridge 120 may represent a process g 110 action to start the data transfer from the device 130 and the data transfer to the device 130 and / or start the data transfer between the devices 130. , F In one embodiment, the pons—includes an arbitration master 1210 for arbitrating the bus. Figure 1 shows a bridge for illustration purposes. However, depending on the implementation results, it can be provided with more than one bridge 120 bus, such as 115 A 125, which is made by the system of the computer and its computerized system The types of buses between devices include these types of buses: Peripheral Component Interconnect (pCl), Top 25 PCI (PCI_X), Industrial Standard Architecture, Expansion, Internal Integrated Circuit (IC), etc. However, the embodiments of the present invention are not limited to these sinks 200540633 and are applied to other kinds of buses. The device can use the technology based on the number of data transfers, or the number of data transfers and / or points per bus. In mosquitoes, ㈣, microseconds, seconds, places, and tables 亍 each-㈣ sends the rising edge clock signal of the bus clock as a logical signal system to move to the high state and the bus 10 15 20 transmission time and this section Time data transmission quantity, = The number of transmissions can use the software " of the data processor such as the connection and the mother's early bit time, and counters and timers, logic circuits, processing: ', one or a combination of hardware, etc. Different 彳 i 彳 tfn Second, when-counter calculation-transmit pulse pulse time within time period ^ day ^ time and so on. The present invention calculates the number of data transmissions per unit time in the specific part of the special record or hardware of each unit or combination. 130 (7). According to the situation of the type of the scoop, ^ 'This transmission period is based on the equipment involved in data transmission, and is ready, and the signal is calculated with the transmission domain signal which is used to start. For example, in a PCI bus device, this device that requires data transfer is often called an initiator device, which starts an initiator ready signal, such as the signal IRDY. In response, the target device, when ready, determines a “target ready signal, such as the signal TRDT. Therefore, this transmission period is a time when the initiator ready signal and the target ready signal TRDY are both Judging period. Either way, for the isa bus device, it only uses a ready signal, such as signal RDY, and this transmission period is a period when the RDY signal is judged. 8 25 200540633 Figure 2 shows the The description provides the timing diagram of the use of the bus according to the quantity of lean material transmission. For convenience of explanation, the data is transmitted in the PCI bus 125 (1) between the bridge 12 and the VGA device Π0 (1). The signal line 210 shows The bus clock signal CLK is usually used in the system, and for the sake of explanation, a data transmission is generated at the rising edge of the signal clk. The signal line 220 displays a "starter" ready signal iRDY, which is Determined by the bridge 120 to indicate that the bridge 120 is ready for transmission. In this example, the signal IRDY is determined to be low. 10 The signal line 230 displays a "target" ready signal TRDY, which is the target VGA device. 1 30 (1) decides to instruct the VGA device 130 (1) to be ready for data transfer. In this example, the signal TRDY is determined to be low. 4 Lu 240 displays a signal TRANSFER indicating the time during the data transfer, For example, between the bridge 120 and the VGA device 130 (1). 15 For the convenience of explanation, the signal TRANSFER is high, and in this embodiment, it uses a signal IRDY and TRDY as input. A logical NOR gate is generated. The signal line 250 displays a signal TRanSFERNUM, which indicates that when the signal TRANSFER is judged, the individual data is transmitted during this period. In a 20 example, the 'transformation number TRANSFERNUM is a signal TRANSFER An AND gate is generated as an input with CLK. In addition, the signal TRANSFERNUM has 7 pulses, so it has 7 transmissions during the period of tRANSFEr.
在一實施例中’在複數個裝置匯流排上，例如匯流排 25 125(4)’其係耦合至一個以上之裝置，此由信號TRANSFER 所表不之傳送期間以及由信號TRANSFERNUM所表示之 資料傳送數量適用於所有匯流排上之裝置，例如，用於匯 9 200540633 流排125(4)之裝置130(4)、裝置130(5)、裝置130(6)和裝 置130(7)。然而，其可產生用於複數裝置匯流排之每個裝 置的TRANSFERNUM信號。 第3圖顯示用以說明個別的TRANSFERNUM信號是如 5 何產生而用於至匯流排125(4)的4個裴置130(4)、130(5)、 130(6)及130(7)之信號。為方便說明之故，裝置130(4)、 130(5)、130(6)及 130(7)係與 4 個”許可”信號 GNT—130(4)、 GNT_130(5)、GNT—130(6)及 GNT__130(7)個別地相關聯。 也就是，當信號GNT_130(4)被判定時，裝置130(4)所用之 10 資料被傳送；當信號GNT_130(5)被判定時，裝置130(5)所 用之資料被傳送；以及當信號GNT_130(6)被判定時，裝置 130(6)所用之資料被傳送，以此類推。為方便說明之故，在 第3圖中之許可信號係判定為高態。 信號線310顯示表示用於匯流排125(4)之資料傳送數 15 量之信號 TRANSFERNUM—125(4)。信號 TRANSFERNUM_125(4)可以第2圖所說明之方式產生，以 及如第3圖所示，包括11個脈衝以供4個裝置130(4)、 130(5)、130(6)及130(7)間之總數為11次傳送之用。 信號線320、330、340、350分別表示這些示範的許可 20 信號 GNT—130(4)、GNT—130(5)、GNT—130(6)及 GNT_130(7) 〇 信號線360、370、380及390分別顯示與裝置130(4)、 130(5) 、 130(6)及 130(7)有關之信號 TRANSFERNUM—130(4) 、TRANSFERNUM—130(5)、 25 TRANSFERNUM—130(6)及 TRANSFERNUM_130(7)。在一 範例中，每一個信號 TRANSFERNUM—130(4)、 10 200540633 TRAN S F ERNUM_ 130(5) 、TRANSFERNUM—130(6)及 TRANSFERNUM—130(7)均係由一個別地以信號 TRANSFERNUM_125(4)及 GNT—130(4)、GNT一 130(5)、 GNT_ 13 0(6)或GNT_ 13 0(7)做為輸入的邏輯及(AND)閘所 5 產生的。如圖所示，信號TRANSFERNUM_130(4)、 TRANSFERNUM一 130(5)、TRANSFERNUM—130(6)及 TRANSFERNUM_130⑺分別包含2個、3個、2個、及4 個脈衝，以供總數為11個脈衝或傳送之用，其係信號 TRANSFERNUM—125(4)所示之脈衝或傳送數量。 10 在上述第2圖及第3圖的範例中，邏輯閘非或(NOR) 和及(AND)係被使用，而且這些邏輯閘可設置於任何適合 的位置，包括設置於此適當的匯流排125上。然而，根據 本發明的技術，其餘邏輯閘或裝置也可用以替代此等非或 (NOR)閘與及（AND)閘以產生信號TRANSFER、 15 TRANSFERNUM、TRANSFERNUM—130 等。此邏輯閘的種 類的選擇係根據邏輯閘的輸入及/或輸出的邏輯位準。舉例 而言，假使只有一個備妥信號RDY係動作為低態，則藉由 利用一反轉器（INVERTER)，信號TRANSFER可從信號 RDY產生。然而，假使信號RDY是動作為高態，則信號 2〇 TRANSFERNUM可藉由Y與時鐘信號CLK等進行邏輯及 (AND)閘運算之信號RDY而直接地產生。 再者’上述說明係相關於本發明實施例。然而，本發 明並不受限於邏輯閘的位置、特定種類的匯流排、備妥信 號數量、備妥信號係判定為高態或低態、資料傳送係發生 25於時鐘信號之降緣或昇緣處、信號係判定為高態或低態等 因素。此外，任何智慧元件，例如，裝置、橋接器、處理 器，均可作為一起始器或標的。 11 200540633 基板管理控制器130(7) 在一實施例中，BMC130(7)為一服務處理器，其對於 系統100及/或其他可體現系統100之系統提供服務。典型 地，BMC 13〇⑺包括自身的處理元件、記憶體、韌體碼等。 5 BMC130(7)可促進一些功能，例如，遠端控制台存取、事 件與錯誤登入等功能。BMC130(7)可控制此系統硬體、促 進及控制可管理服務’其包括，例如，系統診斷、環境監 控、傳至外接系統管理員之資訊等。BMC 130(7)亦提供一 介面埠用於外接控制台存取，其可致能系統100之遠端帶 10外系統管理。因此，一系統管理員可執行系統管理而不需 利用此系統硬體及/或操作系統資源。系統管理之範例包括 重定向此控制台、觀測開機程序、查看及/或修改基本輸入 /輸出系統(BIOS)設定參數、對系統管理訊息回應、查看感 測器資料、警告、定限、FRU資料、BMC之組態、密碼、 15資料等。BMC130(7)也監控系統1〇〇的健全、如處理器ι10 等不同元件的溫度、體現系統1〇〇之電腦底盤等。BMC130⑺ 儲存可被處理器110利用之資訊，其包括，例如底盤溫度、 處理器溫度、非依電性隨機存取記憶體(NVRAM)上之資 訊、指示此底盤是否被開啟之機構等。 20 在一實施例中，BMC130(7)包括一用於測量風扇轉速 多快之風扇轉速計的輸入。假使此溫度開始變得太高時， 然後BMC130(7)將此資訊報告至處理器110,藉由此資訊 來獲得適當的行動，例如增加至風扇的電力使其旋轉速度 加快以藉此降低溫度。每一脈衝代表一風扇的旋轉，而且 25 BMC130⑺決定脈衝的數量或每分鐘之轉速(RPM)。然而， 在一實施例中，信號TRANSFERNUM係饋送至風扇轉速計 之輸入。因此，BMC130(7)，其取代測量風扇之每分鐘轉 12 200540633 速，測量匯流排例如匯流排125之每分鐘資料傳送數量。 實際上，BMC130(7)根據每分鐘資料傳送數量來計算此匯 流排運用率。 第1圖顯示BMC130(7)係位於一複數裝置匯流排上， 5 例如匯流排125(4)。BMC130(7)也可以位於單一裝置匯、、斧 排上，例如匯流排125(1)、125(2)、125(3)等，且此匯流排 種類係可作適當地變化，其包括，例如PCI匯流排、匯 流排等。BMC130(7)也可直接地耦合至橋接器ι2〇、或經由 硬體介面等耦合至橋接器120。本發明並不受限於 10 BMC130(7)係如何連接至一系統。 、 根據對於包括匯流排仲裁之各種用途的資料傳送數量而使 用匯流排運用技術 15In one embodiment, 'on a plurality of device buses, such as bus 25 125 (4)', which is coupled to more than one device, the transmission period represented by the signal TRANSFER and the data represented by the signal TRANSFERNUM The number of transfers applies to all devices on the bus, for example, device 130 (4), device 130 (5), device 130 (6), and device 130 (7) for the 9 200540633 bus 125 (4). However, it can generate a TRANSFERNUM signal for each of the plurality of device buses. Figure 3 shows how the individual TRANSFERNUM signals are generated and used to connect the busbars 125 (4) to 130 (4), 130 (5), 130 (6), and 130 (7). The signal. For the convenience of explanation, the devices 130 (4), 130 (5), 130 (6), and 130 (7) are connected with four "permission" signals GNT-130 (4), GNT_130 (5), GNT-130 ( 6) and GNT__130 (7) are individually associated. That is, when the signal GNT_130 (4) is judged, 10 data used by the device 130 (4) is transmitted; when the signal GNT_130 (5) is judged, the data used by the device 130 (5) is transmitted; and when the signal GNT_130 (6) When judged, the data used by device 130 (6) is transmitted, and so on. For convenience of explanation, the permission signal in FIG. 3 is determined to be high. The signal line 310 displays a signal TRANSFERNUM—125 (4) indicating the number of data transfers for the bus 125 (4). The signal TRANSFERNUM_125 (4) can be generated in the manner illustrated in Figure 2 and, as shown in Figure 3, includes 11 pulses for 4 devices 130 (4), 130 (5), 130 (6), and 130 (7) The total number of times is 11 transfers. Signal lines 320, 330, 340, and 350 indicate permission for these demonstrations. 20 Signals GNT-130 (4), GNT-130 (5), GNT-130 (6), and GNT_130 (7). Signal lines 360, 370, and 380. And 390 display the signals related to devices 130 (4), 130 (5), 130 (6), and 130 (7) TRANSFERNUM-130 (4), TRANSFERNUM-130 (5), 25 TRANSFERNUM-130 (6), and TRANSFERNUM_130 (7). In an example, each signal TRANSFERNUM_130 (4), 10 200540633 TRAN SF ERNUM_ 130 (5), TRANSFERNUM_130 (6), and TRANSFERNUM_130 (7) are all transmitted by a signal TRANSFERNUM_125 (4) And GNT-130 (4), GNT-130 (5), GNT_ 13 0 (6) or GNT_ 13 0 (7) as the input logic and (AND) gate 5. As shown in the figure, the signals TRANSFERNUM_130 (4), TRANSFERNUM-130 (5), TRANSFERNUM-130 (6), and TRANSFERNUM_130, respectively, include 2, 3, 2, and 4 pulses for a total of 11 pulses or For transmission, it is the number of pulses or transmission shown by the signal TRANSFERNUM-125 (4). 10 In the examples in Figures 2 and 3 above, the logic gates (NOR) and (AND) are used, and these logic gates can be placed in any suitable location, including the appropriate busbars. 125 on. However, according to the technology of the present invention, the remaining logic gates or devices can also be used to replace these NOR gates and AND gates to generate the signals TRANSFER, 15 TRANSFERNUM, TRANSFERNUM-130, etc. The type of logic gate is selected based on the logic level of the input and / or output of the logic gate. For example, if only one ready signal RDY is in the low state, the signal TRANSFER can be generated from the signal RDY by using an inverter (INVERTER). However, if the signal RDY is high, the signal 20 TRANSFERNUM can be directly generated by a signal RDY that performs a logical AND operation on the Y and the clock signal CLK. Furthermore, the above description is related to the embodiment of the present invention. However, the present invention is not limited to the position of the logic gate, the particular type of bus, the number of ready signals, whether the ready signal is determined to be high or low, and the data transmission to occur at the falling edge or rising of the clock signal. Factors such as fate and signal are determined to be high or low. In addition, any smart component, such as a device, bridge, or processor, can be used as an initiator or target. 11 200540633 Baseboard Management Controller 130 (7) In one embodiment, the BMC 130 (7) is a service processor that provides services to the system 100 and / or other systems that can embody the system 100. Typically, the BMC 130i includes its own processing elements, memory, and firmware code. 5 BMC130 (7) facilitates functions such as remote console access, events and error login. BMC130 (7) can control the system hardware, promote and control manageable services ’, which includes, for example, system diagnostics, environmental monitoring, and information to external system administrators. BMC 130 (7) also provides an interface port for external console access, which can enable system management on the remote side of system 100. Therefore, a system administrator can perform system management without using the system hardware and / or operating system resources. Examples of system management include redirecting the console, observing the boot process, viewing and / or modifying basic input / output system (BIOS) settings parameters, responding to system management messages, viewing sensor data, warnings, limits, and FRU data , BMC configuration, password, 15 data, etc. The BMC130 (7) also monitors the health of the system 100, the temperature of different components such as the processor ι10, and the computer chassis reflecting the system 100. The BMC130⑺ stores information that can be used by the processor 110, including, for example, chassis temperature, processor temperature, non-electrical random access memory (NVRAM) information, a mechanism indicating whether the chassis is turned on, and the like. 20 In one embodiment, the BMC130 (7) includes a fan tachometer input for measuring how fast the fan speed is. If this temperature starts to become too high, then the BMC130 (7) reports this information to the processor 110, and uses this information to obtain appropriate actions, such as increasing the power to the fan to make it rotate faster to reduce the temperature . Each pulse represents the rotation of a fan, and the 25 BMC130⑺ determines the number of pulses or revolutions per minute (RPM). However, in one embodiment, the signal TRANSFERNUM is fed to the input of the fan tachometer. Therefore, BMC130 (7), instead of measuring the fan's speed per minute 12 200540633, measures the number of data transfers per minute of a bus, such as bus 125. In fact, BMC130 (7) calculates this bus utilization rate based on the number of data transfers per minute. Figure 1 shows that the BMC130 (7) is located on a bus of multiple devices, such as bus 125 (4). BMC130 (7) can also be located on a single device bus, such as bus 125 (1), 125 (2), 125 (3), etc., and the type of this bus can be changed as appropriate, including: For example PCI bus, bus and so on. The BMC130 (7) may also be directly coupled to the bridge ι20 or to the bridge 120 via a hardware interface or the like. The invention is not limited to how the BMC130 (7) is connected to a system. Use of bus utilization technology based on the number of data transfers for various purposes including bus arbitration 15
20 在各種實施例中，藉由匯流排自身或與其他路徑連 接，資料傳送數量係使用於仲裁匯流排。在一實施例中， 仲裁器1210具有關於在一期間内之資料傳送數量及/或每 單位時間内之資料傳送數量之資訊，此仲裁器121〇可作= 適當的決定，此等決定包括何者及/或何時一裝置可取得一 匯流排、此裝置可取得此匯流❹久科。根據執行結=， 仲裁器ΠΗ)可包括用於仲裁附屬匯流排之—個或各個層 間，例如當附屬匯流排（未顯示於圖中）向主匯流排(如^ 排125(4))明求存取。本發明並不受限於仲裁器⑵〇之架 構。仲裁H 1210之決定可與此所欲目的做—連結，例如 =匯，間的資料流量、准許裝置在匯流排上取得足 ^傳送資料、對許可匯流排提供優域等。例如，仲裁 益1幻〇可決定在特糾段所有裝置 帶寬或特定比例的帶寬。在其他時間内，部分裝= 13 25 200540633 排上可具有較高的優先權以及更多的帶寬比率，比如第一 裝置VGA130(1)有50%的帶寬，第二裝置纖維通道130(2) 具有30%的帶寬，第三裝置SCSI130(3)具有20%的帶寬 等。仲裁器1210係由適當的邏輯電路及/或韌體/軟體所架 5構的，因此其可動態地決定或，，直接，，將此匯流排配置到適 當的裝置。一個智慧型處理元件比如處理器11〇、B]y[C130(7) 等，其經由一個或硬體、軟體及韌體的組合可驅動仲裁器 1210或與仲裁器121〇 —同作用以執行所需求的匯流排仲 裁目的。一般而言，仲裁器12ι〇使用，，請求，，及，，許可，，之機 10制，其中這些裝置希冀要求匯流排提供一請求信號REq至 仲裁器1210，當備妥去許可此匯流排至一裝置時，提供一 許可信號GNT至該裝置。 15 20 牡一规點T，纤可至每一匯流排上的帶寬可被控制， 例如用以解決負載的不平衡/瓶糊題，以允許部分裝置擁 有部分的驗存取匯流排的預定帶寬，而非使裝置取得最 多的時間以及避免其他裝置取得匯流排等。在第丨圖中， =裁器12H)是位於橋接器丨㈣，但是仲裁器i2i〇也可 存在於其他任何適當的位置，包括設在橋接器12〇之外。 ，流排仲裁的範例達成使仲裁器12ig可用來結合本發 循m術’包括:所有權、固定的優先權、最後許可、 2法/小最近要料。“，本發㈣衫 方法；其他方法也可同樣運用。 、一 明資料傳送數量係如何用以’以下將說 持有之龍傳賴量與-裝置°_所有^則，其中每次 擁/匯流排的次數將成為 决疋疋否許可一匯流排到一裝豎。 $便說明之故’仲裁器⑽衫，平均而言 應该分配到相同數量的傳送資料之帶寬，以及二個= 14 25 200540633 15 VGA130(1)和SCSI130(3)在一匯流排仲裁中被考慮。然而， 每一次VGA裝置130(1)被許可或，，擁有，，匯流排時，其傳送 1位元組的資料，同時，每次SCSI裝置130(3)被許可匯流 排時，其傳送100位元組的資料。仲裁器121〇，根據每單 5位時間的資料傳送數量（也就是帶寬），在允許SCSI裝置 13〇(3)擁有匯流排1次之前，會先允許VGA裝置130(1)擁 有匯流排1〇〇次。在實行中，對於這兩個裝置13〇(1)和13〇(3) 而a，匯流排運用率係幾乎相同或各5〇%，因為當裝 置130(1)擁有匯流排1〇〇次時，其會傳送ι〇〇位元組的資 10料，然而當SCSI裝置130(3)擁有匯流排丨次時，其也傳送 1〇〇位70組的資料。在這範例中，依據所欲的結果，仲裁器 mo可，據每單位時間之資料傳送數量來調整所有權數。 牛丨】而σ饭使仲裁器121〇決定VGA裝置ΐ3〇(ι)應且有 ==叙m SCSI裝置13_具有這次的匯 二排Γ則仲裁器1210在允許SCSI裝置13G(3)擁有匯 :在^之前，會先允許裝置130(1)去擁有此匯流排 確-、在笨此: 任一地，假使仲裁器121〇 20 二 =:r，VGA裝置13〇⑴根據平均赚軍位 則在這段期^^於每次持有時傳送10位元組的資料， 1卵)之前^裁益1210在將匯流排許可至SCSI裝置 等。就如所見:，允帶=裝f "❹次 的結果而實現M U有讀結合可根據所欲 以直接作出1裁151210可根據資料傳送數量而程式化 進一步二’而且本發明並不受限於特定的結合。更 明之用，兩個[跑例利用兩個裝置130⑴及130(3)僅係供說 以上的裝置也可被一結合上述技術之匯流排 15 25 200540633 仲裁設計的仲裁器121〇所考量。熟於此技者可瞭解到在這 些裝置間不需要將每次持有時之資料傳送數量視為相同的 持有數，SCSI裝置130(3)可比VGA裝置130(1)擁有此匯 流排更長的時間而且因此傳送比VGA裝置130(1)還多的資 5 料。舉例而言，對於相同的3個持有數而言，當SCSI裝置 13〇(3)傳送3〇0位元組之資料時，VGA裝置130(1)可傳送3 位元組的資料。 根據本發明的技術，就資料傳送數量方面而言，匯流 排運用技術也可提供至一智慧型處理元件，例如處理器 10 U〇、BMC130(7)、而作為適當的使用。舉例而言， BMC130(7)，經由其韌體，可直接地程式或配置仲裁器121〇 如上述5兒明以作出合適的決定。任一地，除仲裁器121 〇外， 處理器110、BMC130(7)、橋接器120在統計上可利用每一 匯流排上每單位時間之資料傳送數量以負載平衡此匯流 15排。同樣地，一系統工程師可利用匯流排運用技術資訊來 重新組配此系統，包括系統100,以重定向第一匯流排至第 二匯流排擁擠的運載量等。當實行及控制仲裁器121〇時， 在仲裁器1210與BMC130(7)或產生每單位時間之資料傳送 計量的元件之間可提供一硬體介面。任一地，運行於處理 20器no及7或BMCl3〇(7)之韌體上的軟體可產生每單位時間 之資料傳送數量，以及提供信號以控制仲裁器1210等'。曰 根據代表傳送時段之信號的工作週期之匯流排運用技術 在各種實施例中，表示此匯流排上之傳送期間的傳送 f 2 TRANSFER)U 作週期可用來 決定此種匯流排之匯流排運用率，因為這工作週期係 相等於此匯流排主動地傳送資料時的時間百分 i'一 刀。在一實 20054063320 In various embodiments, the data transfer amount is used to arbitrate the bus by the bus itself or by connecting with other paths. In an embodiment, the arbiter 1210 has information on the number of data transfers in a period and / or the number of data transfers per unit time. This arbiter 121 may make an appropriate decision, and which of these decisions to include And / or when a device can get a bus, this device can get this bus. According to the execution result =, the arbiter (iiΗ) may include one or each layer used to arbitrate the auxiliary bus, for example, when the auxiliary bus (not shown in the figure) is declared to the main bus (such as ^ Row 125 (4)) For access. The invention is not limited to the architecture of the arbiter ⑵〇. The decision of arbitration H 1210 can be linked to this desired purpose, such as = data flow between sinks, permitting the device to obtain sufficient data on the bus ^ to transmit data, and providing a superior domain for the permitted bus. For example, arbitration can determine the bandwidth of all devices or a specific percentage of bandwidth in the special correction section. At other times, partial installation = 13 25 200540633 may have higher priority and more bandwidth ratio, such as the first device VGA130 (1) has 50% bandwidth, the second device fiber channel 130 (2) It has a bandwidth of 30%, and the third device SCSI130 (3) has a bandwidth of 20%. The arbiter 1210 is constructed by appropriate logic circuits and / or firmware / software, so it can dynamically determine or, directly, configure this bus to an appropriate device. An intelligent processing element, such as processor 110, B] y [C130 (7), etc., can drive arbiter 1210 or perform the same function as arbiter 1210 through one or a combination of hardware, software, and firmware. Required bus arbitration purpose. Generally speaking, the arbiter 12m uses the 10 mechanism to request, and, and permit, where these devices hope to request a bus to provide a request signal REq to the arbiter 1210, when ready to permit the bus When reaching a device, a permission signal GNT is provided to the device. 15 20 According to the standard point T, the bandwidth from the fiber to each bus can be controlled, for example, to solve the load imbalance / bottle paste problem, to allow some devices to have part of the predetermined bandwidth of the access bus Instead of getting the most out of your device and preventing other devices from getting the bus. In the figure, the = cutter 12H) is located in the bridge, but the arbiter i2i〇 may also exist in any other suitable location, including outside the bridge 12o. The example of streamlining arbitration is achieved so that the arbiter 12ig can be used in conjunction with this process. It includes: ownership, fixed priority, final license, 2 methods / smallest recent requirements. ", This hair shirt method; other methods can also be used in the same way. How to use the number of data transfers will be used to 'the following will say the amount of dragon transmission and -device ° _ all ^ rules, where each time / The number of buses will become a decision whether to allow a bus to be installed. $ It means that the 'arbiter shirt' should, on average, be allocated to the same amount of bandwidth for transmitting data, and two = 14 25 200540633 15 VGA130 (1) and SCSI130 (3) are considered in a bus arbitration. However, each time a VGA device 130 (1) is licensed or, when it owns, the bus transmits 1 byte At the same time, each time the SCSI device 130 (3) is allowed to bus, it transmits 100 bytes of data. The arbiter 1210, based on the number of data transfers (i.e., bandwidth) per 5-bit time, allows Before the SCSI device 13〇 (3) has the bus 1 time, the VGA device 130 (1) is allowed to have the bus 100 times. In practice, for these two devices 13〇 (1) and 13〇 (3 ) And a, the bus utilization rate is almost the same or 50% each, because when device 130 (1) has bus 1 At the time, it will send 10 bytes of data, but when the SCSI device 130 (3) has the bus, it also sends 100 bits of 70 data. In this example, According to the desired result, the arbiter mo can adjust the number of ownerships according to the amount of data transmitted per unit of time. [牛 丨] and σfan makes the arbiter 121〇 decide that the VGA device ΐ30 (ι) should have and == Syria m SCSI device 13_ With the second row of this time, the arbiter 1210 allows the SCSI device 13G (3) to own the sink: before ^, the device 130 (1) will be allowed to own this bus. : Either way, if the arbiter is 121〇20 == r, the VGA device is 13〇⑴ According to the average military position earned during this period ^^ Each time you hold 10 bytes of data, 1 egg) Prior to ^ Cruise 1210, the bus was licensed to the SCSI device, etc. As you can see: Allowed band = installed f " the result of the times to achieve MU combined reading can be made directly according to what you want 151210 can be based on information Send the number and stylize further two 'and the present invention is not limited to a specific combination. For the sake of clarity, two [run examples using two devices 130⑴ and 130 (3) are only for the purpose of saying that the above devices can also be considered by an arbiter 121 of the arbitration design that combines the above technologies. Regarding the number of data transfers per hold as the same number of holds, the SCSI device 130 (3) can own this bus for a longer time than the VGA device 130 (1) and therefore transfer more time than the VGA device 130 (1) 5 more materials. For example, for the same three holding numbers, when the SCSI device 13 (3) transmits 300 bytes of data, the VGA device 130 (1) can transmit 3 bytes of data. According to the technology of the present invention, in terms of the amount of data transfer, the bus application technology can also be provided to an intelligent processing element, such as the processor 10 U0, BMC130 (7), for proper use. For example, the BMC130 (7), through its firmware, can program or configure the arbiter 121 directly as described above to make a suitable decision. Either way, in addition to the arbiter 121, the processor 110, the BMC 130 (7), and the bridge 120 can statistically use the data transmission amount per unit time on each bus to load balance this bus to 15 rows. Similarly, a system engineer can use the bus to apply technical information to reconfigure the system, including system 100, to redirect the first bus to the crowded load of the second bus, etc. When the arbiter 1210 is implemented and controlled, a hardware interface may be provided between the arbiter 1210 and the BMC 130 (7) or the component that generates the data transfer meter per unit time. Either way, the software running on the firmware processing 20 and 7 or BMC1 30 (7) can generate the number of data transfers per unit time, and provide signals to control the arbiter 1210, etc. '. The bus utilization technology based on the duty cycle of the signal representing the transmission period. In various embodiments, the transmission period of the transmission period on this bus is f 2 TRANSFER. The operating cycle can be used to determine the bus utilization rate of this bus. Because this duty cycle is equivalent to the time i 'when the bus is actively transmitting data. In a real 200540633
10運用率。如同此根據資料傳送數量之匯流排運用技術、根 據傳送信號之工作周期之匯流排運用技術可被各種供類似 於上文所述之各種目的用之處理元件使用。 第4圖顯示根據一實施例之可用來產生傳送信號2DC 成分的RC網路400。 關中，此傳送信號係經由—提供與卫作週期成比例之％ 電壓成份的RC網路而被滤出。而後此Dc電壓係饋授至 BMC130(7)之-ADC(類比至數位轉換器）輸入，以致於 BMCH30⑺，經由其動體，可直接地讀取此輸人電壓的測 量值。麗請⑺接著藉由此傳送信號之完整振幅來分割 此電壓測量他提供—时等於此㈣之工作周期之盘 墓上所述成乎相等於此匯流排傳送資料時的時間比 率。此外，在不同實_巾，與各觀流財關之各種傳 送資料的玉作周期可彼此比較以比較這些匯流排的匯流排 15 第5圖顯示根據一實施例之說明根據個別地表示在匯 流排125⑴及⑵⑺上之傳送期間的信號 TRANSFER—125⑴及TRANSFER—125(2)之工作週期之匯 流排運用率之圖。為方便說明之故，信號TRANSFER_125(1) 及TRANSFER—125(2)之振幅均為〇至5V。信號線510顯 20示TRANSFER—125(1)具有50%的工作週期之信號 TRANSFER—125(1)。"f吕號線520顯示經由饋授至rc網路 400所產生之信號TRANSFER—125(1)的DC成分。因為此 信號丁RANSFERJ25(1)之工作週期為50%，此DC成分位 於信號TRANSFER一 125(1)振幅的50%處，其為2.5V。信號 25 線530顯示具有40%的工作週期的匯流排125(2)之信號 TRANSFER_125(2)。信號線540顯示經由饋授至RC網路 400所產生之信號TRANSFERJ25(2)的DC成分。因為此 17 200540633 h號TRANSFER—125(2)之工作週期為4〇%，此Dc成分位 於 TRANSFER—125(2)振幅的 4〇0/。處，其為 2 〇v。 電腦系統概要 5 帛6圖係—顯示―應用本發明實施例之電腦系統600 的方塊圖。舉例而言，電腦系統6〇〇可用以操作為系統 1〇〇,包括系統1〇〇、執行仲裁器121〇、根據上述之技術執 行任務等。在一實施例中，電腦系統_包括—中央處理 單t〇(CPU)604、隨機存取記憶體(RAM)6〇8、唯讀記憶體 H) (ROM)612、-健存裝置616、卩及一通信介面62〇，所有 裝置都被連接至一匯流排624。 CPU6〇4可控制邏輯、處理資訊、以及調節電腦系統 600内之活動。在一實施例巾，cpu6〇4可執行餘存於 RAM608及ROM6125之指令，藉由，例如調節從輸入裝置 15 628至顯示器裝置632之資料動向。cpu6〇4可包括一個或 多個處理器。10 utilization rate. As such, the bus utilization technology based on the amount of data transmitted and the bus utilization technology based on the duty cycle of the transmitted signal can be used by various processing elements for various purposes similar to those described above. FIG. 4 shows an RC network 400 that can be used to generate a 2DC component of a transmission signal according to an embodiment. In Guanzhong, this transmission signal is filtered through an RC network that provides a% voltage component proportional to the satellite cycle. This Dc voltage is then fed to the -ADC (analog-to-digital converter) input of the BMC130 (7), so that the BMCH30⑺ can directly read the measured value of this input voltage through its moving body. Li please then divide this voltage measurement by the full amplitude of the transmitted signal to measure the voltage he provided—the time equal to the duty cycle of the disk. The tomb described on the grave is almost equal to the time ratio when the bus is transmitting data. In addition, in different implementations, the jade cycles of various transmission data of various Guanliuguanguan can be compared with each other to compare the busbars of these busbars. Fig. 5 shows a description according to an embodiment based on the individual representation of the busbars. A graph of bus utilization ratios for the duty cycles of the signals TRANSFER-125TRA and TRANSFER-125 (2) during the transmission period on 125⑴ and ⑵⑺. For the convenience of explanation, the amplitudes of the signals TRANSFER_125 (1) and TRANSFER-125 (2) are 0 to 5V. The signal line 510 displays TRANSFER-125 (1) with a signal of 50% duty cycle, TRANSFER-125 (1). " f Lu line 520 shows the DC component of the signal TRANSFER-125 (1) generated by feeding to the rc network 400. Because the duty cycle of this signal RANSFERJ25 (1) is 50%, this DC component is located at 50% of the amplitude of the signal TRANSFER-125 (1), which is 2.5V. The signal 25 line 530 shows the signal TRANSFER_125 (2) of the bus 125 (2) with a duty cycle of 40%. The signal line 540 shows the DC component of the signal TRANSFERJ25 (2) generated by feeding to the RC network 400. Because the duty cycle of TRANSFER-125 (2) of 17 200540633 h is 40%, this Dc component is located at 400 / of the amplitude of TRANSFER-125 (2). It is 20 volts. Computer System Overview 5 帛 6 is a block diagram showing a computer system 600 to which an embodiment of the present invention is applied. For example, the computer system 600 can be used to operate as the system 100, including the system 100, the execution arbiter 121, and the tasks performed according to the above-mentioned technology. In one embodiment, the computer system includes a central processing unit (CPU) 604, a random access memory (RAM) 608, a read-only memory (H) (ROM) 612, a health storage device 616, With a communication interface 62, all devices are connected to a bus 624. The CPU 604 can control logic, process information, and regulate activities within the computer system 600. In one embodiment, the CPU 604 can execute the instructions remaining in the RAM 608 and the ROM 6125, for example, by adjusting the data movement from the input device 15 628 to the display device 632. The CPU 604 may include one or more processors.
RAM608’其通常被視為主要記龍，可暫時地儲存資 =及指令以讓CPU6G4執行。位於RAM内之資訊可從 入裝置628獲得或是由CPU6〇4產生，以糊皮cpu6〇4 20執行的指令所要求之運算程序的一部分。 11嶋12儲存-旦寫入至R〇M晶片即為僅可讀取且益 ，修改或移除之資訊與指令。在—實施例中，職612儲 子用於電齡統6 G G之組構及初始操作之命令。 =存裝置616’例如軟碟片、磁碟驅動機、或磁帶驅動 機，長久地儲存用於電腦系統6〇〇之資訊。 通信介面620 置介接。通信介面 可致能電腦系、統_以與其他電腦或裝 62〇可以疋，例如一數據機、整體服務 18 25 200540633 數位網路(ISDN)卡、一區域網路(LAN)埠等。熟於此技者將 瞭解，數據機或ISDN卡係經由電話線提供資料通信，然而 一 LAN埠則是經由一 LAN提供資料通信。通信介面620 也可允許一無線通信。 • 5 匯流排624可以是任何用於通信供電腦系統6〇〇使用 之資訊的通信機制。在第6圖的範例中，匯流排624是一 媒體其用於在CPU604、RAM608、ROM612、儲存裝置616、 通信介面680等之間傳送資料。 電腦糸統600係典型地搞合至一輸入裝置628、一顯示 參 10器裝置632、以及一游標控制636。輸入裝置628，例如一 包括字母與數字以及其他按鍵的鍵盤，傳送資訊與命令至 CPU604。顯示器裝置632，例如一陰極射線管(crt)，顯示 資訊給電腦系統600的使用者。游標控制636，例如一滑 鼠、一執跡球、或游標方向鍵，傳送方位資訊及命令至 15 CPU604以及控制在顯示器裝置632上之游標移動。 電腦系統600可經由一或多個網路與其他電腦或裝置 通信。例如，電腦系統600利用通信介面620，經由一網路 640與另一台連接一印表機648之電腦644通信，或者是經 ® 由全球資訊網652與一伺服器656通信。此全球資訊網652 20 通常是被視為”網際網路(Internet)”。任一地，電腦系統6〇q 可經由網路640存取此網際網路652。 電腦系統600可用來實施上述技術。在各種實施例中， CPU604藉由執行帶至RAM608的指令以實行此技術之各 個步驟。在另一實施例中，硬佈線電路可用來代替或結合 25 軟體指令以實施這些已說明之技術。因此，本發明的各個 實施例並不受限於任何一個軟體、動體、硬體、或電路及 其組合。 19 200540633 ^被聊_執行的指令可被—或多個電腦可讀取 =儲存及/或完成，其可有_任㈣體，而電腦可從立 中言買取資訊。電腦可讀取媒體可从，例如軟式磁碑片: 硬碟、ZIP磁·、磁帶、或任何其他磁性媒體、咖麵、 =讀、娜讓^㈣鳩、餘何其他光學媒體、 t、打孔卡片、或任何其他具有打孔式樣之實體媒體、 RAM、RQM、EPRQM、餘何其他記㈣W或卡E。 電腦可讀取媒體也可以是同軸親、鋼線、光纖、聲波或 10 15 20 電磁波、電容或電感麵合等。如同一範例，此等可被咖綱 執行之指令可以是-或多個軟體程式之類型而且是初始地 被儲存於—經由匯流排624而與電腦系統_介接之 CD-ROM。電腦系統_載入RAM_之指令，執行部份 指令，以及經由通信介面62〇、數據機、以及連至網路之電 話線也就是網路640、網際網路652等傳送部份指令。一經 由=路财純資料之遠端電職行此已接收指令以及傳 送資料至電腦系統600而儲存在儲存裝置616。 在上述說明中，本發明已經藉著參考其詳細的實施例 加以描述。然而，顯而易見的，在不背離本發明的範疇與 精神下，各種修飾與改變係可達成的。因此，說明書與圖 式係被作為說明目的而非用以限制。 【圖式簡單說明】 第1圖表示一根據本發明可執行的實施例之系統； 第2圖表示根據一實施例之時序圖，作為根據資料傳 送數提供匯流排運用之圖解； 第3圖表示用以圖示信號產生的時序圖，此信號產生 代表在多個裝置匯流排上對於裝置的資料傳送數目； 20 25 200540633 第4圖表示一根據一實施例之RC網路； 第5圖表示用於圖示根據傳送信號工作週期之匯流排 運用的圖式；以及 第6圖表示一範例電腦系統之圖式。 【主要元件符號說明】RAM608 'is usually regarded as the main memory, and can temporarily store data and instructions for CPU6G4 to execute. The information located in the RAM can be obtained from the input device 628 or generated by the CPU 604 and used as a part of the operation program required by the cpu 602 20 instructions. 11 嶋 12 Storage-Once written to ROM chip, it is only readable, beneficial, modified or removed information and instructions. In the embodiment, the 612 bank is used for the order and initial operation of the electrical age system 6 G G. The storage device 616 ', such as a floppy disk, a magnetic disk drive, or a magnetic tape drive, permanently stores information for a computer system 600. The communication interface 620 is configured to interface. The communication interface can enable the computer system, system, and other computers or can be installed, such as a modem, overall services 18 25 200540633 digital network (ISDN) card, a local area network (LAN) port, and so on. Those skilled in the art will understand that a modem or ISDN card provides data communication via a telephone line, whereas a LAN port provides data communication via a LAN. The communication interface 620 may also allow a wireless communication. • The 5 bus 624 may be any communication mechanism for communicating information for use by the computer system 600. In the example of FIG. 6, the bus 624 is a medium for transferring data between the CPU 604, the RAM 608, the ROM 612, the storage device 616, the communication interface 680, and the like. The computer system 600 is typically coupled to an input device 628, a display device 632, and a cursor control 636. The input device 628, such as a keyboard including letters and numbers and other keys, transmits information and commands to the CPU 604. A display device 632, such as a cathode ray tube (crt), displays information to a user of the computer system 600. The cursor control 636, such as a mouse, a trackball, or a cursor direction key, transmits position information and commands to the CPU 604 and controls the movement of the cursor on the display device 632. Computer system 600 may communicate with other computers or devices via one or more networks. For example, the computer system 600 uses a communication interface 620 to communicate with another computer 644 connected to a printer 648 via a network 640, or communicates with a server 656 via the World Wide Web 652. This World Wide Web 652 20 is often considered the "Internet". Either way, computer system 60q can access this Internet 652 via network 640. The computer system 600 can be used to implement the techniques described above. In various embodiments, the CPU 604 executes the steps of this technique by executing instructions brought to the RAM 608. In another embodiment, hard-wired circuits can be used in place of or in combination with 25 software instructions to implement these illustrated techniques. Therefore, the embodiments of the present invention are not limited to any one software, moving body, hardware, or circuit, and a combination thereof. 19 200540633 ^ The command executed by the chat can be read-or can be read by multiple computers = stored and / or completed, it can have any body, and the computer can buy information from a neutral language. Computer-readable media can be obtained from, for example, soft magnetic tablets: hard disks, ZIP magnetic tapes, magnetic tapes, or any other magnetic media, coffee noodles, = reads, Narang ^ ㈣Dove, Yu He other optical media, t, playing Hole card, or any other physical media with a hole pattern, RAM, RQM, EPRQM, any other note W or card E. Computer-readable media can also be coaxial, steel wire, optical fiber, sound waves or 10 15 20 electromagnetic waves, capacitors or inductors. As in the same example, these instructions that can be executed by the coffee maker can be-or multiple software programs-and are initially stored in-a CD-ROM that interfaces with the computer system via a bus 624. The computer system _loads RAM_ instructions, executes some instructions, and transmits some instructions through the communication interface 62, the modem, and the telephone line connected to the network, that is, the network 640, the Internet 652, and so on. Once received by the remote telecommunication bank with pure data, it has received the instructions and transmitted the data to the computer system 600 and stored in the storage device 616. In the above description, the present invention has been described by referring to its detailed embodiments. However, it is obvious that various modifications and changes can be achieved without departing from the scope and spirit of the present invention. Therefore, the description and drawings are used for illustrative purposes and not for limitation. [Brief description of the drawings] FIG. 1 shows a system according to an embodiment executable by the present invention; FIG. 2 shows a timing chart according to an embodiment as a diagram for providing a bus application according to the number of data transfers; FIG. 3 shows It is used to illustrate the timing diagram of signal generation. This signal generation represents the number of data transfers to devices on multiple device buses. 20 25 200540633 Figure 4 shows an RC network according to an embodiment; Figure 5 shows the use of In the figure, a diagram of a bus according to a duty cycle of a transmission signal is used; and FIG. 6 shows a diagram of an example computer system. [Description of main component symbols]
100…系統 360、370、380、390、510、 110···處理器 520、530、540·.·信號 115···匯流排 400...RC 網路 120…橋接器 600…電腦系統 1210…仲裁器 604…中央處理器 125(1)…匯流排 608…隨機存取記憶體 125(2)…匯流排 612...唯讀記憶體 125(3)…匯流排 616…儲存裝置 125(4)···匯流排 620...通信介面 130···額外裝置 624...匯流排 130(1)"_VGA 裝置 628...輸入裝置 130(2)…光纖通道裝置 632…顯示器裝置 130(3)…SCSI 裝置 636…游標控制器 130(4)…SCSI 裝置 640...網路 130(5)…纖維通道裝置 644…主機電腦 130(6)…通用序列匯流排 648··.印表機 130(7)...BMC 652...網際網路 210 ' 22卜 230 ' 240 ' 250、 310、320、330、340、305、 656...網路伺服器 21100 ... system 360, 370, 380, 390, 510, 110 ... processor 520, 530, 540 ... signal 115 ... bus 400 ... RC network 120 ... bridge 600 ... computer system 1210 ... arbiter 604 ... CPU 125 (1) ... bus 608 ... random access memory 125 (2) ... bus 612 ... read-only memory 125 (3) ... bus 616 ... storage device 125 ( 4) ... bus 620 ... communication interface 130 ... additional device 624 ... bus 130 (1) " _VGA device 628 ... input device 130 (2) ... Fibre Channel device 632 ... display Device 130 (3) ... SCSI device 636 ... Cursor controller 130 (4) ... SCSI device 640 ... Network 130 (5) ... Fibre channel device 644 ... Host computer 130 (6) ... Universal serial bus 648 ... Printer 130 (7) ... BMC 652 ... Internet 210 '22, 230' 240 '250, 310, 320, 330, 340, 305, 656 ... Web server 21