TW200540607A - Error check circuit with variable transmission data width - Google Patents

Abstract

The present invention provides an error check circuit with variable transmission data width for receiving a series of input data and writing the input data onto a recording medium with a first data width or a second data width. The circuit comprises a first check sum generator and a second check sum generator coupled together, wherein the first check sum generator is used to receive the input data and generate the first set of check sum through operation for writing onto the recording medium, and the second check sum generator is used to receive the input data and generate the second set of check sum through operation for writing onto the recording medium, the second data width being larger than the first data width. Thus, when the data width of the recording medium is equal to the first data width, the first check sum generator will receive all the input data. When the data width of the recording medium is equal to the second data width, the first check sum generator and the second check sum generator will receive half of the input data, respectively.

Description

V. Description of the invention (1) Two-way [Technical field to which the invention belongs J The present invention is a kind of having, changing, and particularly relates to a kind of circuit for producing inspection. [Previous technology] Ensuring the integrity of stored data H. Second key part. Due to the transmission of data and the environmental factors in the design process of the recording media on May 5th, the content of the data was generated. It is a long-term cause of the transmission media or external data content and the data transmitting end is not j, causing the data receiving end to receive Verification i is free of '::::' deviation, which is usually wrong for transmission data -e〇k codes), Par1 ^ ... But the parity check:; ::: = has all the same functions in the same, so another technique that uses the wrong repair, ',., Method to provide repair code) ’not only helped ::. mCti〇n incorrect data, making E Finance widely applicable / acceptable & more accurate / used— = complex error The accuracy of memory data. . The use of the hidden body is to be kept in mind: ^ The media width is "Π" due to the different types, specifications or application occasions. For the 8051 microprocessor, its 8-bit data is read and written with 8-bit units. If 8-bit access is used to control the 16-bit data width of the fast M memory, the error correction code will be 200540607 because the width of the data transmitted by the 8051 processor and the flash memory is different. 2. Description of the invention (2) 丨 ;; Successfully write to flash memory to provide correct information errors and corrections 1 In the process of generating the above error correction code, the correctness of the recording medium is: The same research: the error correction code was written in the proposal of a kind of "Yan Yerengu" ~ Yan Jiuya's application of scientific theory, the final I kind of Han Chong is reasonable and effective to improve the above-mentioned lack of the invention. [Content of the invention] | Material width The value of j 2 ^ 1 is that a variable transmission resource can be provided. The width of the recording medium is equal to the material width: ϊίϋ: 'ί Invention provides-a kind of variable transmission information with a first resource; t , Two to receive a series of input data and input body, wrong 4 杳; Entered into a recording medium, use Γ to enclose. A checksum produces a record of input data, and generates a first set of checksums dt and a second check after operation. And the generation of 11, is related to the first-check Ϊ two groups: check ^ receive ... and receive the input data, and after operation to generate the first data wide household `` 2 3 recorded media 'where the second data width is greater than the first- ί ^ Ϊ Although the data width of the recording medium is equal to the first data width, the input data of the I media receives the input data, and when the recording is semi-parallel: J degrees =: f material width, the input data is divided into -I first Received by the checksum generator and the second checksum generator. • To achieve the above-mentioned object, the present invention provides a memory system, including page 6, 200540607, description of the invention (3) '• • a first memory' has a篦 ^ 'has a second data width; a first —: material width f — pass through the output data of the -memory, and pass through' :: ㊁ ::: two 2 to write into the second memory; a second school The tester and the tester are coupled to each other with a generator to receive the first generator, which is related to A checksum operation generates a second set of checksums to write the output data of the memory, and through the access controller, it controls the first-two memory; and a memory transfer wheel, and Yu 帛 —t material width, etc .; the data between ^ and the first-memory < Shi · t, the first capital oblique 宦 Tang Ri 矣, he made neodymium five second checksum generator all Receiving the first _note ^ ^ lean material width ...., the width is greater than the -data width, then ^ data, and when the second data is divided into half and one: U the output data of the first memory is received. In order to achieve the above-mentioned purpose, the generator and the second checksum generator generate a checksum to write and write for a kind of error checking circuit operation. Receive a string of input data; subdivide the packet. The recorded medium includes the following steps;-the second part of the data; receiving the second data as-the-part of the data and the generator; receiving the second part of the data m by a first-checksum generator and The second checksum yield data is generated and written into the first set of checksums by the first check generator and the second set of checksums. ,. The results are different in this recording medium ~ In order to make your review committee go further, please refer to the following steps to understand the features and techniques of the present invention. The drawings are provided for reference and explanation only. "'Not used to limit the present invention 200540607 V. Description of the invention (4) system. [Embodiment] The present invention is an error checking circuit with a variable transmission data width, which can generate an error correction code of a suitable data width according to the difference in the data width of the recording medium, and write the error correction in accordance with the data width of the recording medium. Code on the recording medium. Please refer to the first figure, which is a schematic diagram of the memory read-write control of the present invention. Recording media refers to flash memory 17 with 16-bit data width. The source of written data is static random access memory (SRAM) 11 with 8-bit data width. 11. Memory access controller 1 9 is controlled by the host (illustration omitted) to perform data transfer between static random access memory 11 and flash memory 17, and an error check circuit 15 is provided for checking the data stored in the memory Whether it is consistent, and the direct memory access controller 19 can provide a large amount of data transfer. In this embodiment, when writing data to the flash memory 17, the error checking circuit 15 receives the static random access memory 11 with a data width of 8 bits at a time by using 2 5 6 bytes as a unit. The output data is processed by the internal algorithm of the error check circuit 15 to generate 3 sets of 8-bit checksums (check §um), and then the checksum is used with the appropriate data width (8 or 16 bits Yuan) is written in the flash memory 17 for the next time the data in the flash memory 17 is read and used as data debugging and correction. And since the flash memory 17 is a 16-bit data width, but the error check circuit 15 receives data input with an 8-bit data width, so how does the error check circuit 15 convert the input to

Page 8 200540607 V. Description of the invention (5) The 8-bit data visibility is converted to output $ ^ 6-bit data width, which is the weight of the current month. "The account will be the internal structure of the right and wrong check circuit below. 5 The method of calculation and operation I will be explained. Referring to the first figure, the drawing shows the t composition of the error check circuit of the present invention. The error check circuit 15 mainly includes a comparison table 15, a checksum generator 153, a The second checksum generator 155, one correction = two '1 5? One juice number table 1 5 9. The static random access memory 1 1 output 丨 | greedy, it is input one by one in 8-bit mode Go to the control 151 and order two to find the corresponding data of 2 5 6 byte data. 丨 In addition, there are 8 you ^ owed to the inspection agency and generated / 1 5 3 and the second checksum generator 1 5 5 It is divided into 1-, 7-, 7-, 7-, and ^ -shell computing power, and outputs the data in the table 1 to the checksum of kZ14. The first checksum generator 153 and the second _ are connected to each other. The first The checksum generator (the first and second generators 1 5 5 use the same algorithm and register g ~ reg-1, reg-2), and recursively The 2-5 6-bit output from the static energy machine memory 11 is taken into account, and the two checksums are used to generate a cry. _R raqi " In this example, make L, ^^ ^ The generation can be based on the difference in the width of the recording media data. 乂 l chooses to generate the width checksum from the first checksum, or to output 8-bit data and generate the n T checksum generator 153 and the second calibration. Verification | = 155 common operation to output a checksum of 16-bit data width. The raw 浐 to i 157 157 compares the written data to the flash memory 17 and generates the memory 17 to read the same data. The checksum table 1_ is for the maintenance function. The counter 疋 is used to control the result value of the positive plate after the comparator 157 comparison. M Page 9 200540607 V. Description of the invention (6) Number. In this embodiment The data width of the medium flash memory 7 is 16 bits, so the checksum written in the flash memory 17 must conform to the data width of 16 bits. In the method of this embodiment, the static random storage is performed. Take the memory 丨 丨 The outputted data of 2 5 6 bytes is divided into half, and it can be regarded as two parts of data of high byte and low byte. The first checksum generator 15 3 calculates the data of the low byte, and the second checksum generator 15 5 is responsible for the data of the high byte. 'Please read the third figure' Flash memory control flow chart. Block 31 shows the execution steps of the first checksum generator 153, and Block 32 shows the second checksum generator 155. Steps are performed. In this embodiment, the data is written by the memory access controller 19 from the static random access memory 11 to transmit 2 5 6 bytes of data to the flash memory 17 (S301); at this time, index = 0 (S30 3), the value of Index is used to indicate one of the data of 256 bytes; judge 1 ^ 8 (1 = 1 (83〇5), re ad status represents the first checksum generator i 53 can receive the data, if not continue to judge; otherwise, the index value is increased by one (S3 0 7), and one of the data of 256 byte data is specified; query the corresponding data of the comparison table 1 5 丨 (S3 〇9; will correspond to The data is input to the first checksum generator 1 5 3, and the values of the three registers in the first checksum generator 153 are calculated according to the algorithm (S3 11); x = 2 5 6 (S313); if yes, output 3 sets of checksum values with 8-bit data width (s3 1 5); otherwise, determine whether the output data width is equal to 8 bits (s 3 1 7), The data width here refers to the flash memory 17 'this embodiment is described by using 8 and 16 bits as examples; if yes, it represents the flash memory.

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Page 10 200540607 V. Description of the invention (7) The data width of the memory 1 7 is 8, and it returns to step s 3 0 5 to continue the first checksum generator 1 7 operation 2 5 6 bits in a recursive manner. Group data; otherwise, the flash memory 17 data width is 16 bits, judging read = 1 (S317), the re ad status represents whether the second checksum generator ι55 can receive data, if not continue to judge; otherwise, the Index value increases One (S321); query the comparison table 151

Corresponding data (S3 23); Input the corresponding data into the second checksum generator 1/5 'and calculate the values of the three registers in the second checksum generator 1 5 5 according to the algorithm (S3 2 5) '· Judgment Index = 2 5 6 (S32 7); if yes, output 3 sets of checksum values (s 3 2 9) with 16 bit width of material, if not, go to step S 3 0 5 In a recursive manner, the first checksum generator 5 3 and the second board checksum generator 1 5 5 jointly calculate 2 5 6 bytes of data. In this implementation, the first checksum generator 15 3 and the second checksum are generated. | 5 5 both have 8-bit το computing power. The data width of the flash memory 7 can be 8 or 1 6 At this point, when data is to be written to the flash memory 17: the algorithm of the present invention will determine the data width of the flash memory 17, the right flash memory 17 is equal to + θ. ^. τ 〇 The width of the unit is 8 bits, then the static random access memory 11 outputs 2 5 6 bits New: owed, " Calculated to generate the data width All Belo materials are generated by the first checksum The data width of the memory device 153 is three sets of checksums of 8 bits. @ 当 快闪 记 9, R.. ^, 16-bit, then the static random access memory 1 1 outputs 2 56 6-bit 70 groups of data by f,

The checker generator 153 and the second checksum generator 153 and the second checksum generator ^ ^ generate three sets of checksums with a data width of 16 bits each. Please refer to the fourth figure, the memory data and The verification data is shown as a control flowchart for reading the integrity of the flash memory according to the present invention. Read flash memory

200540607 V. Description of the invention (8) Calculate 1 7 data and calculate the checksum (" i7 has Ϊ ΐ ΐ Checksum, in order to determine: ί 资料 data in flash memory materials ^ Valley is wrong It is necessary to perform the same operations for reading = this and flash memory 17 with the same calculation method as in the third figure; Judgment No. 2; Do checksum operation S4 0 3) 'If otherwise continue to calculate; if 计算And r and whether to calculate the completed value (S40 5), the new and old corrections referred to here = write and read the memory of the old and new checksums 17 respectively. The same data is stored in the flash correction comparator 157. Execute and compare the results ^ _ and, the comparison is determined by the memory; determine whether the comparison is not equal (S4〇7) Tsai — in ~ data — cmp temporarily; if it is, it represents the dryness of the old and new checksums τ 1 μ 'If no, it means j data is correct;

Whether the data can be repaired (S40 9). The judge further judges the damage. If it indicates that the damaged data cannot be recovered: :: law; definite. Whether the number of comparison results 1 is i (S4 丨 υ 口 Μ Two more further judgments "two nos / tables, occurred in the data: correct the error of ^ by Yi 157, if it indicates that the error occurred in the checksum than the correction of the checksum by the correction comparator 15 7."

In this embodiment, the first checksum generator 153 and the second checksum generator 155 both have 8-bit computing capabilities. The data width of the flash memory 17 may be 8 or 16 bits, as an example. Instructions. However, the main spirit of the present invention is to explain the use of multiple checksum generators to jointly calculate the checksum of a series of input data, which can be applied to recording media with different data widths, thereby making the operation of the present invention more Flexible choice. In summary, the present invention fully complies with the requirements for patent applications. Therefore, if you apply for it in accordance with the Patent Law, please check it in detail and ask Huizhun for the patent.

200540607 V. Explanation of the invention (9) To protect the rights of the inventor, if there is any suspicion of the review committee of the Bureau, please write to us. However, the above description is only a detailed description and a drawing of one of the best specific embodiments of the present invention. Anyone skilled in the art can easily consider the changes or modifications in the field of the present invention. The patent scope of this case is as follows.

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Page 13 200540607 Brief description of the drawings [Simplified description of the drawings]: (1) The first diagram is an architecture diagram of the memory read-write control of the present invention; the second diagram is an architecture diagram of the error check circuit of the present invention The third diagram is a control flowchart for writing check data to the flash memory to generate a checksum according to the present invention; and the fourth diagram is a control flowchart for reading flash memory data and verifying the integrity of the data according to the present invention. (2) Description of drawing number 11 static random access memory 13 memory access controller 15 error checking circuit 17 flash memory 19 direct memory access controller 151 to show table 153 first checksum generator 155 Second checksum generator 157 Calibration comparator 159 Count table

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Claims (1)

200540607 6. Scope of patent application 1. An error checking circuit with a variable transmission data width for receiving a series of input data and writing the input data to a recording medium with a first data width or a second data width, The error checking circuit includes: a first check sum generator for receiving the string of input data, and generating a first set of check sums to be written into the recording medium after calculation; and a second check sum And a generator, which are coupled to the first checksum generator to receive the string of input data and generate a second set of checksums to be written into the recording medium after calculation, wherein the second data width is Is greater than the first data width, and when the data width of the recording medium is equal to the first data width, the first checksum generator receives all the input data, and when the data width of the recording medium is equal to the first data width When the data width is two, the input data is divided into half and received by the first checksum generator and the second checksum generator, respectively. 2. The error checking circuit with variable transmission data width as described in item 1 of the scope of patent application, wherein the first checksum generator has a plurality of registers internally for temporarily storing the calculated values. 3. The error check circuit with variable transmission data width as described in item 1 of the scope of the patent application, wherein the second checksum generator has a plurality of registers internally for temporarily storing the calculated values. 4. The error checking circuit with variable transmission data width as described in item 1 of the scope of patent application, further includes a comparison table for querying the input Page 15 200540607 VI. Scope of patent application The data corresponding to each byte of the data is output to the first checksum generator and the second checksum generator for operation. 5. The error checking circuit with variable transmission data width as described in item 1 of the scope of the patent application, further includes a correction comparator to compare the checksum generated by the written data on the recording medium with the read recording medium. Whether the checksums generated by the data are equal. 6. A memory system comprising: a first memory having a first data width; a second memory having a second data width; a first checksum generator for receiving the first The output data of the memory is processed to generate a first set of checksums to be written into the second memory; a second checksum generator is coupled to the first checksum generator to be used for Receiving output data from the first memory, and generating a second set of checksums to write to the second memory through calculation; and a memory access controller, which controls the first memory and the second memory When the first data width is equal to the second data width, controlling the first checksum generator to receive all the data in the first memory, and when the second data width is greater than The first data width controls half of the output data of the first memory and is received by the first checksum generator and the second checksum generator respectively. 7. The memory system as described in item 6 of the scope of the patent application, wherein the first checksum generator has a plurality of temporary registers for calculation values Page 16 200540607 VI. Scope of Patent Application Temporary deposit. ^ Applicable patent scope ^ I " School Ride ^ + The memory system described in item b & Gan + only the checksum generator 丨 ~ system, where the ^ # is provided with a plurality of registers for calculation values 8 Temporary comparison table, as shown in the patent application scope, for the memory system described in item 2 above, which still includes-data, and rotates to the generator operation corresponding to each byte of the input data. Checksum generator and the second checksum production-correction ratio J Ϊ Stem :: The memory system described in item 6 also includes checksum and readout records; = = = method, which generates a checksum And receiving-serial rotation of data;-3 recorded media, including the following steps: cutting the input data and fighting materials; Gastroenterology is-part-information and-part two: the first Part of the data is generated by -the first checksum. = The second part of the data is generated by the -second checksum ;: The first, second, and second parts of the data are different by the second The first checksum generator and the second checksum generator; and the parent writes the operation results of the first set of checksum generators and the second set of checks on the recording medium. Zodiac 1 2. Please refer to the operation of the error checking circuit described in item i i of the patent scope. Page 17 200540607 6. Application for patent scope The method still includes the steps of: judging the data width of the recording medium. 1 3. The method of operating an error checking circuit as described in item 11 of the scope of patent application, wherein the first checksum generator operates the first portion of data to generate a first set of checksums. 14. The method of operating an error checking circuit as described in item 11 of the scope of patent application, wherein the second checksum generator operates the second part of the data to generate a second set of checksums. Page 18