200537221 玖、發明說明： 【發明所屬之技術領域】 本發明提供一種製造矩陣排列元件之方法，尤指一種製造薄膜 電晶體液晶顯示器（ΤΠ-LCD)之方法。 ' 【先前技術】 隨著科技的日新月異，資訊產品也逐漸朝向小型化、高效率以 及方便攜帶的方向發展，而其中顯示裝置更扮演了一個非常重要 的關鍵角色。近年來，顯示裝置在提高品質、增加面積以及降低 成本上，有著長足的進展。一般而言，液晶顯示器具有重量輕、 功率消耗少以及低輕射專荨的優點’因此，液晶顯示器已廣、、乏地 應用於市面上多種可攜式資訊產品，例如筆記型電腦（n〇teb〇处） 以及個人數位助理（personal digital assistant，PDA)等商口。 此外’液晶螢幕以及液晶電視亦已逐漸普及，取代傳統使用的阶 極射線管（cathode ray tube，CRT)顯示器和電視。因此，如何有 效地提高液晶顯示器的產量，並降低製造成本，實已成為目前一 個重要的課題。 不管是傳統的扭轉向列型液晶顯示器（TN-LCD)，或是近來逐漸 ，及的廣視角液晶顯示器，例如橫向電場液晶顯示器〇pS_LCD)或 是多域垂直排列液晶顯示器（MVA—LCD)，皆是使用開關元件來控制 影像切換。薄膜電晶體（Thin Film Transistor，TFT)是一種常用 的開關7L件’其包含了閘極電極、源極電極、汲極電極以及其他 '、、要的半導體層和隔絕層（insulating layer)。而整個液晶顯示 為的製造流程’往往也取決於薄膜電晶體的製造步驟，因此簡化 薄膜電晶體的製造步驟可以有效地降低液晶顯示器的製造成本。 200537221 習知液晶顯示器中的薄膜電晶體製造方法，是利用四道或五道 光罩來完成。構成薄膜電晶體的必要元件包含了閘極電極、源極 電極、>及極電極以及通道區域，而為了製造這些必要的元件，必 須進行一些固定而且無法省略的製程步驟。然而，隨著半透微影 技術（halftone photolithograph)的成熟，微影蝕刻製程可以僅 使用一道光罩來形成不同厚度的光阻層，而此種半透微影技術也 使得縮減薄膜電晶體的製造流程成為可行。 【發明内容】 因此本發明之主要目的在於提供一種薄膜電晶體之製造方 法，其可以簡化上述習知之製造流程。 根曰據本發明之申請專利範圍，係揭露一種製造液晶顯示器之薄 膜電晶體之方法。該方法係先依序於基板上沉積翻導電層\第 -金屬層、第一隔絕層、半導體層以及第二金屬層。接： :第：=蝕刻製程去除部分第二金屬層、半導體層、第—二 曰第一金屬層以及透明導電層’以形成雜電極 :、、、 及通道區域。之後，沉積第二隔絕層 ^電極以 屬層使源極電極以及汲極電極與其他接m:積第三金 微影蝕刻製程以去除部分第三金屬仃一第三 一半透微影製程，且第-半透微影製程會在；包含第 一光阻層以及第二光阻層。 在第一金屬層上形成第 根據本發明之申請專利+ 法°該方法俾先依疼焕真士圍揭路一種製造液晶顯示器之方 - 序於基板上沉㈣日轉電層 '帛- ι邑層、半導體層以及第二金曰弟*屬層、第 刻製程去除部分第二金屬 接進行第-微影麵 干㈣層第-隔絕層、第—金屬 200537221 層以及透明導電層，以形成掃描線及共通電壓線，並定義薄膜電 晶體區域、通道區域以及晝素電極區域。之後，沉積第二隔絕層， 並進行第二微影蝕刻製程去除部分第二隔絕層、半導體層、第一 隔絕層以及第一金屬層，以形成複數個接觸孔並曝露出部分透明 導電層。最後，沉積第三金屬層，並進行第三微影蝕刻製程，以 形成貢料線與電容區域’並電連接溥膜電晶體區域與晝素電極區 域。第一微影蝕刻製程包含第一半透微影製程，且第一半透微影 製程會在第二金屬層上形成第一光阻層以及第二光阻層。 相較於習知液晶顯示器之薄膜電晶體的製造方法，本發明具有 可簡化製造流程的優點。以液晶顯示器之製造流程來說，所須之 光罩數目可由現行之四道或五道光罩，減少為三道光罩。因此， 本發明可有效地降低薄膜電晶體液晶顯示器的製造成本。 【實施方式】 請參考圖一，圖一為一個液晶顯示器ίο的示意圖。液晶顯示 器10包含了複數條掃描線12、複數條資料線14、複數個開關元 件16以及複數個畫素電極18，其中每一個開關元件16連接一條 對應的掃描線12以及一條對應的資料線14,用來控制對應之畫素 電極的充電與否。 請再參考圖二至圖七，圖二至圖七詳盡地描述了本發明之液晶 顯示器10的製造流程。在本發明之第一較佳實施例中，先提供一 個透明基板20，之後如圖三所示，依序在基板20上沉積一透明導 電層22、一第一金屬層24、一第一隔絕層26、一半導體層28以 及一第二金屬層30。沉積完成之後，再進行一道第一微影蝕刻製 程。第一微影蝕刻製程包括進行一道第一半透微影製程並形成二 個不同厚度的光阻層，例如第一光阻層32以及第二光阻層34。在 200537221 進行第一半透微影製程時，會使用電子束或是雷射照射一具有狹 缝圖案的光罩，其中狹缝圖案係依據電子束或是雷射的波長而定 義，以在光阻層的不同部位形成不同的厚度。進行第一半透微影 製程之後，光阻層會形成第一光阻層32以及第二光阻層34二個 不同厚度的區域，之後再如圖二及圖三所示，進行一道第一餘刻 製程去除部分的第二金屬層30、半導體層28、第一隔絕層26、第 一金屬層24以及透明導電層22，以形成掃描線60和共通電壓線 62。之後，將第二光阻層34移除，並進行第二蝕刻製程製程去除 部分的第二金屬層30，以定義出源/汲極區域64、通道區域66以 及晝素電極區域68。 0 請參考圖四及圖五。當第一微影蝕刻製程結束之後，接著沉積 第二隔絕層36並進行第二微影蝕刻製程。首先，進行一道第二半 透微影製程，以形成第三光阻層38和第四光阻層39,用來定義第 二隔絕層36的圖案。接著，第二微影蝕刻製程再利用一道第三蝕 刻製程，去除未被第三光阻層38和第四光阻層39遮蓋的部分之 第二隔絕層36、半導體層28、第一隔絕層26以及第一金屬層24。 然後，去除第四光阻層39，並去除部分的第二隔絕層36，以形成 複數個接觸孔70。在第二微影蝕刻製程之後，部分的透明導電層 22會被曝露出來，被曝露出來的區域與晝素電極區域68的圖案相 · 符，而二個接觸孔70則是位於源/汲極區域64中被曝露出來的第 二金屬層30上。 請參考圖六和圖七。進行完第二微影蝕刻製程之後，沉積第三 金屬層40和保護層41，並接著進行第三微影蝕刻製程。首先，形 成第三金屬層40、保護層41以及第五光阻層42，再進行一道第 四蝕刻製程移除部分的第三金屬層40和保護層41，以形成資料線 72、導電區域74以及電容區域76。資料線72經由一個接觸孔70 與源/汲極區域64電連接，而導電區域74則是經由另一個接觸孔 11 200537221 70與源/汲極區域64及晝素電極區域68導通。如圖六和圖七中所 不，二個畫素電極區域68的邊緣分別位於共通電壓線62的二邊， 而且共通電壓線62上覆蓋有第二隔絕層36。第三金屬層4〇跨越 共通電壓線62，電連接二個畫素電極區域68，不但可以導通二個 畫素電極區域68，還可以與共通電壓線62形成電容區域％。此 外，第二金屬層40還可以在接觸墊78的位置，依照需求導通第 一金屬層24和第二金屬層3〇，其中接觸墊78係用來與驅動電路、 驅動晶片或是共通電壓電連接。 本々發明之製造方法亦可再加以變化。在下面的第二較佳實施例 第祕衫钱刻製程與上述第一較佳實施例相似，但是第二微 影蝕刻製程與第三微影蝕刻製程則稍有不同。 一几 π參考圖人。在完成第_微影蝴製程之後，沉積第二隔絕芦 36並進行不同的第二微影_製程。在進行第二微純刻製程曰 ^，只形成第二光阻層38來定義第二隔絕層36的圖案。第二 則製程，去除未被第三光阻層3二第 層32遮蓋的部分之第二隔絕層36、半導體層28、第二ί 化^Hi金屬層2 4。第五刻Μ㈣使祕有冑選擇比的 ^ 金屬層24並保留第二金屬層30。因為第金 第第—金屬層30化學特性的差異，選用的溶液可以僅斑 二在進行過第二遍刻製程之後，部分的透 的圖宰:目符出來，被曝露出來的區域與畫素電極區域68 %再參考圖九。進行完第二微·刻製程之後 a 40和保護層41，並接著進行第二 三金屬声40、仅嗜麻η 仃乐一铽衫蝕刻製私。百先，形居 仝屬層40保護層41以及第五光阻層42，再進行一道第六 12 200537221 刻製程移除部分的第三金屬層40和保護層41，以形成資料線72、 導電區域74以及電容區域76。 基板20係由可讓光線穿透的材質構成，例如玻璃基板、石英 基板或是塑膠基板。透明導電層22的材質係為氧化銦錫（ΙΤ0)或 是氧化銦辞（ΙΖ0)。第一金屬層24、第二金屬層30以及第三金屬 層40係由鎢（w)、鉻（Cr)、鋁（A1)、銅（Cu)、錳（Mo)或上述任意 金屬之合金所組成。 上述的較佳實施例係以TN型的薄膜電晶體液晶顯示器之製造 流程來說明，而其他例如STN、IPS或是MVA類型的薄膜電晶體液_ 晶顯示器之製造方法亦與上述較佳實施例類似。相較於習知的製 造方法，本發明可以有效地簡化製造流程，達到降低製造成本的 目的。 以上所述僅為本發明之較佳實施例，凡依本發明申請專利範圍 所做之均等變化與修飾，皆應屬本發明專利之涵蓋範圍。 【圖式簡單說明】 圖式之簡單說明 圖一為本發明液晶顯示器之示意圖。 圖一至圖七為本發明第一較佳實施例之製造流程示意圖。 圖八至圖九為本發明第二較佳實施例之製造流程示意圖。 圖式之符號說明 10 14 液晶顯示器 資料線 12 掃描線 16 開關元件 13 200537221 18 畫素電極 20 基板 22 透明導電層 24 第一金屬層 26 第一隔絕層 28 半導體層 30 第二金屬層 32 第一光阻層 34 第二光阻層 36 第二隔絕層 38 第三光阻層 39 第四光阻層 40 第三金屬層 41 保護層 42 第五光阻層 60 掃描線 62 共通電壓線 64 源/汲極區域 66 通道區域 68 晝素電極區域 70 接觸孔 72 資料線 74 導電區域 76 電容區域 78 接觸墊200537221 (1) Description of the invention: [Technical field to which the invention belongs] The present invention provides a method for manufacturing a matrix array element, particularly a method for manufacturing a thin film transistor liquid crystal display (TΠ-LCD). '[Previous technology] With the rapid development of technology, information products have gradually developed toward miniaturization, high efficiency, and portability, and the display device has played a very important key role. In recent years, display devices have made great progress in improving quality, increasing area, and reducing cost. Generally speaking, liquid crystal displays have the advantages of light weight, low power consumption, and low light emission. Therefore, liquid crystal displays have been widely and seldom used in a variety of portable information products on the market, such as notebook computers (n〇 teb〇) and personal digital assistant (personal digital assistant (PDA)). In addition, LCD screens and LCD TVs have gradually become popular, replacing traditionally used cathode ray tube (CRT) displays and TVs. Therefore, how to effectively increase the output of liquid crystal displays and reduce manufacturing costs has become an important issue at present. Whether it is a traditional twisted nematic liquid crystal display (TN-LCD), or a recent wide-view liquid crystal display, such as a lateral electric field liquid crystal display (pS_LCD) or a multi-domain vertical alignment liquid crystal display (MVA-LCD), Both use switching elements to control image switching. A thin film transistor (TFT) is a commonly used 7L component of a switch, which includes a gate electrode, a source electrode, a drain electrode, and other semiconductor layers and an insulating layer. The entire manufacturing process of a liquid crystal display often depends on the manufacturing steps of the thin film transistor. Therefore, simplifying the manufacturing steps of the thin film transistor can effectively reduce the manufacturing cost of the liquid crystal display. 200537221 The conventional method for manufacturing thin film transistors in liquid crystal displays is accomplished by using four or five masks. The necessary elements for forming a thin film transistor include a gate electrode, a source electrode, > and electrode electrodes, and a channel region. In order to manufacture these necessary elements, some fixed and unavoidable process steps must be performed. However, with the maturity of halftone photolithograph, the lithography etching process can use only one photomask to form photoresist layers with different thicknesses, and this type of transflective lithography also reduces the thickness of thin film transistors. The manufacturing process becomes feasible. SUMMARY OF THE INVENTION Therefore, the main object of the present invention is to provide a method for manufacturing a thin film transistor, which can simplify the conventional manufacturing process. According to the patent application scope of the present invention, a method for manufacturing a thin film transistor of a liquid crystal display is disclosed. In this method, a conductive layer, a first metal layer, a first insulation layer, a semiconductor layer, and a second metal layer are sequentially deposited on a substrate. Connect :: No.:= The etching process removes part of the second metal layer, the semiconductor layer, the first-second metal layer and the transparent conductive layer 'to form a heteroelectrode: ,, and, and a channel region. After that, a second insulating layer is deposited as an electrode layer to connect the source electrode and the drain electrode to each other: a third gold lithography process to remove a portion of the third metal, a third half through the lithography process, And the -semi-transmissive lithography process will be there; including a first photoresist layer and a second photoresist layer. Forming the first patent + method according to the present invention on the first metal layer. This method firstly unveils a method for manufacturing a liquid crystal display according to Tonghuan Zhenshi-Sequentially depositing a day-to-day electricity transfer layer on a substrate '帛-ι The eutectic layer, the semiconductor layer, and the second metal layer, the second metal removing part of the first process is connected to the -lithographic surface dry layer, the -isolating layer, the -metal 200537221 layer, and the transparent conductive layer to form Scan lines and common voltage lines, and define thin film transistor regions, channel regions, and day electrode regions. After that, a second isolation layer is deposited and a second lithographic etching process is performed to remove a portion of the second isolation layer, the semiconductor layer, the first isolation layer, and the first metal layer to form a plurality of contact holes and expose a part of the transparent conductive layer. Finally, a third metal layer is deposited and a third lithographic etching process is performed to form a tributary line and a capacitor region 'and electrically connect the tritium film transistor region and the day electrode region. The first lithographic etching process includes a first semi-transparent lithographic process, and the first semi-transparent lithographic process forms a first photoresist layer and a second photoresist layer on the second metal layer. Compared with the conventional method for manufacturing a thin film transistor of a liquid crystal display, the present invention has the advantage of simplifying the manufacturing process. In terms of the manufacturing process of the liquid crystal display, the required number of photomasks can be reduced from the current four or five photomasks to three photomasks. Therefore, the present invention can effectively reduce the manufacturing cost of the thin film transistor liquid crystal display. [Embodiment] Please refer to FIG. 1. FIG. 1 is a schematic diagram of a liquid crystal display. The liquid crystal display 10 includes a plurality of scanning lines 12, a plurality of data lines 14, a plurality of switching elements 16 and a plurality of pixel electrodes 18, wherein each switching element 16 is connected to a corresponding scanning line 12 and a corresponding data line 14. , Used to control the charging of the corresponding pixel electrode. Please refer to FIGS. 2 to 7 again. FIGS. 2 to 7 describe the manufacturing process of the liquid crystal display 10 of the present invention in detail. In the first preferred embodiment of the present invention, a transparent substrate 20 is provided first, and then as shown in FIG. 3, a transparent conductive layer 22, a first metal layer 24, and a first insulation layer are sequentially deposited on the substrate 20 in order. The layer 26, a semiconductor layer 28 and a second metal layer 30. After the deposition is completed, a first lithographic etching process is performed. The first lithographic etching process includes performing a first transflective lithography process and forming two photoresist layers with different thicknesses, such as the first photoresist layer 32 and the second photoresist layer 34. In 200537221, during the first semi-transparent lithography process, an electron beam or laser was used to illuminate a mask with a slit pattern, where the slit pattern was defined according to the wavelength of the electron beam or laser to Different portions of the resist layer form different thicknesses. After the first semi-transparent lithography process is performed, the photoresist layer will form two areas of different thicknesses, namely a first photoresist layer 32 and a second photoresist layer 34. Then, as shown in FIGS. 2 and 3, a first step is performed. The part of the second metal layer 30, the semiconductor layer 28, the first isolation layer 26, the first metal layer 24, and the transparent conductive layer 22 are removed by the remaining processes to form the scan lines 60 and the common voltage line 62. After that, the second photoresist layer 34 is removed, and a second etching process is performed to remove part of the second metal layer 30 to define a source / drain region 64, a channel region 66, and a day electrode region 68. 0 Please refer to Figure 4 and Figure 5. After the first lithographic etching process is completed, a second isolation layer 36 is then deposited and a second lithographic etching process is performed. First, a second transflective process is performed to form a third photoresist layer 38 and a fourth photoresist layer 39, which are used to define the pattern of the second isolation layer 36. Next, the second lithographic etching process uses a third etching process to remove the second insulating layer 36, the semiconductor layer 28, and the first insulating layer of the portions not covered by the third photoresist layer 38 and the fourth photoresist layer 39. 26 和 第一 金属 层 24。 26 and the first metal layer 24. Then, the fourth photoresist layer 39 is removed, and a part of the second insulating layer 36 is removed to form a plurality of contact holes 70. After the second lithographic etching process, a part of the transparent conductive layer 22 will be exposed. The exposed area matches the pattern of the day electrode region 68, and the two contact holes 70 are located at the source / drain. The region 64 is exposed on the second metal layer 30. Please refer to Figure 6 and Figure 7. After the second lithographic etching process is performed, a third metal layer 40 and a protective layer 41 are deposited, and then a third lithographic etching process is performed. First, a third metal layer 40, a protection layer 41, and a fifth photoresist layer 42 are formed, and then a fourth etching process is performed to remove the third metal layer 40 and the protection layer 41 to form a data line 72 and a conductive region 74. And the capacitance region 76. The data line 72 is electrically connected to the source / drain region 64 through a contact hole 70, and the conductive region 74 is electrically connected to the source / drain region 64 and the day electrode region 68 through another contact hole 11 200537221 70. As shown in FIGS. 6 and 7, the edges of the two pixel electrode regions 68 are respectively located on two sides of the common voltage line 62, and the common voltage line 62 is covered with a second insulation layer 36. The third metal layer 40 crosses the common voltage line 62 and is electrically connected to the two pixel electrode regions 68. Not only can the two pixel electrode regions 68 be conducted, but also a capacitance region% can be formed with the common voltage line 62. In addition, the second metal layer 40 can also be at the position of the contact pad 78 to conduct the first metal layer 24 and the second metal layer 30 as required. The contact pad 78 is used for driving the circuit, the driving chip, or the common piezoelectricity. connection. The manufacturing method of the present invention can also be changed. The second preferred embodiment below is similar to the first preferred embodiment, but the second lithographic etching process and the third lithographic etching process are slightly different. A few π reference figure people. After the second lithography process is completed, a second isolation reed 36 is deposited and a different second lithography process is performed. During the second micro-pure engraving process, only the second photoresist layer 38 is formed to define the pattern of the second isolation layer 36. In the second process, the second insulating layer 36, the semiconductor layer 28, and the second metal layer 24 are removed from the portions not covered by the third photoresist layer 32 and the second layer 32. In the fifth moment, the metal layer 24 having the selective ratio is retained and the second metal layer 30 is retained. Because of the difference in the chemical properties of the first and second metal layer 30, the selected solution can only be spotted. After the second pass of the engraving process, a part of the transparent image is displayed: the target symbol appears, the exposed area and pixels. The electrode area is 68% again referring to Figure IX. After the second micro-etching process is performed, a 40 and the protective layer 41 are performed, and then the second and third metal sounds 40 are performed, and only the hemp-prone η 铽 铽 铽 铽 shirt is etched for private use. Baixian, the protective layer 41 and the fifth photoresist layer 42 of the same layer 40 are formed, and then a sixth 12 200537221 etch process is performed to remove the third metal layer 40 and the protective layer 41 to form the data line 72 and conduct electricity. Region 74 and capacitor region 76. The substrate 20 is made of a material that allows light to pass through, such as a glass substrate, a quartz substrate, or a plastic substrate. The material of the transparent conductive layer 22 is indium tin oxide (ITO) or indium oxide (IZO). The first metal layer 24, the second metal layer 30, and the third metal layer 40 are made of tungsten (w), chromium (Cr), aluminum (A1), copper (Cu), manganese (Mo), or an alloy of any of the foregoing metals. composition. The above-mentioned preferred embodiment is described by using a manufacturing process of a TN-type thin-film transistor liquid crystal display, and other methods such as STN, IPS, or MVA-type thin-film transistor liquid crystal display manufacturing methods are also the same as the above-mentioned preferred embodiments. similar. Compared with the conventional manufacturing method, the present invention can effectively simplify the manufacturing process and reduce the manufacturing cost. The above description is only a preferred embodiment of the present invention, and all equivalent changes and modifications made in accordance with the scope of patent application of the present invention shall fall within the scope of the patent of the present invention. [Brief description of the drawings] Brief description of the drawings FIG. 1 is a schematic diagram of a liquid crystal display of the present invention. 1 to 7 are schematic diagrams of the manufacturing process of the first preferred embodiment of the present invention. 8 to 9 are schematic diagrams of a manufacturing process of a second preferred embodiment of the present invention. Description of the symbols 10 14 LCD data line 12 Scan line 16 Switch element 13 200537221 18 Pixel electrode 20 Substrate 22 Transparent conductive layer 24 First metal layer 26 First insulation layer 28 Semiconductor layer 30 Second metal layer 32 First Photoresist layer 34 Second photoresist layer 36 Second insulation layer 38 Third photoresist layer 39 Fourth photoresist layer 40 Third metal layer 41 Protective layer 42 Fifth photoresist layer 60 Scan line 62 Common voltage line 64 Source / Drain region 66 Channel region 68 Day electrode region 70 Contact hole 72 Data line 74 Conductive region 76 Capacitive region 78 Contact pad
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