TW200536096A - Chip-type sensor against esd and stress damages and contamination interference - Google Patents

Chip-type sensor against esd and stress damages and contamination interference Download PDF

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TW200536096A
TW200536096A TW93110603A TW93110603A TW200536096A TW 200536096 A TW200536096 A TW 200536096A TW 93110603 A TW93110603 A TW 93110603A TW 93110603 A TW93110603 A TW 93110603A TW 200536096 A TW200536096 A TW 200536096A
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layer
stress
chip
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TW93110603A
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TWI233198B (en
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Bruce C S Chou
Wallace Y W Cheng
Chen-Chih Fan
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Lightuning Tech Inc
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Abstract

A chip-type sensor against ESD and stress damages and contamination interference includes a substrate structure and a protection layer covering over the substrate structure. The protection layer includes, from bottom to top, a first layer for providing a first stress against the substrate structure, a second layer for providing a second stress against the substrate structure, and a third layer for providing a third stress against the substrate structure. The first stress and the third stress belong to one of a tensile stress and a compressive stress, and the second stress belongs to the other of the tensile and compressive stresses.

Description

200536096 五、發明說明(1) 【發明所屬之技術領域】 之曰於:種可抗靜電與應力破壞及防殘污干擾 ;曰2 ί::播是關於一種晶片式指紋感測器具有 一表面保蠖層結構的設計,蕤 巧 及防止指紋殘留所造成之干;2供耐Μ、耐靜電破壞、 給本案受讓人之下4請二擾;發明係關聯至讓渡 091106_,t _ g 1中華民國專利申請案序號 指η Μ / 年4月3日,發明名稱為「電容式 =二」申,= ^ ^ ^ ^ 、月日為2 0 0 3年5月6日,發明名稱為「可抗 :電石:及防殘污干擾之電容式指紋感測器及其製造方 / J玍 華民國專利申請案序號0 9 2 1 246 97,中請曰為 曰發明名稱為「能防止指紋殘留之電容式指 紋感測器及其處理太、土 · Ώ / 、 〇 92 1 32 480,申請日Υ2〇」〇= 4)中華民國專利申請案序號 裝置的表面處理方ΛΤ田月20曰’發明名稱為晶片 万去及使用該方法所形成之晶片裝置」。 【先前技術】 去卢ΐ ΐ導體製程領域所提供的晶片製造方式中,通常需 隱$ Γ =提i、的電特性’並且需將晶片透過封裝的程序 Λ ' 4基體中’以免除例如壓力及靜電等外力的任何200536096 V. Description of the invention (1) [Technical field to which the invention belongs] Said in: a kind of anti-static and stress damage and anti-fouling interference; 2: :: is a chip-type fingerprint sensor with a surface protection The design of the sublayer structure is ingenious and prevents the dryness caused by fingerprint residues; 2 for resistance to M, anti-static damage, to the assignee of the case 4 for two disturbances; the invention is related to transfer 091106_, t _ g 1 The Republic of China patent application serial number refers to η Μ / April 3, year, the invention name is "capacitive = two" application, = ^ ^ ^ ^, month date is May 6, 2003, and the invention name is " Capable of resisting: calcium carbide: and anti-fouling interference capacitive fingerprint sensor and its manufacturer / J 玍 华 民 民 Patent Application No. 0 9 2 1 246 97, the name of the invention is "can prevent fingerprint residue" Capacitive fingerprint sensor and its processing device Tai, Tu · Ώ /, 〇92 1 32 480, application date Υ20 ″ 0 = 4) Surface treatment method of the Republic of China patent application serial number device ΛΤ 田 月 20 said 'Invention The name is wafer and the wafer device formed by this method. " [Previous technology] In the wafer manufacturing methods provided in the field of conductor processing, it is usually necessary to hide the electrical characteristics of $ Γ = mention i, and to pass the chip through the packaging process Λ '4 substrate' to avoid, for example, pressure And any external force such as static electricity

可能的破壞。 J 铁而隨菩日 Η 露部;之曰曰:應用領域的發展,新的應用使得必須裸 ^ ^ .日日5衣面於環境中,例如晶片式的指紋感測器便 舄要提供一盘丰ih & ^ 〃 丁和接觸的晶片表面(中華民國專利申請案Possible destruction. J Tieru follows the exposed part of the Bo Ri Sun; said: the development of application fields, new applications make it necessary to be naked ^ ^ 5 days and 5 clothes in the environment, such as chip-type fingerprint sensors will provide a Pan Feng ih & ^ Ding He contacted wafer surface (ROC patent application

200536096 五、發明說明(2) 序號0 9 1 1 0 6 8 0 6,申請日為2 〇〇2年4月3日,發明名稱為「電 容式指紋讀取晶片」,暫准專利中),以讀取手指的纹 路,作為身份識別使用。 、 為此,晶片表面的機械特性便必須被加以考量以 -财手指施壓及抗靜電破壞的結構。^彳如電容式指紋感 測晶片更需要考慮殘留指紋效應的問題。 習知技術上,電容式指紋感測晶片的基礎結構為在一 石夕基材内製作相關感測及控制處理電4,在晶片的表面佈 置矩陣型的複數金屬板作為感測電極(從此感測電極以下 包含感測及控制處理電路及矽基材將統稱為基板結構), ^且形成-介電材料層於晶片的最外表面,兼做感測電容 :二質以及晶片裸露於外的保護層。為達到上述晶片表面 :财磨的特性:習知技術都是利用一堅硬的介電材料 ^為敢外表層的保護層,例如世界專利 、^ 〇3/〇m41A1、、美國專利第6 〇91〇82、歐洲專利 EP1256899、美國專利第β 弟6, 1 1 4, 8 62唬及美國專利第 6:515,488號,都揭露了此一架構。簡而 ^明不外乎例如氮切、碳切、氧化銘或鑽石之一堅硬的 材料層形成於基板結構上方,抑或在二者=::一 3 的介電材料,例如氧化石夕。 t之門存g柔車人 μ 氣化石夕、碳化石夕、氧化銘或鑽石之堅硬材料層雖 然材料本質的強度特性良 =更柯付增雖 楚^、t板、、構上守各易受到厚度的限制,其原因乃為兮 、料層與基板結構間的熱殘餘應力所導致:、通常氮化μ200536096 V. Description of the invention (2) Serial number 0 9 1 1 0 6 8 0 6, the application date is April 3, 2002, the name of the invention is "capacitive fingerprint reading chip", patent pending), To read the lines of the finger, it is used for identification. For this reason, the mechanical characteristics of the wafer surface must be considered in order to protect the structure from the pressure of the fingers and anti-static damage. ^ For example, the capacitive fingerprint sensor chip needs to consider the residual fingerprint effect. Conventionally, the basic structure of a capacitive fingerprint sensor chip is to make related sensing and control processing electronics in a substrate, and arrange a plurality of metal plates of matrix type on the surface of the chip as sensing electrodes. The electrodes below include the sensing and control processing circuit and the silicon substrate will be collectively referred to as the substrate structure), and a dielectric material layer is formed on the outermost surface of the chip, which also serves as a sensing capacitor: the second quality and the protection of the chip exposed Floor. In order to achieve the above-mentioned surface of the wafer: the characteristics of financial grinding: the conventional technology uses a hard dielectric material ^ as a protective layer for the outer surface, such as the world patent, ^ 〇3 / 〇m41A1, US patent No. 6 091 〇82, European patent EP1256899, U.S. patent β 6,211, 8,62 and U.S. patent 6: 515,488, all disclose this structure. In short, it means that a hard material layer such as nitrogen cut, carbon cut, oxidized diamond or diamond is formed above the substrate structure, or a dielectric material, such as stone oxide, is used for both = :: 3. The gate of t is a soft rider. μ The hard material layer of gasified stone, carbonized stone, oxidized metal, or diamond. Although the material has good strength characteristics, it is more difficult to increase the thickness of the t plate, and the structure. The limitation is due to the thermal residual stress between the material layer and the substrate structure: usually nitriding μ

200536096 五 發明說明(3) 矽、碳化矽、氧化鋁或鑽石會 構造成張應力(tensile str彳基材為主的該基板結 該等材料於該基板結構上,會因J應,如果沈積太厚的 來’不僅晶片I易受力破損:也:而導致破$ ’如此-在半導體製程中僅能提供厚度小二法承受靜電破壞。通常 問題。雖然…仍然存在相二1米的製作以避免上述 容易產生材料缺陷,造成;㈡的熱殘餘應力於其中, 成破壞。為此,解決熱殘留應:以增= 造 (機三次方成正比),便成二重要ϋ。 口2課題。解決靜電破壞可以分:; 卜向=破= 與厚度平方成正比::如Ί 的靜電電場強度係 崎麻陪也 叙商用的積體電路製程,复仅 j:子度約為1微米(其材料通常為氧化矽及氮化矽的雔居 【,可以承受的靜電破壞電壓(air m〇de)約為曰 又因為上述發明的保護層結構無法有效增加其厚度γ , 上述發明無法僅利用保護層材料達到靜電破壞的防1而 導通=地方式是利用裸露金屬網狀結構將靜電荷 V逋至接地狀悲,例如上述發明WO 0 1 /0 6448M、W0 0 3/0 9 8 54 1 A1 、歐洲專利EP 1 25 68 9 9都有採用此一 種金屬導通靜電的概念在許多的電子產品都有採用’。,此 同者在於於晶片表面實施時需要考慮與積體電路制1 ^不 及材料的匹配性。 衣乂流程 例如,世界專獅(Π/關8A1揭露了裸露金屬網狀結200536096 Fifth invention description (3) Silicon, silicon carbide, aluminum oxide or diamond will be structured as tensile stress (tensile str 彳 substrates based on substrates. These materials will be bonded to the substrate structure. "Thickness comes" not only is the chip I vulnerable to damage: it also causes breakage. "So-in the semiconductor process, only the thickness of the second method can be provided to withstand electrostatic damage. Usually the problem. Although ... there are still phase two 1 meter production to Avoid the above-mentioned easy-to-generate material defects and cause; the thermal residual stress of ㈡ is in it and cause damage. For this reason, to solve the thermal residual should be: increase = manufacturing (proportional to the cube of the machine), it becomes the second important problem. Solving electrostatic damage can be divided into: bu xiang = broken = proportional to the square of thickness :: Rugao's electrostatic field strength is a commercial integrated circuit manufacturing process, which is only about 1 micron (its The material is usually a dwelling of silicon oxide and silicon nitride. The electrostatic breakdown voltage (air mOde) that can withstand is about 1500. Because the protective layer structure of the above invention cannot effectively increase its thickness, the above invention cannot use protection only. The layer material achieves anti-electrostatic destruction 1 and the conduction = ground method is to use a bare metal mesh structure to trap the electrostatic charge V to ground, such as the above-mentioned inventions WO 0 1/0 6448M, W 0 0 3/0 9 8 54 1 A1 The European patent EP 1 25 68 9 9 has adopted the concept of this kind of metal conducting static electricity. It is used in many electronic products. The same lies in the need to consider the integrated circuit system when implementing on the surface of the wafer. For example, the world's special lion (Π / 关 8A1 exposes a bare metal mesh knot

200536096 五、發明說明(4) 構作為靜電導通結構,然而所使用的製造流程中所採 例如單層T:N作為金屬感測電極及裸露金屬網 積體電路製程戶斤採用㈣準方法,且晶 不疋 易造成TiN薄膜導線的斷線問題,再者nN阻折也= 有瞬間的靜電大電流通過則容易燒斷。貝;:二 含了金材料,這樣的設計可以解決全二屬取卜表面包 這種製造流程,卻無法相容於石夕積;然而 材料會導致;亏$。 $路製程巾’因為金 歐洲專利EP 1 2 5 6 8 9 9號揭露一種鎢厶 鎢金屬的沈積及後續的回蝕步驟中二金屬網設計。然而在 保護層上形成許多小孔洞而造感=碳切 成感測器之破壞I:感測器之外表面時,會造 秋 丹有’被小孔洞的蛀 形成親水性,因此當手指的水分接$㈢使保護層表面 而使影像品質變差。為此,尚須 ,面時會擴散,進 續的化學機械研磨(CMP)製程而將氧θ礼化矽的沈積及後 而達到平整的外表面。然而,此兴乳化石夕填滿前述的小孔洞 雜,而不適合於-般商業晶圓代:廠^造過程太過複 〃又’當上述習知技術實施二電= 製f;序。 保濩層材料(上述保護層材料,曰、、、文感測晶片時, 避免手指的油及汗水殘留, :,水或親油特性)無法 形成殘留影像,影響後續 =指指紋殘留於晶片表面 、用 甚至可以藉此攻擊系統達200536096 V. Description of the invention (4) The structure is used as an electrostatic conduction structure, but the manufacturing process uses a single layer of T: N as the metal sensing electrode and the bare metal grid integrated circuit. The crystal is not easy to cause the disconnection of the TiN thin film wire, and the nN resistance is also equal to the instantaneous large static current, which is easy to burn. Bei;: 2 Contains gold material, this design can solve the manufacturing process of the surface package of all two genus, but it is not compatible with Shi Xiji; however, the material will cause; loss $. $ 路 制 程 巾 ’Because of gold European patent EP 1 2 5 6 8 9 9 discloses a tungsten rhenium tungsten metal deposition and the two metal mesh design in the subsequent etch-back step. However, many small holes are formed in the protective layer to create sensation = carbon cuts the damage of the sensor I: When the sensor is outside the surface, Qiutan will be made hydrophilic by the puppets of the small holes, so when the finger ’s The contact of moisture causes the surface of the protective layer to deteriorate the image quality. To this end, it is necessary that the surface will diffuse, and the continuous chemical mechanical polishing (CMP) process will deposit the oxygen θ and silicon silicon and then reach a flat outer surface. However, this kind of emulsified stone fills the aforementioned small holes and is not suitable for general commercial wafer generation: the manufacturing process is too complicated, and when the above-mentioned conventional technology is implemented, the second power = system f; sequence. The material of the protective layer (the above protective layer material, to avoid the residue of oil and sweat of the fingers when the wafer is sensed by the above-mentioned, to prevent the residual oil and sweat of the fingers, water, or lipophilic characteristics) can not form a residual image, affecting subsequent = refers to fingerprints remaining on the surface of the wafer You can even use this to attack the system to achieve

第10頁 200536096 五、發明說明(5) 到破解的目的。 因此,如何提供一種可抗靜電與應力破壞及防殘污干 擾之晶片式感測器,實為本案所欲解決之問題。 【發明内容】 因此,本發明之一個目的係提供一種晶片式指紋感測 器,其可對抗靜電與應力破壞,並能有效防止殘污干擾, 藉以提昇感測器之感測效果,並延長其使用壽命。 為達成上述目的,本發明提供一種可抗靜電與應力破 壞及防殘污干擾之晶片式感測器,其包含一基板結構及覆 蓋於該基板結構上之一保護層。保護層由下而上依序包 含:一第一層,用以對該基板結構提供一第一應力;一第 二層,用以對該基板結構提供一第二應力;及一第三層, 用以對該基板結構提供一第三應力,其中該第一應力與該 第三應力同屬於一張應力與一壓應力兩者之其一者,而該 第二應力屬於該張應力與該壓應力兩者之另一者,藉以減 少殘留應力。 【實施方式】 本發明之晶片式感測器,係以指紋感測器為例作說 明,其類型可以是電容式指紋感測器、溫差式指紋感測 器、電容壓力式指紋感測器等,然本發明並不以此為限。 圖1顯示利用本發明之電容式指紋感測器來讀取手指指 紋之示意圖。如圖1所示,此指紋感測器2係製作於矽基材Page 10 200536096 V. Description of the invention (5) To the purpose of cracking. Therefore, how to provide a chip-type sensor capable of resisting static electricity and stress damage and preventing residue interference is a problem to be solved in this case. [Summary of the Invention] Therefore, an object of the present invention is to provide a chip-type fingerprint sensor, which can resist the damage of static electricity and stress, and can effectively prevent the interference of residues, thereby improving the sensing effect of the sensor and extending it. Service life. In order to achieve the above object, the present invention provides a wafer-type sensor capable of resisting static electricity, stress damage, and anti-fouling interference, which includes a substrate structure and a protective layer covering the substrate structure. The protective layer includes, in order from bottom to top: a first layer for providing a first stress to the substrate structure; a second layer for providing a second stress to the substrate structure; and a third layer, It is used to provide a third stress to the substrate structure, wherein the first stress and the third stress belong to one of a stress and a compressive stress, and the second stress belongs to the tensile stress and the compression The other of the two is to reduce residual stress. [Embodiment] The chip sensor of the present invention is described by taking a fingerprint sensor as an example. The type can be a capacitive fingerprint sensor, a temperature difference fingerprint sensor, a capacitive pressure fingerprint sensor, etc. However, the present invention is not limited to this. FIG. 1 shows a schematic diagram of reading a finger print using a capacitive fingerprint sensor of the present invention. As shown in Figure 1, this fingerprint sensor 2 is fabricated on a silicon substrate

200536096200536096

五、發明說明(6) 上並切告1丨成一晶片形狀, 列之複數個電容式4^要/函^面積為二維(2 D )矩陣排 未示卜晶片的表面佈;? / A其周邊控制處理電路(圖中 (從此感測電極以下包人/型?复數♦金屬板作為感測電極 統稱為基板結構),並】感測及控制處理電路及石夕基材將 本品 m 亚且形成一介電材料層於晶片的最外 义當手指广接貝L電二介電質以及晶片裸露於外的保護層。 峰(Ri^gem會與ί ^ ^日卜手表面的不規則形狀紋 器2上留下對應於兮:嵝,谷式感測凡20接觸,而在該感測 容值曲線…的形;=的電=:線11&。透過讀取電 ^ 便可以辨遇原來紋峰1 1之形狀。 -円圖V系岡t圖1之電容感㈣元之第一實施例之局部側視示 :圖。”2所示,本發明之電容式指紋感測器包含一矽基 、稷數個(圖中僅顯示一個)感測電極22及一保護層 夕土材2 1、内έ有對應每一感測電極2 2之一感測電路 :^在感測元陣列周邊還包括一信號處理及控制電路 2 1 Β (示思地緣於圖4 )’詳細的感測元陣列與周邊電路設置 I以參考本專利發明者另一專利說請書(1)中華民國專利申 =案序號091106806,申請日為2〇〇2年4月3日,發明名稱為V. Description of the invention (6) It is stated above that a wafer shape is formed, and a plurality of capacitive 4 ^ requirements / functions are arranged in a two-dimensional (2D) matrix. The surface cloth of the wafer is not shown; / A Its peripheral control processing circuit (in the picture (hereafter the sensing electrode includes people / types? Plural metal plate as the sensing electrode are collectively referred to as the substrate structure), and] the sensing and control processing circuit and Shi Xi substrate will be the product m A layer of dielectric material is formed on the outermost part of the wafer. When the finger is in contact with the dielectric material of the second dielectric and the protective layer exposed on the wafer, the peak (Ri ^ gem will interact with The regular shape pattern 2 leaves a shape corresponding to Xi: 嵝, valley-type sensing where the 20 touches, and the shape of the sensing capacitance curve ... = electricity =: line 11 & by reading electricity ^ it can be Identifies the shape of the original ripple peak 11.-Figure V is a partial side view of the first embodiment of the capacitive sensing unit of Figure 1 in Figure 1: Figure. "2, the capacitive fingerprint sensing of the present invention The device includes a silicon base, several (only one shown in the figure) sensing electrodes 22, and a protective layer of earth material 2 1. There is a corresponding one of each sensing electrode 2 2 A sensing circuit: ^ also includes a signal processing and control circuit 2 1 B around the sensing element array (shown in Figure 4) 'Detailed sensing element array and peripheral circuit settings I to refer to the inventor of the patent for another A patent application (1) Patent application of the Republic of China = case number 091106806, the application date is April 3, 2002, and the name of the invention is

電谷式指紋讀取晶片」,暫准專利中。感測電極2 2係位 於石夕基材2 1上,並電連接至感測電路2丨a (從此感測電極2 2 以下包含感測電路2 1 A及信號處理及控制處理電路2 1 B及矽 基材2 1將統稱為基板結構2 9 )。保護層2 6覆蓋於基板結構 2 9上。因此,於本實施例中,基板結構2 9包含一矽基材2 j 及複數個感測電極22。矽基材21内含有複數個感測電路21 A"Electric Valley fingerprint reader chip", patent pending. The sensing electrode 2 2 is located on the Shixi substrate 21 and is electrically connected to the sensing circuit 2a. (From here on, the sensing electrode 2 2 includes the sensing circuit 2 1 A and the signal processing and control processing circuit 2 1 B. And the silicon substrate 21 will be collectively referred to as a substrate structure 2 9). The protective layer 26 covers the substrate structure 29. Therefore, in this embodiment, the substrate structure 29 includes a silicon substrate 2 j and a plurality of sensing electrodes 22. The silicon substrate 21 contains a plurality of sensing circuits 21 A

第12頁 200536096Page 12 200536096

及一#唬處理及控制電路2 1 β。複數個感測電極2 2以陣列排 列的方式形成於矽基材2 1上,分別對應於該等感測電路2l Α 並電連接至該等感測電路2 1 a。 保護層26由下而上依序包含第一至第三層26八至26(:。 第一層26A用以對該基板結構29提供一第一應力。第二層 2 6B用以對該基板結構29提供—第二應力。第三層2%用曰以 對該基板結構29提供一第三應力。And a # bluff processing and control circuit 2 1 β. A plurality of sensing electrodes 22 are formed on the silicon substrate 21 in an array arrangement, respectively corresponding to the sensing circuits 21A and electrically connected to the sensing circuits 21a. The protective layer 26 includes first to third layers 26 to 26 (: from the bottom to the top. The first layer 26A is used to provide a first stress to the substrate structure 29. The second layer 26B is used to the substrate The structure 29 provides a second stress. The third layer 2% is used to provide a third stress to the substrate structure 29.

^於一例子中,第一應力與第三應力同屬於一張應力, 而第二應力屬於一壓應力。亦即,藉由第一層26A與第三層 26C所提供的張應力來與第二層26β所提供的壓應力抵銷, 使得保護層26的熱殘留應力得以減少。於此情況下,第一 層2 6 A、與第;層2 6 G係由氮化;^、碳化⑨、類鑽碳材料與鑽 石材料之單一層或複合層所組成,而第二層26B係由二氧化 矽,組_成^。在本實施例中的第一至第三層之較佳組合為氮 1匕=/ 一氧化矽/氮化矽,導因為可以與商用積體電路製程 :降低製造的成本。同時在本實施例中二層氮化矽的 厚度可以不同以保留適當的應力結構。 於另一例子中’第一應力與第三應力同屬於壓應力,^ In an example, the first stress and the third stress belong to the same stress, and the second stress belongs to a compressive stress. That is, the tensile stress provided by the first layer 26A and the third layer 26C is used to offset the compressive stress provided by the second layer 26β, so that the thermal residual stress of the protective layer 26 can be reduced. In this case, the first layer 2 6 A, and the first layer 2 6 G are composed of a single layer or a composite layer of nitride; ⑨, hafnium carbide, diamond-like carbon material and diamond material, and the second layer 26B Department of silicon dioxide, group _ into ^. The preferred combination of the first to third layers in this embodiment is nitrogen 1 / silicon monoxide / silicon nitride, which can be combined with a commercial integrated circuit manufacturing process to reduce manufacturing costs. At the same time, the thickness of the two layers of silicon nitride in this embodiment may be different to maintain a proper stress structure. In another example, the first stress and the third stress are both compressive stresses.

而、一胃應力屬於張應力。亦即,藉由第一層26A與第三層 ft所提/共的壓應力來與第二層2 6β所提供的張應力抵銷, ^ 2知保/蔓層2 6的熱殘留應力得以減少。於此情況下,第二 】2^Β、/系由氮化石夕、碳化矽、類鑽碳材料或鑽石材料之單一 二或複合層所組成,而第一層2 6 Α與第三層26C係由二氧化 所、、且成。在本實施例中的第一至第三層之較佳組合為二However, a stomach stress is a tensile stress. That is, the compressive stresses provided by the first layer 26A and the third layer ft are used to offset the tensile stress provided by the second layer 2 6β, so that the thermal residual stress of the two layers can be obtained. cut back. In this case, the second] 2 ^ B, / is composed of a single two or composite layer of nitrided silicon, silicon carbide, diamond-like carbon material or diamond material, and the first layer 2 6 Α and the third layer 26C is made of dioxide. The preferred combination of the first to third layers in this embodiment is two

第13頁 200536096 五、發明說明(8) ^化=/氮化矽/二氧化矽,導因為可以與商用積體電路製 粒相谷,降低製造的成本。同時在本實施例中二層二氧化 矽的厚度可以不同以保留適當的應力結構。 ^藉由本發明之保護層之三明治構造,可以使得整個保 濩層之殘留應力降低,因此可以增加保護層之厚度,使得 其在機械強度(與厚度三次方成正比)方面,以及靜電防護 能力(承受電場強度與厚度二次方成正比)方面有相當良好 的效果。在本發明實施例中,保護層之厚度最佳為3〜5微米 ’例如本發明一較佳實施例依序為二氧化矽0 · 7 // m / 氮化矽2 // m /二氧化矽〇 · 2 // m ,由此可見機械強度將為習 知技術的1〜2 // m的至少3倍。同時,相較於商用積體電路 製程保護層厚度約為1微米,本發明實施例的靜電電場承受 可以增加至少8倍。 圖3係為圖1之電容感測元之第二實施例之局部側視示 意圖。如圖3所示,除了上述之三明治構造以外,保護層2 6 可以更包含屬於一咼分子材料層之一第四層Md,其乃塗敷 於該第三層2 6C上,以提供與一手指接觸之一斥水及斥油之 表面,藉以防止指紋殘留於其上。高分子材料層26D係由鐵 氟龍(Teflon)或類鐵氟龍化學結構材料所組成。或者,言 分子材料層26D係藉由使用一具有高分子單體的溶液而形@成 在第三層26C上’具有高分子單體的溶液具有一氟碳聚合體 端及一矽烷基之極性端。氟碳聚合體端係裸露於外,並具 有一柔軟片段之一氣礙南分子鍵’用以保護一 受於外部干擾’石夕院基之極性端係用以將高分子材料層_Page 13 200536096 V. Description of the invention (8) ^ = silicon nitride / silicon dioxide, because it can be granulated with commercial integrated circuits, reducing manufacturing costs. At the same time, the thickness of the two-layer silicon dioxide in this embodiment may be different to maintain a proper stress structure. ^ With the sandwich structure of the protective layer of the present invention, the residual stress of the entire protective layer can be reduced, so the thickness of the protective layer can be increased, so that its mechanical strength (which is proportional to the cube of the thickness) and electrostatic protection ability ( Withstand the electric field strength is proportional to the square of the thickness) has a very good effect. In the embodiment of the present invention, the thickness of the protective layer is preferably 3 to 5 μm. For example, in a preferred embodiment of the present invention, the order is silicon dioxide 0 · 7 // m / silicon nitride 2 // m / dioxide Silicon 0 · 2 // m, which shows that the mechanical strength will be at least 3 times that of the conventional technology 1 ~ 2 // m. At the same time, compared with the thickness of the protective layer of the commercial integrated circuit manufacturing process is about 1 micron, the electrostatic field withstand of the embodiment of the present invention can be increased by at least 8 times. FIG. 3 is a schematic partial side view of the second embodiment of the capacitive sensing element of FIG. 1. FIG. As shown in FIG. 3, in addition to the sandwich structure described above, the protective layer 26 may further include a fourth layer Md, which is one of the molecular material layers, which is coated on the third layer 26C to provide a Fingers touch one of the water and oil repellent surfaces to prevent fingerprints from remaining on them. The polymer material layer 26D is composed of Teflon or Teflon-like chemical structural material. Alternatively, the molecular material layer 26D is formed by using a solution having a polymer monomer on the third layer 26C. The solution having a polymer monomer has a fluorocarbon polymer end and a silane group polarity. end. The fluorocarbon polymer end is exposed to the outside and has a soft segment that blocks the South molecular bond ’to protect a polar end of the Shi Xiyuan's base from the external interference’.

200536096 五、發明說明(9) 牙心口 T疋於^亥第二層2 6 C上。於另一實施例中,第四層2 6 D 可以=陶瓷原子層(ceramic at〇mic ,譬如是氧化 :與乳化鈦^,以形成同樣的斥水及斥油之表面(請參見中 華民國專利申請案序號092124697,申請日為2〇〇3年9月8 日,發明名稱為「能防止指紋殘留之電容式指紋感測器及 其處理方法」及中華民國專利申請案序號〇 92 1 3 248 〇, 日為2 0 03年11月20日,發明名稱為「晶片裝置的表面處理 方法及使用該方法所形成之晶片裝置」)。200536096 V. Description of the invention (9) Tooth mouth T is located on 2 6 C on the second floor of Haihe. In another embodiment, the fourth layer 2 6 D may be a ceramic atomic layer (ceramic at 0mic, for example, oxidation: and emulsified titanium ^ to form the same water and oil repellent surface (see the Republic of China patent The application number is 092124697, the application date is September 8, 2003, and the invention name is "Capacitive fingerprint sensor capable of preventing fingerprint residue and its processing method" and the Republic of China Patent Application No. 92 1 3 248 〇, date is November 20, 2003, and the invention name is "Surface treatment method of wafer device and wafer device formed by using this method").

除了上述藉由應力補償設計的保護層結構可以大幅增 加耐壓強度及靜電破壞防護外,為了更進一步增加本發^ ,片式指紋感測器的靜電防護,請參見圖4,其係為靜X電防 護=另一實施例。圖4顯示圖3之電容式指紋感測器之剖視 示意圖。如圖4所示,本發明之電容式指紋感測器2基本上 包含一内含複數個感測電路及一信號處理及控制電路的矽 基材2 1、屬於感測電極之複數個平板電極2 2、一金屬網 2 3、複數個靜電放電單元2 4、複數個焊墊2 5及一保護層 26。於本實施例中,基板結構29可以被視為包含矽基材 21、平板電極22、金屬網23、靜電放電單元24及焊墊25。 該等平板電極2 2係以陣列排列的方式形成於該矽基材2 1 上。金屬網2 3係形成於該等平板電極2 2之間,並與該等平 板電極22齊平,且包圍各該平板電極22。詳言之,金屬網 2 3係縱橫地穿設於該等平板電極2 2之間隙中。各該平板電 極2 2與該金屬網2 3隔開一預定之間距。該等焊墊2 5係作為 戎電容式指紋感測器2之輸入與輸出部分。該金屬網2 3連接In addition to the protective layer structure designed above by stress compensation, which can greatly increase the compressive strength and protection against electrostatic damage, in order to further increase the present ^, the electrostatic protection of the chip fingerprint sensor, please refer to Figure 4, which is static X electric protection = another embodiment. FIG. 4 is a schematic cross-sectional view of the capacitive fingerprint sensor of FIG. 3. As shown in FIG. 4, the capacitive fingerprint sensor 2 of the present invention basically includes a silicon substrate 2 containing a plurality of sensing circuits and a signal processing and control circuit. 1. A plurality of flat electrodes belonging to the sensing electrodes. 2 2. A metal net 2 3. A plurality of electrostatic discharge cells 2 4. A plurality of welding pads 25 and a protective layer 26. In this embodiment, the substrate structure 29 can be regarded as including a silicon substrate 21, a plate electrode 22, a metal mesh 23, an electrostatic discharge unit 24, and a bonding pad 25. The flat electrodes 2 2 are formed on the silicon substrate 2 1 in an array arrangement. The metal mesh 23 is formed between the flat electrodes 22 and is flush with the flat electrodes 22 and surrounds each of the flat electrodes 22. In detail, the metal meshes 2 3 are arranged vertically and horizontally in the gaps between the flat electrodes 22. Each of the plate electrodes 22 and the metal mesh 2 3 are separated by a predetermined distance. These pads 25 are used as the input and output parts of the Rong capacitive fingerprint sensor 2. The metal mesh 2 3 connections

第15頁 200536096 五、發明說明(10) 至一接地端GND,主要是要將靜電導引至接地端GND,避免 感測器遭受到靜電破壞。該等靜電放電單元24係與該金屬 網23連接,進而連接至接地端。相鄰之靜電放電單元η之 距離D遠大於相鄰之平板電極2 2之間距,所以該等靜電放電 單元2 4之數目遠小於該等平板電極2 2之數目。 保護層2 6係完全覆蓋於該等平板電極2 2及該金屬網 23 ’並局部覆蓋於該等靜電放電單元24及該等焊墊25之 上。違保護層2 6係於该等靜電放電單元2 4上形成複數之第 一開口27,並於該等焊墊25之上形成複數之第二開口28。 值得注意的是,各該第一開口 2 7之尺寸遠小於各該第二開 口 28之尺寸。 圖5顯示圖4之局部剖視示意圖。圖6顯示圖4之焊墊之 放大示意圖。如圖5與6所示,鋁金屬疊層3〇包含位於該基 板21上之一鈦層51,位於該鈦層51上之一鋁合金層52,^ 位於邊鋁合金層52上之一氮化鈦層53。鋁合金層52係由各 該第一開口27露出。各焊墊25包含位於該基板21上之一鈦 層51,位於該鈦層51上且由各該第二開口28露出之一鋁合 金層52,及位於該鋁合金層52上且圍繞各該第二開口28二 二氮化鈦層53。值得注意的是,由於蝕刻製程之特性,使 得在各該第一開口 2 7中之該氮化鈦層5 3之一中間厚度τ丨小 於該氮化鈦層53之一周邊厚度T2,而位在各該第二開口 28 中之氮化鈦層53實質上完全會被移除。 +圖7顯示圖4之電容式指紋感測器之局部俯視示意圖。 沿者圖7之線4-4即可得到如圖4所示之側視圖。從圖7可以Page 15 200536096 V. Description of the invention (10) To a ground terminal GND, the main purpose is to guide static electricity to the ground terminal GND to prevent the sensor from being damaged by static electricity. The electrostatic discharge cells 24 are connected to the metal net 23 and further connected to the ground terminal. The distance D between adjacent electrostatic discharge cells η is much larger than the distance between adjacent plate electrodes 22, so the number of these electrostatic discharge cells 24 is much smaller than the number of plate electrodes 22. The protective layer 26 is completely covered on the flat electrodes 22 and the metal mesh 23 'and is partially covered on the electrostatic discharge cells 24 and the solder pads 25. The non-protective layer 2 6 forms a plurality of first openings 27 on the electrostatic discharge cells 24 and a plurality of second openings 28 on the pads 25. It is worth noting that the size of each of the first openings 27 is much smaller than the size of each of the second openings 28. FIG. 5 is a schematic partial cross-sectional view of FIG. 4. FIG. 6 shows an enlarged schematic view of the bonding pad of FIG. 4. As shown in FIGS. 5 and 6, the aluminum metal stack 30 includes a titanium layer 51 on the substrate 21, an aluminum alloy layer 52 on the titanium layer 51, and a nitrogen layer on the side aluminum alloy layer 52.化 titanium layer 53. The aluminum alloy layer 52 is exposed through each of the first openings 27. Each bonding pad 25 includes a titanium layer 51 on the substrate 21, an aluminum alloy layer 52 on the titanium layer 51 and exposed through the second openings 28, and on the aluminum alloy layer 52 and surrounding each of the The second opening 28 is a titanium nitride layer 53. It is worth noting that due to the characteristics of the etching process, an intermediate thickness τ 丨 of the titanium nitride layer 53 in each of the first openings 27 is smaller than a peripheral thickness T2 of the titanium nitride layer 53. The titanium nitride layer 53 in each of the second openings 28 is substantially completely removed. + FIG. 7 shows a partial top view of the capacitive fingerprint sensor of FIG. 4. Follow the line 4-4 in Figure 7 to get the side view shown in Figure 4. From Figure 7 you can

第16頁 200536096 五、發明說明(11) 清楚看出,為了製作靜電放電單元2 4,本發明在不影響感 測效果之情況下犧牲掉某些平板電極之感測面積。所以, 該等平板電極22包含複數個犧牲電極22S及複數個標準電極 22N,該等犧牲電極22S係與該等靜電放電單元24鄰接,且 各該犧牲電極22S之尺寸小於各該標準電極22N之尺寸。於 本實施例中,各該靜電放電單元24係僅與一個犧牲電極22S 鄰接。所以在九個平板電極22中,只有一個犧牲電極2 2S。 平板電極2 2與金屬網2 3可以是由相同之材料所製造 成。舉例而言,平板電極22與金屬網23可以是積體電路製 粒中的最頂層之金屬薄膜,如鋁金屬疊層3〇或銅金屬疊 層。於本實施例中,平板電極22之面積約為4〇微米*4〇微 米,電容式感測元2 0之面積為5 〇微米* 5 0微米,平板電極2 2 與手指1間形成感測電容,而金屬網2 3係作為靜電防護用。 當手指靠近感測器時,靜電可以從第一開口 2 7經由金 屬網23而流向接地端GND。於本實施例中,二個相鄰之靜電 放電單元24的最佳化間距D為5〇〇至1〇〇〇微米。 、圖8顯示依據本發明第三實施例之電容式指紋感測器之 俯視不意圖。圖8之感測器係與圖7類似,不同之處在於圖8 之各忒靜電放電單兀24係僅與兩個犧牲電極2 2S鄰接。亦 即γ兩個鄰接之平板電極22各犧牲掉一個區域來供靜電放 電單元24使用。 、圖9顯示依據本發明第四實施例之電容式指紋感測器之 俯視不意目。圖9之感測器係與圖7類似,不同之處在於圖9 之各該靜電放電單元24係僅與四個犧牲電極22S鄰接。亦 200536096 五、發明說明(12) 即’四個鄰接之平板電極2 2各犧牲掉一個區域來供靜電放 電單元24使用。 藉由上述構造’供靜電放電單元24使用之第一開口27 係與供焊墊25使用之第二開口28係設計於同一道光罩中, 但其尺寸則有相當大差距。舉例而言,第一開口 2 7之尺寸 通常為5至10微米,而第二開口 28之尺寸通常為1〇〇至15〇微 米。所以,故在開口形成之過程中,不僅可以完全去除保 4層2 6而形成第二開口 2 8,最上面的氮化鈦層5 3亦可以完 王被,除而使鋁合金層5 2完全裸露出,以利後續的打線動 作…、^本項技藝者應可輕易理解到,形成開口所使用的 ^式蝕刻方式皆有負載效應(loading effect),也就是 2巧:車:小者蝕刻速度較慢。本發明即是利用這-特 5 #^ ^^ -271^ 耐腐:、^入度約為〇· 1微米)°由於氮化欽層53不易氧化, 之長期使用、適合暴露於空氣中。如此,靠近 感測的之物體的靜電便 及銘合金層52連線由第一開口27、氣化鈦層53 且本發明採用的金屬地端,藉以避免靜電破壞。並 用積體電路製程,係利=及製造程序完全等同於任何商 完成感測電極及靜ΐS3層的銘或者銅金屬製程同時 與製造流程不相容她5;屬網。可以免除上述習知技術 ,合及材枓不相容的問題。 習知技術之:不需要使用具有高複雜度之前述 程及材料來製造本用積體電路工廠的標準流Page 16 200536096 V. Description of the invention (11) It is clear that in order to make the electrostatic discharge unit 24, the present invention sacrifice the sensing area of some flat electrodes without affecting the sensing effect. Therefore, the flat electrodes 22 include a plurality of sacrificial electrodes 22S and a plurality of standard electrodes 22N. The sacrificial electrodes 22S are adjacent to the electrostatic discharge cells 24, and the size of each of the sacrificial electrodes 22S is smaller than that of each of the standard electrodes 22N. size. In this embodiment, each of the electrostatic discharge cells 24 is adjacent to only one sacrificial electrode 22S. Therefore, among the nine plate electrodes 22, there is only one sacrificial electrode 22S. The plate electrode 22 and the metal mesh 23 may be made of the same material. For example, the plate electrode 22 and the metal mesh 23 may be the topmost metal film in the integrated circuit granulation, such as an aluminum metal laminate 30 or a copper metal laminate. In this embodiment, the area of the flat electrode 22 is about 40 microns * 40 microns, the area of the capacitive sensing element 20 is 50 microns * 50 microns, and sensing is formed between the flat electrode 2 2 and the finger 1. Capacitors, and metal meshes 2 and 3 are used for electrostatic protection. When a finger approaches the sensor, static electricity can flow from the first opening 27 to the ground terminal GND through the metal net 23. In this embodiment, the optimized distance D between two adjacent electrostatic discharge cells 24 is 5,000 to 10,000 microns. Fig. 8 shows a plan view of a capacitive fingerprint sensor according to a third embodiment of the present invention. The sensor system of FIG. 8 is similar to FIG. 7 except that each of the electrostatic discharge units 24 of FIG. 8 is adjacent to only two sacrificial electrodes 22S. That is, two adjacent plate electrodes 22 of? Are sacrificed one area each for use by the electrostatic discharge unit 24. Fig. 9 shows an unintended plan view of a capacitive fingerprint sensor according to a fourth embodiment of the present invention. The sensor of FIG. 9 is similar to that of FIG. 7 except that each of the electrostatic discharge cells 24 of FIG. 9 is adjacent to only four sacrificial electrodes 22S. Also 200536096 V. Description of the invention (12) That is, each of the four adjacent plate electrodes 22 is sacrificed an area for the electrostatic discharge unit 24 to use. With the above configuration, the first opening 27 for the electrostatic discharge unit 24 and the second opening 28 for the pad 25 are designed in the same mask, but there is a considerable difference in size. For example, the size of the first opening 27 is usually 5 to 10 micrometers, and the size of the second opening 28 is usually 100 to 150 micrometers. Therefore, during the formation of the openings, not only the 4 layers 2 6 can be completely removed to form the second openings 2 8, but the uppermost titanium nitride layer 5 3 can also be finished and the aluminum alloy layer 5 2 can be removed. Fully exposed to facilitate subsequent wire-making actions ..., ^ This artist should easily understand that the ^ -etching methods used to form the openings all have a loading effect, that is, 2 clever: car: small Etching speed is slow. The present invention utilizes this feature- # 5 ^ ^^ -271 ^ Corrosion resistance: the penetration degree is about 0.1 micron) ° Since the nitride layer 53 is not easy to oxidize, it is suitable for long-term use and is suitable for exposure to the air. In this way, the static electricity near the object being sensed is connected to the metal alloy layer 52 through the first opening 27, the vaporized titanium layer 53, and the metal ground terminal used in the present invention to avoid electrostatic damage. The integrated circuit manufacturing process is used, and the manufacturing process is completely the same as that of any manufacturer who completes the inscription of the sensing electrode and the static S3 layer or the copper metal process. It is also incompatible with the manufacturing process. Can eliminate the above-mentioned conventional technology, the problem of incompatible materials. Known technology: It is not necessary to use the aforementioned processes and materials with high complexity to manufacture the standard flow of this integrated circuit factory

第18頁 200536096 五、發明說明(13) 本發明優點不僅在於ESD防護能力,同時僅利用長間距 之少數靜電放電單元便可以完成ESD防護,即使使用後有殘 污,大部分殘污也是獨立的,並不與金屬網2 3連接,減少 了許多殘污電容對影像所造成的干擾。 在較佳實施例之詳細說明中所提出之具體實施例僅用 以方便說明本發明之技術内容,而非將本發明狹義地限制 於上述實施例,在不超出本發明之精神及以下申請專利範 圍之情況,所做之種種變化實施,皆屬於本發明之範圍。Page 18 200536096 V. Explanation of the invention (13) The advantages of the present invention are not only the ESD protection capability, but also the ESD protection can be completed by using only a few electrostatic discharge cells with a long distance. It is not connected to the metal mesh 23, which reduces the interference caused by many residual capacitors on the image. The specific embodiments proposed in the detailed description of the preferred embodiments are only used to facilitate the description of the technical content of the present invention, rather than to limit the present invention to the above embodiments in a narrow sense, without exceeding the spirit of the present invention and the following patent applications The scope of the scope and the various changes made are all within the scope of the present invention.

第19頁 200536096 圖式簡單說明 圖1顯示利用本發明之電容式指紋感測器來讀取手指指 紋之示意圖。 圖2係為圖1之電容感測元之第一實施例之局部側視示 意圖。 圖3係為圖1之電容感測元之第二實施例之局部側視示 意圖。 圖4顯示圖3之電容式指紋感測器之剖視示意圖。 圖5顯不圖4之局部剖視不意圖。 圖6顯示圖4之焊墊之放大示意圖。 圖7顯示圖4之電容式指紋感測器之局部俯視示意圖。 圖8顯示依據本發明第三實施例之電容式指紋感測器之 俯視不意圖。 圖9顯示依據本發明第四實施例之電容式指紋感測器之 俯視不意圖。 元件代表符號說明] T1〜中間厚度 GND〜接地端 1〜手指 1 1〜紋峰 2 0〜電容式感測元 2 1 A〜感測電路 2 2〜平板電極(感測電極) 22S〜犧牲電極 T2〜周邊厚度 D〜間距 2〜指紋感測器 1 1 a〜電容值曲線 2 1〜矽基材 2 1 B〜信號處理及控制電路 22N〜標準電極 2 3〜金屬網Page 19 200536096 Brief Description of Drawings Figure 1 shows a schematic diagram of reading fingerprints using a capacitive fingerprint sensor of the present invention. FIG. 2 is a schematic partial side view of the first embodiment of the capacitive sensing element of FIG. 1. FIG. FIG. 3 is a schematic partial side view of the second embodiment of the capacitive sensing element of FIG. 1. FIG. FIG. 4 is a schematic cross-sectional view of the capacitive fingerprint sensor of FIG. 3. FIG. 5 shows a partial cross-sectional view of FIG. 4. FIG. 6 shows an enlarged schematic view of the bonding pad of FIG. 4. FIG. 7 is a partial top view of the capacitive fingerprint sensor of FIG. 4. FIG. 8 shows a plan view of a capacitive fingerprint sensor according to a third embodiment of the present invention. FIG. 9 shows a plan view of a capacitive fingerprint sensor according to a fourth embodiment of the present invention. Description of Symbols of Components] T1 ~ Intermediate thickness GND ~ Ground terminal 1 ~ Finger 1 1 ~ Wave peak 2 0 ~ Capacitive sensing element 2 1 A ~ Sensing circuit 2 2 ~ Flat electrode (sensing electrode) 22S ~ Sacrificial electrode T2 ~ peripheral thickness D ~ pitch 2 ~ fingerprint sensor 1 1 a ~ capacitance curve 2 1 ~ silicon substrate 2 1 B ~ signal processing and control circuit 22N ~ standard electrode 2 3 ~ metal mesh

第20頁 200536096 圖式簡單說明 2 5〜焊墊 26A〜第一層 260第三層 2 7〜第一開口 2 9〜基板結構 5 1〜鈦層 24〜靜電放電單元 2 6〜保護層 26B〜第二層 2 6 D〜第四層 2 8〜第二開口 30〜铭金屬疊層 5 2〜銘合金層 5 3〜氮化鈦層Page 20 200536096 Brief description of the drawings 2 5 ~ pad 26A ~ first layer 260 third layer 2 7 ~ first opening 2 9 ~ substrate structure 5 1 ~ titanium layer 24 ~ electrostatic discharge unit 2 6 ~ protective layer 26B ~ Second layer 2 6 D ~ Fourth layer 2 8 ~ Second opening 30 ~ Ming metal stack 5 2 ~ Ming alloy layer 5 3 ~ Titanium nitride layer

第21頁Page 21

Claims (1)

200536096 六、申請專利範圍 1. 一種可抗靜電與應力破壞及防殘污干擾之晶片式感 測器,包含: 一基板結構;及 一保護層,覆蓋於該基板結構上,該保護層由下而上 依序包含: 一第一層,用以對該基板結構提供一第一應力; 一第二層,用以對該基板結構提供一第二應力;及 一第三層,用以對該基板結構提供一第三應力,其 中該第一應力與該第三應力同屬於一張應力與一壓應力兩 者之其一者,而該第二應力屬於該張應力與該壓應力兩者 之另一者。 2. 如申請專利範圍第1項所述之可抗靜電與應力破壞 及防殘污干擾之晶片式感測器,其中該第一層與該第三層 係由二氧化矽所組成,而該第二層係由氮化矽、碳化矽、 類鑽碳材料與鑽石材料之單一層或複合層所組成。 3. 如申請專利範圍第1項所述之可抗靜電與應力破壞 及防殘污干擾之晶片式感測器,其中該第二層係由二氧化 矽所組成,而該第一層與該第三層係由氮化矽、碳化矽、 類鑽碳材料與鑽石材料之單一層或複合層所組成。 4. 如申請專利範圍第1項所述之可抗靜電與應力破壞 及防殘污干擾之晶片式感測器,其中該保護層更包含: 一高分子材料層或陶瓷原子層,塗敷於該第三層上, 以提供與一手指接觸之一斥水及斥油之表面,藉以防止指 紋殘留於其上。200536096 6. Scope of patent application 1. A wafer-type sensor capable of resisting static electricity, stress damage and anti-fouling interference, including: a substrate structure; and a protective layer covering the substrate structure, the protective layer is The above sequence includes: a first layer to provide a first stress to the substrate structure; a second layer to provide a second stress to the substrate structure; and a third layer to apply a first stress to the substrate structure; The substrate structure provides a third stress, wherein the first stress and the third stress belong to one of a sheet stress and a compressive stress, and the second stress belongs to both the tensile stress and the compressive stress. The other. 2. The chip-type sensor capable of resisting static electricity, stress damage and anti-fouling interference as described in item 1 of the scope of patent application, wherein the first layer and the third layer are composed of silicon dioxide, and the The second layer is composed of a single layer or a composite layer of silicon nitride, silicon carbide, diamond-like carbon material and diamond material. 3. The chip-type sensor capable of resisting static electricity, stress damage and anti-fouling interference as described in item 1 of the scope of patent application, wherein the second layer is composed of silicon dioxide, and the first layer and the The third layer is composed of a single layer or a composite layer of silicon nitride, silicon carbide, diamond-like carbon material and diamond material. 4. The chip-type sensor capable of resisting static electricity, stress damage and anti-fouling interference as described in item 1 of the scope of patent application, wherein the protective layer further comprises: a polymer material layer or a ceramic atomic layer, which is coated on The third layer is provided with a water-repellent and oil-repellent surface in contact with a finger, thereby preventing fingerprints from remaining thereon. 第22頁 200536096 六、申請專利範圍 5. 如申請專利範圍第4項所述之可抗靜電與應力破壞 及防殘污干擾之晶片式感測器,其中該高分子材料層係由 鐵氟龍(T e f 1 ◦ η )或類鐵氟龍化學結構材料所組成。 6. 如申請專利範圍第4項所述之可抗靜電與應力破壞 及防殘污干擾之晶片式感測器,其中該高分子材料層係藉 由使用一具有高分子單體的溶液而形成在該第三層上,該 具有高分子單體的溶液具有一氟碳聚合體端及一矽烷基之 極性端,該氟碳聚合體端係裸露於外,用以保護一積體電 路免受於外部干擾,該矽烷基之極性端係用以將該高分子 材料層穩固固定於該第三層上。 7. 如申請專利範圍第6項所述之可抗靜電與應力破壞 及防殘污干擾之晶片式感測器,其中該氟碳聚合體端具有 一柔軟片段之一氟碳高分子鍵。 8. 如申請專利範圍第4項所述之可抗靜電與應力破壞 及防殘污干擾之晶片式感測器,其中該陶瓷原子層係為一 氧化紹層或一氧化鈦層。 9. 如申請專利範圍第1項所述之可抗靜電與應力破壞 及防殘污干擾之晶片式感測器,其中該保護層之厚度大於2 微米。 10. 如申請專利範圍第1項所述之可抗靜電與應力破壞 及防殘污干擾之晶片式感測器,其中該保護層之厚度為3至 5微米。 11. 如申請專利範圍第1項所述之可抗靜電與應力破壞 及防殘污干擾之晶片式感測器,其中該基板結構包含:Page 22, 200536096 6. Scope of patent application 5. As described in item 4 of the scope of patent application, a chip-type sensor capable of resisting static electricity and stress damage and preventing interference from interference, wherein the polymer material layer is made of Teflon (T ef 1 ◦ η) or Teflon-like chemical structural materials. 6. The chip-type sensor capable of resisting static electricity, stress damage, and anti-fouling interference as described in item 4 of the scope of patent application, wherein the polymer material layer is formed by using a solution having a polymer monomer On the third layer, the polymer monomer-containing solution has a fluorocarbon polymer end and a silane-based polar end, and the fluorocarbon polymer end is exposed to protect an integrated circuit from For external interference, the polar end of the silane group is used to firmly fix the polymer material layer on the third layer. 7. The chip-type sensor capable of resisting static electricity and stress damage and preventing interference from residues as described in item 6 of the scope of the patent application, wherein the fluorocarbon polymer end has a fluorocarbon polymer bond which is a soft segment. 8. The chip-type sensor capable of resisting static electricity, stress damage and anti-fouling interference as described in item 4 of the scope of patent application, wherein the ceramic atomic layer is a oxide layer or a titanium oxide layer. 9. The chip-type sensor capable of resisting static electricity, stress damage and anti-fouling interference as described in item 1 of the scope of patent application, wherein the thickness of the protective layer is greater than 2 microns. 10. The chip-type sensor capable of resisting static electricity, stress damage and anti-fouling interference as described in item 1 of the scope of patent application, wherein the thickness of the protective layer is 3 to 5 microns. 11. The chip-type sensor capable of resisting static electricity, stress damage and anti-fouling interference as described in item 1 of the scope of patent application, wherein the substrate structure includes: 第23頁 200536096 六、申請專利範圍 一矽基材,内含有複數個感測電路;及 複數個感測電極,以陣列排列的方式形成於該矽基材 上,分別對應於該等感測電路並電連接至該等感測電路。 12. 如申請專利範圍第1 1項所述之可抗靜電與應力破 壞及防殘污干擾之晶片式感測器,其中該基板結構更包 含: 一金屬網,縱橫地穿設於該等感測電極之間並與該等 感測電極齊平,且包圍各該感測電極,該金屬網連接至一 接地端,該保護層係完全覆蓋於該金屬網上。 13. 如申請專利範圍第1 2項所述之可抗靜電與應力破 壞及防殘污干擾之晶片式感測器,其中該基板結構更包 含: 複數個靜電放電單元,與該金屬網連接,並形成於該 等感測電極中之預定數目之相鄰之感測電極之間,該等靜 電放電單元之數目小於該等感測電極之數目,該保護層係 局部覆蓋於該等靜電放電單元上。 14. 如申請專利範圍第1 3項所述之可抗靜電與應力破 壞及防殘污干擾之晶片式感測器,其中該基板結構更包 含: 複數個焊墊,作為該晶片式感測器之輸入與輸出部 分,該保護層係局部覆蓋於該等焊墊之上,藉以於該等靜 電放電單元上形成複數之第一開口,並於該等焊墊之上形 成複數之第二開口,各該第一開口之尺寸小於各該第二開 口之尺寸Page 23 200536096 VI. Patent application scope-a silicon substrate containing a plurality of sensing circuits; and a plurality of sensing electrodes formed on the silicon substrate in an array arrangement corresponding to the sensing circuits respectively And is electrically connected to the sensing circuits. 12. The chip-type sensor capable of resisting static electricity, stress damage, and anti-fouling interference as described in item 11 of the scope of the patent application, wherein the substrate structure further includes: a metal mesh running across the sensors horizontally and vertically. Between the measuring electrodes and flush with the sensing electrodes and surrounding each of the sensing electrodes, the metal mesh is connected to a ground terminal, and the protective layer is completely covered on the metal mesh. 13. The chip-type sensor capable of resisting static electricity, stress damage, and anti-fouling interference as described in item 12 of the scope of the patent application, wherein the substrate structure further includes: a plurality of electrostatic discharge cells connected to the metal mesh, And formed between a predetermined number of adjacent sensing electrodes among the sensing electrodes, the number of the electrostatic discharge cells is less than the number of the sensing electrodes, and the protective layer is partially covered by the electrostatic discharge cells on. 14. The chip-type sensor capable of resisting static electricity, stress damage and anti-fouling interference as described in item 13 of the scope of patent application, wherein the substrate structure further includes: a plurality of solder pads as the chip-type sensor For the input and output parts, the protective layer is partially covered on the pads, so that a plurality of first openings are formed on the electrostatic discharge cells, and a plurality of second openings are formed on the pads. The size of each of the first openings is smaller than the size of each of the second openings 第24頁 200536096 六、申請專利範圍 15. 如申請專利範圍第1 3項所述之可抗靜電與應力破 壞及防殘污干擾之晶片式感測器,其中二個相鄰之靜電放 電單元的間距實質上在5 0 0至1 0 0 0微米之間。 16. 如申請專利範圍第1 1項所述之可抗靜電與應力破 壞及防殘污干擾之晶片式感測器,其中該等感測電極包含 複數個犧牲電極及複數個標準電極,該等犧牲電極係與該 等靜電放電單元鄰接,且各該犧牲電極之尺寸小於各該標 準電極之尺寸。Page 24 200536096 6. Scope of patent application 15. As described in item 13 of the scope of patent application, the chip-type sensor can resist static and stress damage and prevent interference from interference, two of which are adjacent electrostatic discharge cells. The pitch is substantially between 500 and 100 microns. 16. The chip-type sensor capable of resisting static electricity, stress damage and anti-fouling interference as described in item 11 of the scope of patent application, wherein the sensing electrodes include a plurality of sacrificial electrodes and a plurality of standard electrodes, and The sacrificial electrodes are adjacent to the electrostatic discharge cells, and the size of each of the sacrificial electrodes is smaller than that of each of the standard electrodes. 第25頁Page 25
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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI578414B (en) * 2016-05-26 2017-04-11 旭景科技股份有限公司 Method for packaging fingerprint sensing chip and fingerprint sensing module made using the same
TWI608425B (en) * 2013-09-10 2017-12-11 映智科技股份有限公司 Finger detecting method and device of fingerprint recognition integrated circuit
CN107526996A (en) * 2016-06-21 2017-12-29 旭景科技股份有限公司 Fingerprint sensing chip method for packing and utilize its manufactured fingerprint sensing module
CN112582253A (en) * 2019-09-30 2021-03-30 长鑫存储技术有限公司 Method for improving internal stress of semiconductor device and semiconductor device

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI608425B (en) * 2013-09-10 2017-12-11 映智科技股份有限公司 Finger detecting method and device of fingerprint recognition integrated circuit
TWI578414B (en) * 2016-05-26 2017-04-11 旭景科技股份有限公司 Method for packaging fingerprint sensing chip and fingerprint sensing module made using the same
CN107526996A (en) * 2016-06-21 2017-12-29 旭景科技股份有限公司 Fingerprint sensing chip method for packing and utilize its manufactured fingerprint sensing module
CN112582253A (en) * 2019-09-30 2021-03-30 长鑫存储技术有限公司 Method for improving internal stress of semiconductor device and semiconductor device
CN112582253B (en) * 2019-09-30 2022-03-22 长鑫存储技术有限公司 Method for improving internal stress of semiconductor device and semiconductor device

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