TW200535622A - Interference and system for transporting real-time data - Google Patents

Abstract

An interference for transporting real-time data is applied to a nonreal-time data transported by real-time transporting, and to a real-time data transported by nonreal-time transporting. The present invention has a nonreal-time data interference unit for receiving/transporting nonreal-time data, and an IO unit coupled to the nonreal-time data interference. In addition, the present invention further comprises a memory unit and a network interference control (NIC) unit. Wherein, the memory unit is used to store the nonreal-time data and the real-time data. The NIC unit is coupled to the memory unit for receiving/transporting the real-time data.

Description

200535622 1) It belongs to the non-technical platoon, and the assets are in flow ^ (The issued customs bank technical flow system, yc number Huiming originally had the letter C of the predecessor system, and if it is sent, it is first made with the US system ^ [别Data t position (B control plan to send the letter is also the case when the WS is passed, when the military relays the brain, such as do, the material is included. Such materials such as electricity are transmitted. Examples of the 111 transfer of funds make Ming due to a case of delivery. Yes. For example, the technical field of sending and receiving the master's example in the system window] is about a real-time data transmission interface and system, and a special method for real-time transmission of non-real-time data and real-time transmission Real-time data transmission interface and system.] Is a transmission path composed of a set of wires used to transmit data between the unit or the system and the system. These wires include material lines and control lines, which are used in each In the bus cycle), addresses, data and components and systems, or systems and systems are transmitted separately according to the bus protocol. There are also many types of buses. Among them, ANC buses are high-speed / real-time buses. Its data transmission rate is 4MHz, which is mainly 16-bit parallel transmission. ANC confluence It is used to connect the real-time signal processing device of the system to the host computer. It is used to number the real-time data generated by the processing device to the host computer, and the real-time data must be passed to the real-time signal processing device. However, the host computer may be non-real-time transmission. When a computer-based radar system performs a self-test, it uses a host computer, for example, as the operating software. When the host computer is a non-computer system, the real-time signal processing device will run out of time, or the signal processing device will not operate normally when an error occurs that the data is not transmitted in accordance with the data sequence. f] The purpose of the present invention is to provide a real-time data transmission interface

13353twf.ptd Page 7 200535622 V. Description of the invention (2) In the aspect, non-real-time data can be transmitted in real time, and real-time data can be transmitted in non-real time. Another object of the present invention is to provide a real-time data transmission system, which can connect a non-real-time host computer with a real-time signal processing device, and can transfer data to each other without errors. An object of the present invention is to provide an interface for real-time data transmission, which is suitable for real-time transmission of non-real-time data and non-immediate transmission of real-time data. The real-time data transmission interface of the present invention includes a non-real-time data interface unit for receiving / transmitting non-real-time data, and an input-output unit coupled to the non-real-time data interface unit, wherein the input-output unit is used as the non-real-time data and real-time data. Transmission interface. In addition, the present invention also includes a memory unit and a network interface control unit, wherein the memory unit is coupled to the gastric output unit and used to store non-real-time data and real-time data. The network interface control unit is coupled to the memory unit, which is used to receive / transmit real-time data. In the embodiment of the present invention, the non-real-time data interface unit includes a bus interface unit, which serves as an interface for non-real-time data input / output. In addition, the non-real-time data interface unit also includes a data output latch (Latch), a data input latch, and a control signal latch, all of which are coupled to the bus interface unit through the internal data bus. In addition, the non-real-time data interface unit further includes a buffer and a flag register. The buffer is coupled to the bus interface unit through an internal data bus. The flag + register is coupled to the buffer, which is used to store the flag status. In a better case, the non-real-time data interface unit also includes a clock generator for generating

13353twf.ptd Page 8 200535622 V. Description of the invention (3) Clock signal to other units, and the frequency of the clock signal is 10 Μ Η z. In addition, the input / output unit includes a control logic unit, which causes the input / output unit to perform a read / write operation according to an external control signal. The input-output unit also includes a check circuit, a data output latch and a data input latch, all of which are coupled to the control logic unit. Among them, when a self-test mode is started, the control logic unit controls the inspection circuit to check the correctness of the data output by the input and output units, and generates a check result. In addition, the memory unit includes a control logic unit, which controls the operation of the memory unit according to an external control signal. In addition, the memory unit includes a first address counter, a first memory, and a first buffer latch unit. Among them, the first address counter is coupled to the control logic unit and is used to provide a || bit address to the first memory. The first memory is used to store non-real-time data, and the first memory is coupled to the first buffer latch unit through an internal data bus. In the embodiment of the present invention, the memory unit is further configured with a second address counter, a second memory, and a second buffer latch unit. In a better case, the network interface control unit includes a programmable interface controller and a TTL / differential level conversion interface. The TTL / differential level conversion interface is used to convert real-time data between the TTL type and the differential type, and temporarily store the real-time data. In addition, the program interface controller includes a storage device and a sequencer, and a micro program is stored in the storage device to control the operation of the program interface controller. The sequencer is coupled to the storage device, + to execute the instructions of the microprogram, and will adjust the execution order according to external conditions. And the programming interface controller also includes condition selector and event / interrupt

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In order to make the present invention and other objects, features and advantages more obvious

13353twf.ptd Page 10 200535622 V. Description of the invention (5) Easy to understand 'The following exemplifies a preferred embodiment, which is described in detail below with reference to the attached drawings. [Embodiment] FIG. 1 is a block diagram of an instant data transmission system according to a preferred embodiment of the present invention. Referring to FIG. 1, the present invention provides a real-time data transmission circuit 2000 to connect a host computer and a signal processing device 120 at time X, and is used as a real-time data transmission interface. Among them, the host computer 丨 i 〇 is based on non-real-time operating software to operate, such as Windows operating software. The real-time signal processing device 120 is used to process real-time signals, such as a radar system. FIG. 2 is a block diagram of an instant data transmission circuit according to a preferred embodiment of the present invention. Referring to FIG. 2, the real-time data transmission circuit 2 0 and the host computer 1 1 0 perform non-immediate data transmission according to, for example, the s A / p c bus. The real-time data transmission circuit 200 and the real-time signal processing device 120 transmit data through a high-speed / real-time data transmission bus for real-time transmission, such as military-standard A N C bus. In this embodiment, the 'host computer 1 10' is coupled with the non-real-time data interface unit 2 of the data transmission circuit 2 0 through the SA / pc I bus and is used to send non-real-time data to the data. Transmission circuit within 200. Non-real-time data will be stored in memory unit 2 3 0 after inputting and outputting 7L 2 2 0. The real-time signal processing device 120 reads non-real-time data stored in the memory 230 by means of real-time data transmission through the network interface control unit 24. In contrast, when the instant signal processing device 120 needs to send real-time data to the host computer 110, it proceeds in the opposite way.

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Page 11 200535622 V. Description of the invention (6) In more detail, when the application program in the host computer 丨 丨 2 learns that the real-time signal processing device 1 2 0 needs to perform real-time data transmission, it will send non-real-time data The data and the control block c 〇ntr 〇1 for controlling the memory unit 230 and the network interface control unit 240 are sent to the non-real-time data interface unit 2 1 0 by, for example, Is A / PCI bus. . The non-real-time data interface unit 21 sends the non-real-time data to the input-output port 222 of the input-output unit 220. In addition, the non-real-time data interface unit 210 stores the control word con trol in the input / output port 2 24. Among them, the input / output port 22 2 determines whether to write non-real-time data into the memory unit 230. If the input / output port 222 determines that the non-real-time data is written into the memory unit 230, the non-real-time data will be stored in the memory (A) 2 32. 'Please continue to refer to FIG. 2 when the non-real-time data is stored in the memory (a) 2 3 2 0' The network " surface control unit 2 4 0 will go to the memory unit according to the control block c 0 ntr ο 1 Read non-real-time data in real-time data transmission mode within 230, and send non-real-time data to real-time signal processing device via high-speed / real-time data transmission bus such as ANC bus. 2 0. In contrast, when the real-time signal processing device 120 needs to send real-time data to the host computer, it stores the real-time data into the memory (B) 234 through the network interface control unit 24. The input / output port 222 reads the real-time data from the memory unit 230 and sends the real-time data to the host computer 110 through the non-real-time data interface unit 2o. The following describes the internal structure of each functional block separately. First, please refer to FIG. 3 ', which illustrates a block diagram of the internal structure of a non-real-time data interface unit according to a preferred embodiment of the present invention.丨 s A / p c I Bus Interface Unit 3 〇 1

13353twf.ptd Page 12 200535622 V. Description of the invention (7) It receives the non-real-time data transmitted by the ISA / PCI bus, and then sends it to the data output latch 3 〇3 and data through the internal data bus 3 1 Enter the latch 3 0 5. When the non-real-time data is sent to the non-real-time data interface unit 2 i 0, it is sent to the data output locker 3 0 3 through the ISA / PCI bus interface unit 301, and then sent out through the data output bus. If external real-time data is to be sent to the ISA / PCI bus through the non-real-time data interface unit 210, the data input latch will be sent to the data input latch via the data input bus 3 005 ^ and then sent through the internal data bus 31 The ISA / PCI bus interface unit 301 is output by the ISA / PCI bus. Please continue to refer to FIG. 3, the ISA / PCI bus interface unit 301 controls the latch / buffer device in the other functional blocks of the present invention through the control bus to control the direction of data transmission. In addition, the internal control signals of the non-real-time data interface unit 2 and the control signals of other function blocks of the present invention are temporarily stored in the control signal latch 3 07 through the internal data bus 31. The control signals that control the other functional blocks of the present invention are then output by the control bus. In addition, the buffer 3 0 9 in the 'non-real-time data interface unit 2 1 0 is connected to the flag register 3 1 1. In this embodiment, the flag register 3j can provide two flags for other function blocks in the present invention to set the flag. In the present invention, the other functional blocks in the present invention can set a flag through the cognitive signal ack to represent the current state of the functional block. For example, the host computer 1 1 0 in FIG. 1 can also read or clear the flag status stored in the flag register 3 1 1 through the internal data bus 3 丨. When the cognitive signal ack is enabled and the host computer is informed via the σ ISA / PCI bus interface unit 3, the host computer 1 10 will read or clear it through the ISA / PCI bus interface unit 301.

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Page 13 200535622 V. Description of the invention (8) Flag status. Buffer 3 0 9 can be a three-state buffer (3-S t a t e B u f f ^ r) ′ When the computer reads or clears the flag, the buffer 3 0 9 is on. When the non-real-time data interface unit 2 is transmitting data, the buffer 309 is in a high impedance state. In addition, the non-real-time data interface unit 2 10 can also be equipped with a clock generator 3 丨 3, which is used to provide the working clock required by the f-function block of the present invention. In this implementation, the frequency of the clock signal output by the clock generator 313 is 10 MHz. FIG. 4 is a block diagram showing an internal structure of an input / output unit το according to a preferred embodiment of the present invention. Please refer to FIG. 4, the control logic unit 4 丨 1 generates the internal control signal to the inspection circuit 4 1 according to the non-real-time data interface unit 2 丨 〇 by controlling the control signal sent from the bus 4 1 3, , Resources. Material β output latch 4 1 5 and data input latch 4 1 7. In addition, the f-system logic unit 4 1 1 will also send a cognitive signal ack to indicate the current state of the input / output unit 2 2 0. When the non-real-time data needs to be output through the input-output unit 0, it will be sent to the two-way bus 4 through the data bus, and then the data output latch 4 1 5 will take out the non-real-time data from the two-way bus 4 1 and follow The control logic unit 4 1 1 determines whether to output non-real-time data from the data output bus. In contrast, when real-time data needs to be transmitted through the input / output unit 2 2 0, the data input latch 4 1 7 'is first stored through the data input bus, and then the real-time data is determined according to the control logic unit 4 1 1 Into the two-way bus 4 丨. Continuing to refer to FIG. 4, in this embodiment, the input-output unit 2 2 0 further includes a check circuit 4 1 3. When the self-test mode of the present invention is activated,

13353twf.ptd Page 14 200535622 5 Invention description (9) = 413 will check the input result from the input and output unit 22〇 to the bidirectional bus 41. The old Beco also produced Fig. 5 is a block diagram showing the internal structure of a unit according to the present invention. Please refer to the figure. Best $ =, two types of memory ^ ^ > 1 M s R π 1 ιν u ^ δ,,, σ Hidden unit 530 includes control logic early 5 0 1 and two sets of symmetrical Store counter (Α) 512, memory (Α) 514 and, ^ and. Among them, the address system is fine # yarn six 4 and the buffer lock unit (A) 510 (B) Zhizhi pepper grilled miscellaneous one-Λ, Γ ten digits WB) 522, memory W ·-Punch lock () 5 2 0 constitutes the storage module (B). Since the operation modes of the f storage modules (A) and (B) are approximately the same, the working principle of the storage module (A) is described. Next " Please continue to refer to Figure ^, the control logic unit 501 is connected to the address counter r " and the address counter (B) 5 2 2 respectively, and is also coupled to the memory (A) 4 and the memory (B ) 5 2 4. In addition, the control logic unit 501 is further coupled to the buffer latch unit (A) 510 and the buffer latch list = (B) 5 2 0 through the internal data bus 51. Among them, the control logic unit 501 receives the control bus and sends an external control signal to generate an internal control signal to control the memory unit 530. The address counter (a) 5 1 2 receives the address signal transmitted by the address bus in order to generate the address address to the memory (A) 5 丨 4. The address a d d r e s s rotated to the memory (A) 5 1 4 may be loaded by the host computer 1 1 10 in FIG. 2 or may be sequentially generated by the address counter (A) 5 1 2. The memory (A) 5 1 4 is coupled to the buffer latch unit (A) 510 through the internal data bus 5 1. The buffer latch unit (A) 510 includes a data input latch (A) 5 1 6 And data output buffer (A) 5 1 8. Working principle and function of the buffer latch unit (A) 5 1 0, and the latch device of Fig. 3 and Fig. 4

200535622 V. Description of Invention (10) is similar and will not be repeated here. In the embodiment, two sets of storage modules can be operated at the same time. The two sets of storage modules can be operated simultaneously. Therefore, the buffer (a) 518 and the data output buffer (brother) 5 ° 8 are in the state of the data wheel out. Only one storage module is allowed for the wheel 503 at a time, and two types of “self: body” are provided in the flag. The element 23 ° also includes the temporary storage of the flag except its value. 〇 Set or clear the status. The stack electronics 110 can also read from the flag register 5 0 3 "Please continue to refer to Figure 2, the network loser _ w interface controller 242 and TTL_ ^ t control unit 2 4 0 includes The programmable interface controller 242 is responsible for changing the interface 244. Among them, the programmable device 120 performs real-time data ^ that is, the output circuit 2 0 0 and real-time signal processing will transmit high-speed / real-time data ^ ^ '' differential level conversion interface 2 44 interface 则 6ΛΞ 部 明 之: a kind of preferred embodiment The microprogram can be programmed inside the program: II 丨: Refer to Fig. 6 'storage device 601 for the operation flow. The sequencer 6 0 3 is coupled to the microcomputer in the storage device m of the road interface control unit 240; the J connection: the setting 601 is used to execute the programming in the condition system. In this embodiment, the condition selector of the external 1 storage device is generated. In addition, " event / interrupt handler 607 and microprocessor 609. 200535622 V. Description of the invention (11) The event / interrupt handler 6 0 7 is used to disable, enable, and process interrupt signals or events generated by the host computer as shown in FIG. 2, and the event / interrupt handler 607 will generate an interrupt The vector (Interrupt Vector) to the condition selector 605 causes the sequencer 603 to execute an interrupt service routine. The microprocessor 609 is used to perform the operation of the arithmetic logic unit explained by the sequencer 603 in order to produce a result. In addition, in this embodiment, the programmable interface controller 242 also includes a parity element (Parity M = set 611 'is used to check whether the parity input to the programmable interface controller is correct, and generates the parity to the programmable path 242. Among the output data, the flying surface control is the above-mentioned. The real-time data transmission of the present invention is a bit check generating device, so the recognition can be reduced. Because it has the same feature, the present invention also provides a bit f in the memory unit. = Error. There will be no data sequence error when transferring data. ^ = Therefore, in the real-time data transmission interface provided by the present invention $ 土 二 = In addition, non-real-time data or real-time data is stored in two ^ In the case of material, the non-real-time data will be transmitted in real time-early to middle, so it can be transmitted. Or the real-time data will be transmitted in non-real time. Although the present invention has been limited to the present invention by preferred embodiments, anyone skilled in this art will be familiar with it. The above is not intended to be used within the scope, but can be changed slightly without departing from the spirit of the present invention.

13353twf.ptd Page 17 200535622 Brief Description of Drawings Figure 1 is a block diagram of an instant data transmission system according to a preferred embodiment of the present invention. FIG. 2 is a block diagram of an instant data transmission circuit according to a preferred embodiment of the present invention. FIG. 3 is a block diagram showing an internal structure of a non-real-time data interface unit according to a preferred embodiment of the present invention. FIG. 4 is a block diagram showing an internal structure of an input / output unit according to a preferred embodiment of the present invention. FIG. 5 is a block diagram showing an internal structure of a memory unit according to a preferred embodiment of the present invention. FIG. 6 is a block diagram showing the internal structure of a programmable interface controller according to a preferred embodiment of the present invention. [Illustration of Graphical Symbols] 3 1, 5 1: Internal data bus 41: Bidirectional bus 1 1 0: Host computer 1 1 2: Application program 1 2 0: Real-time signal processing device 2 0 0: Real-time data transmission circuit 2 1 0: Non-real-time data interface unit 220: Input-output unit 222, 224: Input-output Tan # 2 3 0: Memory unit 2 3 2: Memory (A)

13353twf.ptd Page 18 200535622 Schematic description 234 Memory (B) 240 Network interface control unit 242 Programmable controller 244 TTL-differential level conversion interface 30 1 ISA / PC I bus interface unit 303 Data m latch 305 data input latch 307 control signal latch 309 buffer 31 1 flag register 313 clock generator 411, 50 1: control logic unit 413 check circuit 415 data output latch 417 Data m input latch 510 buffer latch unit (A) 512 address bus (A) 514 memory (A) 516 data input latch (A) 518 data output buffer (A) 520 buffer latch unit (B) 522 address bus (B) 524 memory 526 data m out buffer (B)

13353twf.ptd Page 19 200535622 Schematic description 528 Data input latch (B) 60 1 Storage device 603 Sequencer 605 Condition selector 607 Event / interrupt handler 61 1 Parity generation check device

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Claims (1)

200535622 6. Scope of patent application 1 · A real-time data transmission interface is suitable for real-time transmission of a non-real-time data and non-real-time transmission of a real-time data. The real-time data transmission interface includes: a non-real-time data interface unit for To receive / transmit the non-real-time data; an input-output unit coupled to the non-real-time data interface unit as a transmission interface between the non-real-time data and the real-time data; a memory unit coupled to the output-input unit for temporary storage The non-real-time data and the real-time data; and a network interface control unit coupled to the memory unit for receiving / transmitting the real-time data. L 2. The real-time data transmission interface as described in item 1 of the scope of the patent application, wherein the non-real-time data interface unit includes: a bus interface unit, which serves as an interface for the non-real-time data input / output; a data output latch, The internal data bus is coupled to the bus interface unit, and the data output latch is used as a latch for the non-real-time data interface unit to output data to other units; a data input latch is used for the internal data bus The bus is coupled to the bus interface unit, and the data output latch is used as a latch for the non-real-time data interface unit to receive data transmitted by other units; a control signal latch is connected to the bus through the internal data bus The bus interface unit is coupled, and the control signal latch is a latch that is a control signal sent by the non-real-time data interface unit to other units; 13353twf.ptd Page 21 200535622 VI. Patent application scope A buffer, which is coupled to the bus interface unit through the internal data bus; and a flag register, which is coupled to the buffer to store a flag status . 3. The real-time data transmission interface as described in item 2 of the scope of patent application, wherein the buffer includes a tri-state buffer, and when the flag status in the flag register is set / read, the tri-state buffer The three-state buffer is in a high-impedance state when the flag state is not set / read. 4. The real-time data transmission interface described in item 2 of the scope of patent application, wherein the non-real-time data interface unit further includes a clock generator for generating a clock signal to other units, and the frequency of the clock signal is 10 Μ Η z. 5. The real-time data transmission interface as described in item 1 of the scope of patent application, wherein the input-output unit includes: a control logic unit that reads / writes the input-output unit according to an external control signal; An inspection circuit is coupled to the control logic unit. When a self-test mode is activated, the control logic unit controls the inspection circuit to check the correctness of the data output by the input and output unit, and generates an inspection result; a data output pin A lock coupled to the control logic unit, and when the non-real-time data is transmitted through the input-output unit, the control logic unit controls the non-real-time data to be latched to the data-output latch and decides whether to input > output the non-real-time Data; and a data input latch, coupled to the control logic unit, when the real-time 13353twf.ptd Page 22 200535622 6. Scope of Patent Application ___ When the data is read through the input wheel-out unit, 誃 receive the real-time data. Λ, the shaking wheel into the latch system 6. As described in the scope of the application for patent application, the memory unit includes: f beating wheel interface, a control logic unit, based on an external body control unit; soul control The memory is a first address counter, which is coupled to the control logic unit ^ ^ the first address; 70 'is to provide a first memory, which is coupled to the non-real-time data of the first address meter; 15 is used to store the A first buffer latch unit, through an internal memory, is used as the first memory input / round sink: coupled to the second L handle to the control logic unit, providing a first one Two memories, coupled to the second address real-time data; and a device for storing the second buffer latch unit, and passing the second internal memory as the second memory to input two materials: row eight Face to face, the memory unit further includes a flag temporarily seizing the interface, state. It is used to store a flag. 8. As described in item 丨 of the scope of patent application, the network interface control unit includes a human interface, a transmission n-plane, a TTL / differential level conversion interface, and a ττ 丨. / 1-side controller and — /, medium and TTL / differential level conversion interface 13353twf.ptd Page 23 200535622 VI. Application for Patent Scope To make this real-time information _Tu ^^^ and temporarily store the real-time information. Sad and-differential-type door-to-door basin Λ Ruϋ Conversion of patent No. 8 in the patent scope 'Eight ° χ program " surface controller includes, real-time data of L. ^ A storage device The material transfer wheel interface, the interface controller's control function, stores a micro-style order; the sequencer, which is connected to the wrong storage device in turn, is used to control the program, and 'adjusted according to external conditions to execute the widget- The condition selector, the sequence of splicing; A-type means to provide the sequencer for judgment; ^, used to temporarily store the external bar age ^ Γ event / interrupt handler, coupled to the storage ten, break ## and Either one of the two events; χ = storage device, used to process the order; to connect the storage device '15 to run the micro program, the output of the two is used to control the controller according to the program interface Either generate a parity bit and check the parity bit of the real-time data input to the program " face control | §. 〇 A real-time data transmission system, including: — the host computer 'operates according to one of the non-real-time processing software; a 1-hour signal processing device for processing a real-time data; and a data transmission circuit for connecting the host The computer and the real-time signal processing device, 'the data transmission circuit receives a non-real-time data output from the host computer' and simulates the real-time transmission to send the non-real-time data to the real-time signal processing device. In addition, the data The transmission circuit is Page 24 200535622 VI. Scope of patent application The real-time data output by the signal processing device, and the non-real-time transmission is used to send the real-time data to the host computer. 1 1. The real-time data transmission system as described in item 10 of the scope of patent application, wherein the host computer has an application program for controlling the operation of the data transmission circuit. 1 2. The real-time data transmission system as described in item 10 of the scope of patent application, wherein the data transmission interface includes: a non-real-time data interface unit coupled to the host computer for use as the host computer and the data transmission circuit Interface for data transmission, and the non-real-time data interface unit provides a clock signal; an input-output unit is coupled to the non-real-time data interface unit for latching the non-real-time data to a data output bus, and Real-time data is latched on a data input bus; a memory unit is coupled to the input-output unit to store the non-real-time data and the real-time data, and a network interface control unit is coupled to the memory unit and the The real-time signal processing device is used as an interface for data transmission between the real-time signal processing device and the data transmission circuit. 1 3. The real-time data transmission system described in item 12 of the scope of patent application, wherein the non-real-time data interface unit and the host computer transmit data according to an ISA / PCI bus. 14. The real-time data transmission system according to item 12 of the scope of patent application, wherein the input-output unit has a first input-output port and a second input-output port, wherein the first input-output port is used for storing control The network 13353twf.ptd Page 25 200535622 6. The control word set of the patent control interface control unit and returns a flag status to the host computer. In addition, the second input and output port is used to write the non-real-time data to the network interface. The control unit, or read the real-time data from the network interface control unit. 15. The real-time data transmission system as described in item 12 of the scope of patent application, wherein the memory unit includes a first memory and a second memory for storing the real-time data and the non-real-time data. 16. The real-time data transmission system as described in item 12 of the scope of patent application, wherein the network interface control unit includes a programmable interface controller and a TTL / differential level conversion interface. 1 7. The real-time data transmission system described in item 16 of the scope of patent application, wherein the programmable interface controller is used for real-time data transmission with the real-time signal processing device. 1 8. The real-time data transmission system described in item 16 of the scope of patent application, wherein the TTL / differential level conversion interface is used to convert a TTL type bus signal into a differential type bus signal. 13353twf.ptd Page 26