.200534069 九、發明說明： 【發明所屬之技術領域】 本發明係關於一種電流負載偵測裝置及組設電流負載 偵測裝置之電源供應系統。 【先前技術】 如圖1所示，在習知之負載偵測裝置中，電源供應器10 | 係用以輸入高電壓準位（例如：110伏特）之交流電，並輸 出低電壓準位（例如：12伏特）之直流電，以供應中央處 10 理器40或其他負載裝置運作時所需之電力◦由於中央處理 器40消耗電力所需之電壓準位（例如：3.3伏特）較電源供 應器10所提供之電壓準位為低，故藉由儲能電感24及儲能 電容26之儲能能力，並配合PWM控制器12控制高閘極控制 訊號Ugate及低閘極控制訊號Lgate，以分別控制開關器20 15 及開關器22之開啓/閉合狀態，使電源供應器10可提供電力 > 至中央處理器40。其中，開關器20所汲取之電力係由電源 供應器10所提供，PWM控制器12可依據中央處理器40所汲 取之電力大小而調整開關器20及開關器22之切換速度，以 滿足中央處理器40於重負載或輕負載下之電力消耗。又為 20 了監視中央處理器40之表面溫度，係於儲能電感24與中央 處理器40之間，放置一個並接之電阻30及感應器32，感應 器32可偵測電阻30上之壓降，以間接取得中央處理器40所 汲取之電流量或壓降變化，如果電流量係為增加或壓差增 加，則感應器32命令電子裝置42 (例如：散熱風扇）加強 200534069 散熱效果；如果電流量係為減少或壓差減少，則感應器％ 命令電子裝置42降低散熱效果。 ^然而，使用電阻3〇及感應器32所組成之習知負載偵測 衣而待中央處理益 40因負載大小而改變電流汲取量 5後，感應器32方調整電子裝置42之運作，由於電子装f42 之運作無法與中央處理器4〇之電力消耗同步，且藉由電阻 $面量測電流變化或壓差變化，將產生較大之誤差，而且 .若負載電流過大時，該電阻會產生過大的功率消耗；因此， 這將導致後端中央處理器4〇之表面溫度逐漸上升，益法發 ω揮電子裝置42最佳之功效，且產生不必要的功率消耗。 【發明内容】 15 20 *本，明之主要目的係在提供一種電流負載偵測裝置， :負載衣置之負載產生變化時，俾能偵測pwM王作週期訊 號之變化而調整電子裝置之運作。 ^本毛月之另目的係在提供一種電源供應系統，可供 私土負載衣£’並依據負載裝置之負載產生變化而調整電 子裝置之運作。 為達成上述目的，本發明揭露一種電流負載偵測裝 ^ u括·卞位取樣态，係對PWM工作週期訊號進行取樣， 並輸出取樣訊號；頻率淳&盟 少 ，、+產生裔，係用以產生高頻訊號；計 時器，係用以輸入高艏却啼#兩 口 门Λ、Λ就並累計之，以產生單位時間訊 號並輸出之；計數器，佴· 、 係用以輸入取樣訊號並累計之，以 產生累加訊號，並依攄s a此_ 依蘇早位時間訊號而輸出累加訊號；以 6 200534069 及控制器，係用以依據累加訊號而輸出電子裝置控制訊 號，以控制電子裝置之運作0 為達成上述目的，本發明揭露一種電源供應系統，包 括：電源產生器，係用以提供電力；PWM控制器，係整合 5 於電源產生器，其依據負載裝置之負載狀態而輸出PWM工 作週期訊號；能量儲存裝置，係依據PWM工作週期訊號而 儲存電力，並輸出電力至負載裝置；電流負載偵測裝置， 係用以依據PWM工作週期訊號而輸出電子裝置控制訊號； > 以及電子裝置，係依據電子裝置控制訊號而運作。 10 在上述之中，負載裝置可為中央處理器、顯示晶片等 負載裝置；電子裝置可為散熱風扇、超頻器等電子裝置； 而PWM工作週期訊號可為高閘極控制訊號Ugate、低閘極控 制訊號Lgate、或PWM訊號。 15 【實施方式】 為能讓貴審查委員能更瞭解本發明之技術内容，特舉 > 一較佳具體實施例説明如下。 如圖2所示，本發明電流負載偵測裝置50可依據高閘極 控制訊號Ugate、低閘極控制訊號Lgate、或PWM訊號之脈 20 波寬度之變化以調整電子裝置42 (例如：散熱風扇）之運 作，在本實施例中並以高閘極控制訊號Ugate為例，進行本 發明電流負載偵測裝置50運作之説明，但不以此為限。因 此，如果高閘極控制訊號Ugate之高準位維持時間增加，則 加強電子裝置42之運作，例如：增加散熱風扇之轉速；如 200534069 果高閘極控制訊號Ugate之高準位維持時間減少，則減少電 子裝置42之運作，例如：降低散熱風扇之轉速。 甩 如圖3所示，電流負載偵測裝置5〇可由準位取樣器μ、 頻率產生器54、計時器56、計數器58控制器6〇、及暫存哭 62所組成。頻率產生器54係用以產生高頻訊號，例如⑴二.200534069 IX. Description of the invention: [Technical field to which the invention belongs] The present invention relates to a current load detection device and a power supply system equipped with a current load detection device. [Prior art] As shown in FIG. 1, in a conventional load detection device, the power supply 10 | is used to input AC voltage at a high voltage level (for example, 110 volts) and output a low voltage level (for example: 12 volts) of DC power to supply power required by the central processing unit 10 or other load devices. ◦ The voltage level required by the central processing unit 40 to consume power (eg, 3.3 volts) is lower than that of the power supply unit 10. The voltage level provided is low. Therefore, the high-gate control signal Ugate and the low-gate control signal Lgate are controlled by the energy storage capacity of the energy storage inductor 24 and the energy storage capacitor 26 and the PWM controller 12 to control the switches respectively. The open / closed states of the switches 20 15 and the switch 22 enable the power supply 10 to provide power to the CPU 40. The power drawn by the switch 20 is provided by the power supply 10, and the PWM controller 12 can adjust the switching speed of the switch 20 and the switch 22 according to the amount of power drawn by the central processing unit 40 to meet the central processing. Power consumption of the device 40 under heavy load or light load. It is also 20 to monitor the surface temperature of the central processing unit 40. It is connected between the energy storage inductor 24 and the central processing unit 40, and a parallel resistor 30 and an inductor 32 are placed. The sensor 32 can detect the pressure on the resistor 30. Drop to indirectly obtain the change in the amount of current or voltage drop drawn by the central processing unit 40. If the amount of current is increased or the pressure difference is increased, the sensor 32 commands the electronic device 42 (for example: a cooling fan) to strengthen the 200534069 cooling effect; if In order to reduce the amount of current or the pressure drop, the sensor% instructs the electronic device 42 to reduce the heat dissipation effect. ^ However, after using a conventional load detection garment consisting of a resistor 30 and a sensor 32 and waiting for the central processing 40 to change the current draw 5 due to the load size, the sensor 32 adjusts the operation of the electronic device 42. The operation of the f42 cannot be synchronized with the power consumption of the CPU 40, and the current or pressure difference measured by the resistance $ will cause a large error, and if the load current is too large, the resistance will produce Excessive power consumption; therefore, this will cause the surface temperature of the back-end central processing unit 40 to gradually rise, the best efficiency of the electronic device 42 and the unnecessary power consumption. [Summary of the invention] 15 20 * The main purpose of this and Ming Ming is to provide a current load detection device: when the load of the load is changed, it cannot detect the change of the pwM king cycle signal to adjust the operation of the electronic device. ^ Another purpose of this month is to provide a power supply system that can be used to load clothes on the ground, and adjust the operation of the electronic device based on changes in the load of the load device. In order to achieve the above object, the present invention discloses a current load detection device including a sampling state, which samples a PWM duty cycle signal and outputs a sampling signal; the frequency is & It is used to generate high-frequency signals; the timer is used to input high 艏 but cry # two mouth doors Λ, Λ are accumulated to generate a unit time signal and output; the counter, 佴 ·, is used to input the sampling signal and Accumulate to generate accumulated signal and output the accumulated signal according to the early time signal of _sa; 6 200534069 and the controller are used to output the electronic device control signal based on the accumulated signal to control the electronic device. Operation 0 In order to achieve the above purpose, the present invention discloses a power supply system including: a power generator for supplying power; a PWM controller integrated with the power generator, which outputs PWM work according to the load status of the load device Periodic signal; energy storage device, which stores power according to the PWM duty cycle signal and outputs power to the load device; current load detection device, PWM signal according to the duty cycle of the control signal and outputs the electronic apparatus; > and an electronic device, the electronic device control system based on the operation signal. 10 Among the above, the load device may be a load device such as a central processing unit, a display chip; the electronic device may be an electronic device such as a cooling fan, an overclocker; and the PWM duty cycle signal may be a high-gate control signal Ugate, a low-gate Control signal Lgate or PWM signal. 15 [Embodiment] In order to allow your review committee to better understand the technical content of the present invention, a special > preferred embodiment is described below. As shown in FIG. 2, the current load detection device 50 of the present invention can adjust the electronic device 42 according to the variation of the 20-wave width of the high-gate control signal Ugate, the low-gate control signal Lgate, or the PWM signal (eg, a cooling fan) ) Operation, in this embodiment, a high gate control signal Ugate is taken as an example to describe the operation of the current load detection device 50 of the present invention, but it is not limited thereto. Therefore, if the high-level maintaining time of the high-gate control signal Ugate increases, the operation of the electronic device 42 is strengthened, for example: increasing the speed of the cooling fan; such as 200534069 if the high-level maintaining time of the high-gate control signal Ugate is reduced, Then, the operation of the electronic device 42 is reduced, for example, the speed of the cooling fan is reduced. As shown in FIG. 3, the current load detection device 50 may be composed of a level sampler μ, a frequency generator 54, a timer 56, a counter 58 and a controller 60, and a temporary storage 62. The frequency generator 54 is used to generate high-frequency signals, such as
Hz之高頻訊號，並輸出高頻訊號至計時器％。準位取 5 2可用以對高閘極控制訊號u g a t e進行取樣，並輸出取= 號至計數器58。計時器56計數高頻訊號之次數，例如^ 數1〇〇個高頻訊號，並輸出單㈣間訊號至計數⑽激 器58係用以累計取樣訊號之次數，並於接收單 訊 之同時，輸出累加訊號至控制器：爾 訊號與散熱風扇轉速（或自載〜士來存态62係儲存累加 飞員載私流大小）之對應表。例如· 當累加訊號為8〇時，散熱風扇轉速較佳係為3200轉 15 ^號40時，散熱風扇轉速較佳係為16轉。此外，^存 “2係可储存累加訊號與散熱風扇 如:散熱風扇轉速較佳係等於累加訊號乘二 加訊號與散熱風扇轉速亦可非直接對應，而累 應至散熱風肩消耗功率，例如二、疋累加Λ號對 扇消耗功率較佳係為8〇% .號為80時，散熱風 耗功率較佳係為4〇%於；：加訊號40時’散熱風扇消 應關係有許多可能，並==號與散熱風扇轉速之對 器62之累加訊號與散熱風扇‘之：:：制器6。讀取暫存 號而輸出致能訊號Fac至電子裝 應表，並依據累加訊 風扇），以調整散熱風扇之 ^万、此例較佳係為散熱 .逯或消耗功率。電子裝置42 20 200534069Hz high frequency signal and output high frequency signal to timer%. The level pick 5 2 can be used to sample the high gate control signal u g a t e and output the fetch = sign to the counter 58. The timer 56 counts the number of high-frequency signals, for example, 100 high-frequency signals, and outputs a single signal to the counting exciter 58 for accumulating the number of sampling signals, and at the same time as receiving the single signal, Output the accumulated signal to the controller: Correspondence table between the signal and the speed of the cooling fan (or self-loaded ~ Shilai store state 62 is the size of the accumulated accumulated pilot private flow). For example, when the cumulative signal is 80, the speed of the cooling fan is preferably 3200 rpm. 15 ^ 40, and the speed of the cooling fan is 16 rpm. In addition, the “2 series” can store the accumulated signal and the cooling fan. For example, the speed of the cooling fan is preferably equal to the cumulative signal multiplied by two plus the speed of the cooling fan. Second, the cumulative power consumption of the fan No. Λ is preferably 80%. When the number is 80, the power consumption of cooling air is preferably 40%; When the signal is 40, there are many possibilities for cooling fan response. , And == and the accumulated signal of the cooling fan speed counter 62 and the cooling fan '::: controller 6. Read the temporary number and output the enable signal Fac to the electronic assembly table, and according to the accumulated signal fan ) To adjust the cooling fan, this example is better to dissipate heat or consume power. Electronic device 42 20 200534069
土中央處理器40，其可依據致能訊號FAC之大小而調整中央 處理為40之工作頻率（内頻或外頻），使中央處理器40於 重載時能以較高之運算能力以處理負載，於輕載時能以一 身又之運异化力以處理負載，如此一來，中央處理器之運 算能力即可隨負載之變化而調整，以提高中央處理器4〇之 運作效能。 i 如圖4所示，中央處理器4〇負載之初始狀態係為穩定， 田中央處理$ 4G因故増加負載時，由於中央處理器4〇所消 10耗之功率增加，故瞬間消耗電流I上升，瞬間輸入電壓ν〇υτ 下降，此時，PWM控制器12偵測到輸入電壓ν〇υτ2變化， 故增加單位時間内高閘極控制訊號卩纠“之高準位 間（相反地即降低單位時間内高閘極控制訊號❿攸之低準 位維持時間），如單位時間T1、T2、及Τ3所示，此時，中 15央處理器40所消耗之功率增加，故其溫度亦增加，電 載偵測裝置50偵測高閘極控制訊號之高準位維 間之變化，故提高散熱風扇之轉速或消耗功率。於單 間T4及T5時，由於負載消耗已回歸穩定，故逐漸降低 極控制訊號Ugate之高準位維持時間，此時 裝置50偵測高閘極控制訊號Ugatei高準位維持時 化，故逐漸降低崙埶4 μ、n、、上_ ' 待時間之變 於單位時間 ’故鬲閘極控制訊 此時，電流負 化，故逐漸降低散熱風扇之轉速或消耗功率。 T5之後’由於負載消耗已回復正常狀態，故高 號Ugate4咼準位維持時間亦回復正常狀 200534069 載偵測裝置50使散熱風扇之運作維持在正常之轉速或消耗 功率。 可想而知地，本發明電流負載偵測裝置50除可依據高 閘極控制訊號Ugate之脈波寬度之變化以調整電子裝置42 5 之運作外，亦可依據低閘極控制訊號Lgate之脈波寬度之變 化以調整電子裝置42之運作，如圖5所示，由於運作過程與 上述説明相似，故不多作贅述◦此外，為了強化高閘極控 制訊號Ugate及低閘極控制訊號Lgate之驅動能力，使用者亦 > 可於電源供應器10内之PWM控制器12之後端加入緩衝裝置 10 28，其中，緩衝裝置28可為正向器、反向器、緩衝器、或 上述元件之結合，如圖6所示，因此，本發明電流負載偵測 裝置50亦可依據PWM訊號（PWM控制器12之輸出訊號）之 脈波寬度之變化以調整電子裝置42之運作。在此連結關係 下，本發明電流負載偵測裝置50之運作過程與上述説明相 15 似，故不多作贅述。 當中央處理器40之負載一改變，高閘極控制訊號 Ugate、低閘極控制訊號Lgate、或PWM訊號之高/低準位維 持時間亦改變（即Duty Cycle改變），而本發明電流負載偵 測裝置50可偵測出高閘極控制訊號Ugate、低閘極控制訊號 20 Lgate、或PWM訊號之高/低準位維持時間之變化，可於第 一時間調整電子裝置42之運作，以排除中央處理器40所產 生之熱能，故較習知負載偵測裝置具有顯著之進步性。 200534069 上述實施例僅係為了方便說明而舉 牛例而已，本發明所 主張之權利範圍自應以申請專利範圍所述為準，而非僅限 於上述實施例。 又 5The local CPU 40 can adjust the working frequency (internal frequency or external frequency) of the central processing unit 40 according to the size of the enabling signal FAC, so that the central processing unit 40 can process with a higher computing power under heavy load. The load can deal with the load with the alienation force at light load. In this way, the computing power of the central processing unit can be adjusted as the load changes to improve the operating performance of the central processing unit 40. i As shown in Figure 4, the initial state of the CPU 40 load is stable. When Tian Tianzhong processes $ 4G for some reason, when the load is increased, the power consumed by the CPU 4 10 increases, so the instantaneous current consumption I The input voltage ν〇υτ decreases when the input voltage rises. At this time, the PWM controller 12 detects a change in the input voltage ν〇υτ2. Therefore, it increases the high level between the high gate control signal and the correction level per unit time. The high gate control signal maintains the low level maintenance time per unit time), as shown in the unit time T1, T2, and T3. At this time, the power consumed by the central 15 central processor 40 increases, so its temperature also increases. The electric load detection device 50 detects the change in the high level dimension of the high-gate control signal, so the speed or power consumption of the cooling fan is increased. At single rooms T4 and T5, the load consumption has returned to stable, so it is gradually reduced. The high level maintenance time of the pole control signal Ugate. At this time, the device 50 detects that the high level of the high gate control signal Ugatei is maintained in time. Therefore, it gradually lowers the 埶 4 μ, n, and _ 'until the time changes to the unit. Time's gate At this time, the current is negative, so the speed or power consumption of the cooling fan is gradually reduced. After T5 ', because the load consumption has returned to normal, the high level Ugate4 咼 level maintenance time also returns to normal. 200534069 Load detection device 50 The operation of the cooling fan is maintained at a normal speed or power consumption. It is conceivable that the current load detection device 50 of the present invention can adjust the electronic device 42 5 according to the change in the pulse width of the high-gate control signal Ugate. In addition to the operation, the operation of the electronic device 42 can also be adjusted based on the change in the pulse width of the low gate control signal Lgate. The driving capability of the high-gate control signal Ugate and the low-gate control signal Lgate, the user can also add a buffer device 10 28 to the rear end of the PWM controller 12 in the power supply 10, wherein the buffer device 28 can be positive A commutator, inverter, buffer, or a combination of the above components, as shown in FIG. 6, therefore, the current load detection device 50 of the present invention can also be based on the PWM signal (PW The pulse width of the output signal of the M controller 12 is changed to adjust the operation of the electronic device 42. Under this connection relationship, the operation process of the current load detection device 50 of the present invention is similar to that described above, so it is not necessary to do more. When the load of the CPU 40 is changed, the high / low level maintenance time of the high-gate control signal Ugate, the low-gate control signal Lgate, or the PWM signal also changes (that is, the Duty Cycle changes), and the current of the present invention changes. The load detection device 50 can detect the change of the high / low level maintaining time of the high-gate control signal Ugate, the low-gate control signal 20 Lgate, or the PWM signal, and can adjust the operation of the electronic device 42 at the first time. In order to exclude the thermal energy generated by the central processing unit 40, it has a significant improvement over the conventional load detection device. 200534069 The above embodiments are merely examples for convenience of explanation. The scope of the rights claimed in the present invention shall be based on the scope of the patent application, rather than being limited to the above embodiments. Another 5
10 【圖式簡單說明】 圖1係習知負載偵測裝置之示意圖。 圖2係本發明電流負載偵測裝置之示意圖。 圖3係本發明電流負載偵測裝置之方塊圖。 圖4係負載與之高閘極控制訊號之關係圖。 圖5係本發明電流負載偵測裝置之另—示意圖。 及緩 圖6係本發明電流負載偵測裝置、pWM控制器 衝裝置之連結關係之示意圖。 【主要元件符號 說明: 10 電源供應器 12 22 開關器 24 30 電阻 32 42 電子裝置 50 54 頻率產生器 56 62 控制器 6010 [Schematic description] Figure 1 is a schematic diagram of a conventional load detection device. FIG. 2 is a schematic diagram of a current load detection device according to the present invention. FIG. 3 is a block diagram of a current load detection device according to the present invention. Figure 4 is the relationship between the load and the high gate control signal. FIG. 5 is another schematic diagram of the current load detection device of the present invention. Figure 6 is a schematic diagram of the connection relationship between the current load detection device and the pWM controller punch device of the present invention. [Symbol of main components Explanation: 10 Power supply 12 22 Switch 24 30 Resistance 32 42 Electronic device 50 54 Frequency generator 56 62 Controller 60
PWM控制器 儲能電感 感應器 電流負載偵測裝 計時器 暫存器 2〇開關器 儲能電容 40 中央處理器 置52準位取樣器 58計數器 28 緩衝裝置 15PWM controller Energy storage inductor Sensor Current load detection timer Timer register 20 Switch energy storage capacitor 40 CPU set 52 level sampler 58 counter 28 buffer device 15