TW200533069A - Combination field programmable gate array allowing dynamic reprogrammability - Google Patents

Abstract

A cell that can be used as a dynamic memory cell for storing data used in programming a field ogrammable gate array(FPGA) is disclosed. The cell comprises a select transistor having a gate, a source, and a drain, the gate connected to said write bitline, the source connected to a floating point node, and the drain connected to a row wordline. A sense device determines the data stored on the floating point node. Finally, switch that is controlled by the floating point node is provided.

Description

200533069_ V. Description of the invention (1) [Technical field to which the invention belongs] The present invention relates to a field programmable gate array (FPGA), and in particular to a gate capable of being dynamically reprogrammed by charging a charge, and a gate based on a transistor The breakdown of the gate oxide layer (gate ο X ides) comes to a non-volatile programmable one-time programmable gate array. [Previous Technology] Field programmable gate arrays (FPGAs) are constantly producing more applications, such as logic and / or processing elements. A field programmable gate array using a static random access memory (SRAM) cell type requires six transistors. This static random access memory system is used to provide configurable or programmable switches, and The above code is usually stored in a chip's non-volatile memory in a bit map. A field programmable gate array based on static random access memory is first programmed by programming the non-volatile memory, and the bit stream from the non-volatile memory is The non-volatile memory is loaded into the static random access memory, and the static random access memory system is used to control the field programmable gate array. This solution for multiple wafers (mu 1 t i-c h i p) leads to the formation coefficient (f 0 r m f a c t 0 r) of magic | and relatively high cost. • Another type of field programmable gate array is based on anti-fuse (an t l-f u s e) technology. Although widely accepted, anti-fuse technology still requires a special fuse process. In addition, field-programmable gate arrays based on anti-fuse technology can only be programmed

Page 6 200533069 ________________________ V. Description of Invention (2) Once. Another type of field-programmable gate array is based on flash memory (f 1 a s h memory) technology. However, flash memory technology requires more complex semiconductor processes, which will increase costs. In addition, flash memory technology typically lags the first to second generation of advanced complementary metal-oxide-semiconductor field-effect transistor (CMOS) logic processes. • [Abstract] The present invention provides a unit cell, which can be used as a dynamic memory book unit for storing data or a field programmable gate array (FPGA) unit cell for programming. In an array of bit lines, read bit lines, and column word lines, the unit cell includes a capacitor having a first end and a second end, and the first end is connected to a row of bit lines. And the second terminal is connected to a switch control node; a selection transistor has a gate, a source, and a drain, wherein the gate is connected to a write bit line, and the source is connected to the above A switch control node, and the drain is connected to the column word line; and a switch is controlled by the switch control node, wherein the switch control node stores data with a voltage of 0 or 1. The present invention provides a method for operating a dual-mode cell connected to a column of word lines, a row of write lines, and a read bit line, wherein the unit cell includes: a capacitor having a first terminal and a first terminal; Two terminals, the first terminal is connected to the row write bit line, and the second terminal is connected to a switch control node;

Page 7 200533069 V. Description of the invention (3) A selection transistor having a gate, a source and a drain, the gate is connected to the read bit line, and the source is connected to the switch control node And the drain is connected to a row of word lines; and a switch is controlled by the switch control node; the steps of the method include: when the cell is used as a field programmable gate array (FPGA) cell and is programmed: (1) providing a first voltage to the row bit line; (2) turning on the selection transistor; and (3) providing a second voltage to a selected word line of the column, wherein the first voltage is Forming a potential difference with the second voltage through the capacitor makes the dielectric used to convert the capacitor into a resistive element collapse; when the unit cell is used as a dynamic memory unit to store data •: (1) On The above selection transistor; (2) The above data is provided to the above-mentioned switch control node through the above-mentioned word line, wherein the above-mentioned switch control node stores the data with a voltage of 0 or 1. The invention provides a unit cell, which can be used as a dynamic memory unit cell for storing data or a field programmable gate array unit cell for programming. The unit cell is used to have row bit lines and read bit lines. In an array of word lines, the unit cell includes: a capacitor having a first end and a second end, the first end being connected to a row of bit lines (B p), and the second end Connection | a switch control node; a selection transistor having a gate, a source, and a drain, wherein the gate is connected to the write bit line (Bw ·), and the source is connected to the switch A control node and the drain connected to a line of word lines (WL); a switch controlled by the switch control node, wherein the switch control node is stored with a voltage of 0 or 1

Page 8 200533069__ 5. Description of the invention (4) Materials; and a sensing element for determining the above voltage on the above-mentioned switch control node. The invention provides a unit cell, which can be used as a dynamic memory unit cell for storing data. The unit cell is used for an array having a row bit line, a read bit line, and a column word line. The cell includes: a capacitor having a first end and a second end, wherein the first end is connected to a row of bit lines (Bp), the second end is connected to a switch control node, and the switch control node is stored The above data; a selection transistor (Tw) having a gate, a source, and a drain, wherein the gate is connected to the write element line (Bw) and the source is connected to the switch control node, The drain is connected to a series of word lines; and, a sensing element is used to determine data located on the switch control node. [Embodiment] The present invention discloses a transistor-based Field Programmable Gate Array (FPGA) with an ultra-thin dielectric layer, which can be crushed (soft or hard) under pressure to set leakage The value of the current. A suitable ultra-thin dielectric layer is a high-quality gate oxide layer (gate OX ide) with a thickness of about 50 A or less and used in the electrical body. Generally, it can be made by the current advanced complementary metal-oxide-semiconductor field-effect transistor. (CMOS) logic process. This oxide layer is usually formed by depositing, growing oxide from the active area of silicon, or some combination thereof. Other suitable dielectric values include oxide-nitride-oxide composites or oxide composites.

Page 9 200533069 V. Description of the invention (5) Here, the present invention will describe some embodiments in detail. However, it should be noted that in addition to these explicit descriptions, the present invention can also be implemented in various other embodiments. In addition, the scope of the present invention is not limited to any embodiment, and it depends on the scope of the accompanying patent application. In addition, the parts of different components are not shown according to the actual scale, and the dimensions of related parts are enlarged, and the insignificant part is omitted 'to provide a clearer description and understanding of the present invention. • Reference in this specification to "one embodiment" or "an embodiment" means that a particular feature, structure, or characteristic described in this embodiment is included in at least one embodiment of the invention. Therefore, "an embodiment"-or "an embodiment" throughout this specification does not all mean the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. The design of the flash memory based on the breakdown of the gate oxide layer of the present invention was developed by the inventor of the present case and applied by the applicant of the present case. Related patents include: US Patent Application No. 0 9/9 5 5, 6 4 1 filed on August 18, 2001, entitled "Semiconductor Memory Cell _d Memory Array Using a Breakdown Phenomena in "An Ultra-Thin Dielectric", filed in the United States on December 17, 2001, and filed under the patent number 10/0 2 4, 3 2 7 and entitled "Senu conductor Memory Cell and Memory Array Using a Breakdown Phenomena in an Ultra-Thin Dielectric ", please request in 2001 200533069_; _ V. Description of the invention (U.S. Patent Application No. 0 9/9 8 2, 0 3 4 of October 17, 2007), the title of which is" Smart Card Having Non-Volatile Memory Formed From

"Logic Process", U.S. Patent Application No. \ 09 / 982,31 4 of October 17, 2001, entitled "Reprogrammable!

"Non-Volatile Oxide Memory", filed on April 26, 2002 丨 U.S. Patent Application No. 10/1 3 3,604, entitled "H i gh.!

Density Semiconductor Memory Cell and Memory Array

Using a Single Transistor. " The first figure is a schematic diagram of F PGA 100 in the present invention. Array 100 is a 2 by 2 # array, however, this array can be an array of any size. The array 1 0 0 includes I four-memory cell 102, and each cell includes a selection transistor | 104, a capacitor 106, and a switch 108. ： That is, 1 cell C crystal C body line recalls the first observation and inspection R come • ϋ. Accounted for the first intersection of black and black}, J such as line instance element or J line element cell crystal memory line is element also Bit C take R read line to the column connected to the connection of the poles and gates 4 ο of 1-14 body 10 crystal transistor selection

LB plant line R word line word line body crystal elective select this end 1 and connect the connection on the other side. The element system is connected to the line source 4 ο "the line position 10 2 and "Select" or 丨 to capacitor I (BL: the gate of switch 108 is also connected to the source of selection transistor 104, so it is located between the above source and one end of capacitor 106. This connection point is It is called switch control 200533069_____________________ V. Description of the invention (7) The control node, and the source and drain of the switch 108 are connected to other switches in the same row in a "daisy chain" manner. In the (program) step, a relatively large voltage will pass through the selected row and the selected column of capacitors 106, causing the gate oxide layer of capacitor 106 to collapse. In one embodiment of the present invention, the The other memory cell 1 0 2 in the figure is formed from the same cell 1 0 2 at the intersection of the row bit line CX and the column bit line R y, where the value of y is 1 to N, N Is the total number of columns, and the value of X is from 1 to M, and M is the total number of rows. ♦ Use the memory cell 10 2 for The programmed (programmed) component of FPGA 100 in the first figure has many advantages because this component can be made using many common complementary metal-oxide-semiconductor field-effect transistor (CMOS) processes. This process Only a single polycrystalline stone (ρ ο 1 ysi 1 ic ο η) deposition step is used, without adding any mask steps. This is different from the FPGA floating flash of the “floating gate” type | Usually requires at least two layers of polycrystalline silicon. This is also different from 1! Anti-fuse type FPGA, which requires special process steps. In addition, with the advancement of modern technology, the size of capacitors and transistors can be very small, for example丨 Such as 0.18 micron, 0.1 13 micron or even smaller line width processes, so that will be large 丨

I increases the density of the FPGA.丨 • Ranzhan only shows 2 by 2 FPGA 1 0 0, but in fact when using such as advanced: 0. 13 micron complementary metal oxide half field effect transistor logic manufacturing process, this FPGA will contain tens of thousands of crystals Cells, or even millions of unit cells,

Page 12 200533069_____ V. Description of the invention (8) The progress of the complementary metal-oxide-semiconductor half-field effect transistor logic process will enable a larger array of 1J. The second figure shows a partial configuration of FPGA 100, which is suitable for advanced complementary metal-oxide-semiconductor half-field-effect transistor logic process. The term “metal oxide half field effect transistor” referred to here generally refers to any gate material ^ including deposited polysilicon and other good conductors, and various types of gate dielectric layers, but it is not limited to stone oxide . For example, the above-mentioned dielectric layer may be any type of dielectric layer, such as an oxide or a nitride, which may cause a hard or soft collapse after a voltage is applied for a period of time. In one embodiment, the present invention uses a degree of approximately 50 A (50 A in a 0.5 micron process, 30 A in a 0.8 micron process, and 0.1 3 micron During the process, it is 20 A) thermally grown gate 丨 silicon oxide. ; The preferred configuration of FPGA 1 0 0 is grid (gr id), such as the line of C1 and C2

The I line is perpendicular to the alignment lines such as R 1 and R 2. The second figure shows two unit cells 102, arranged in an array of 1 by 2. As shown in the second figure, the first metal wire (M 1) is used to connect the gate of the above-mentioned switch (SW) to one end of the capacitor 106. In addition, the drain of the transistor (ST and 104) is selected. Connected to the zigzag line through the η + diffusion contact, metal No. 1, metal No. L (ν ia), and metal No. 2 (Μ 2). In addition, all components (selective transistor 104, capacitor 106, and switch 108) are formed from many layers of low-voltage (LV) oxide.

Page 13 200533069___ 5. Description of the invention (9) The operation of FPG A 1 0 0 will be described with reference to the third figure and reference voltages. Different applications or different process technologies may be used. Voltage. During programming (programming), various cells in FPGA 100 are exposed to one of four possible programmed voltage combinations, such as lines 3 0 1, 3 0 3, 3 0 5, 3 0 7, and the read voltage is displayed on lines 3 0 9, 3 1 1, 3 1 3, and 3 1 5. Suppose an FPGA cell 1 02 (cell 2 02 in the second figure is a general cell related to all the cells in FPGA 100) is selected to be stylized and located at the intersection of R 1 and C 1 That is, the selected memory cell 10 2 is located above the selected column and the selected row (SR / SC). As shown by line 301, the voltage on the selected word line R1 (not labeled Vwl or "voltage on word line") is 0 'and the voltage on bit line C1 (labeled as Vbl or "bit line" Voltage ") is 8 volts. In addition, the voltage on the selected readout bit line (labeled Vblr or i "Voltage on the readout bit line") is 3.3 volts. This set of voltages makes the “on” of the transistor 104 to be applied. It applies 0 volts from the word line i to one end of the capacitor 106, and the other end of the capacitor 106 is connected to a voltage value of 8 volts. Element line (V b 1), so the voltage through capacitor 106 is 8 volts. The oxidized gate of capacitor 106 is designed to collapse at this potential difference, so the FPGA cell is programmed. The details will be described below. When the oxide layer of capacitor 106 collapses, capacitor 106 will be converted into a resistor. It should be understood that the precise strength of the applied voltage is independent of the thickness and other factors of the gate oxidation. For example, for a complementary metal-oxygen half field effect of 0.1 3 microns

Page 14 200533069 V. Description of the invention (ίο) In the transistor process, the above gate oxide layer is usually thin, so a lower one is required.

The potential difference passes through the capacitor 106. I j | In the case where R1 and Cl are the selected columns and rows, consider the intersection of the selected column and the unselected row in the FPGA crystal | Cell 1 0 2 (SR / UC, such as R 1 and C2 ) 'S impact. As shown by line 30 5, the voltage of the word line R1: the value is 0 volts, the voltage value of the unselected read bit line (Vbl) is 0, and the voltage value on the unselected bit line C 2 Is 0. Since the transistor 104 is selected: The voltage on the gate is 0 volts, so the FPG A unit cell 102 is not programmed under these conditions. In the case where R1 and C1 are the selected columns and rows respectively, consider the

The impact of the intersection point (UR / SC, for example: i R 2 and C 1) of the selected row and the unselected row in cell 102. As shown by line 3 0 3, the voltage on the unselected word line R 2 is a value of 3.3 volts, the voltage value on the selected read bit line (Vbl r) above is 3.3 volts, and The voltage on the bit line C 1 is 8 volts. Because the voltage value of the read I bit line is 3.3 volts, the "on" of the transistor 104 is selected, and 3.3 volts on the word line is applied to one end of the capacitor 106. The other end of the capacitor is fixed to the above-mentioned bit line, or 8 volts in the case of |, so that the potential difference of 4.7 volts passes through the capacitor 106 丨 f gate oxide layer. The memory cell 1 0 2 is not designed for these situations. In the case where R1 and C1 are the selected columns and rows respectively, consider the

Page 15 200533069 V. Description of the invention (11) The impact of the intersection (UR / UC, for example: R 2 and C 2) of the unselected row and the unselected row in Cell 102. As shown by line 3 07, the voltage value on the unselected word line R 2 is 3.3 volts, the voltage value on the unselected read bit line (Vb 1 r) is 0 volts, and the above unselected bits The voltage value of line C 2 is 0 volts. Since the voltage on the gate of the selection transistor 104 is 0 volts, the above selection transistor is in the "off" position, so that one end of the capacitor 106 is in a floating state. Since the other end of the capacitor 106 is connected to the above-mentioned bit line, its voltage value is 0 volts, and the FPGA cell 102 is not programmed under these conditions. |

I is programmed in FPGA cell 102 by the breakdown of the gate oxide layer of capacitor 106; • Later, the physical characteristics of cell 102 have changed, especially capacitor 106 will become a resistive element. It should be noted that during stylization, although through the above

I The voltage value of the selected transistor oxide (ie, 3.3 volts on the gate of the selected transistor 10 4) is greater than the normal voltage (for 0 · 1 8 μm complementary metal-oxygen half | field effect transistor process and 1.8 volts), but because the programming time (usually about or less than a few seconds) is very short, this higher voltage will not cause the gate oxide layer of the selected transistor 104 to collapse. The reading of FPGA 100 is implemented in the following manner. Firstly, a read selection voltage of 1.8 volts is applied to the selected row bit line (SC), and a read selection voltage of 1.8 volts is applied to the above read selection bit line. (Vb 1 r ) And a voltage of 0 volts is applied to the selected column word line (SR). It should be noted that these voltages are for a typical 0.18 micron 丨 complementary metal-oxide-semiconductor half-field-effect transistor process, but in smaller and more advanced 丨

Page 16 200533069______ V. Description of the invention (12) In the process of complementary metal-oxide-semiconductor half field effect transistor, a lower voltage value is usually used. For example, in a 0.13 micron complementary metal-oxide-semiconductor field-effect transistor process, the read selection voltage value of the selected row bit line and the selected read line bit line is generally approximately 1.2 volts. Assume that R1 and C1 are the selected column and row (SC / SR), and F PG A 1 0 2 located at the intersection is stylized, as shown by line 3 0 9 and will be transmitted through bit line C 1 and 1 8 to 3 · 3 volts (read selection voltage) is applied to one end of capacitor 106. It should be noted that a higher bit line voltage will cause the bit line to induce a higher read current, and in addition, 1.8 volts will be applied to the select transistor through the read bit line 1 0 4 And a voltage of 0 volts through the word line R 1 to the drain of the selection transistor 104. This will make the selection-transistor 104 to the "on" state. However, even if the above-mentioned selection transistor is “on”, some resistance (r e s i s t a n c e) still exists in the above-mentioned selection transistor. In addition, there is also a voltage of 1.8 to 3.3 volts through the capacitor 106. If this capacitor is programmed, the leakage current (usually more than 10 microamperes) will be removed from the selected bit line. The word line flowing to the selected column above. In fact, the programmed capacitor 106 and the selection transistor 104 will form a voltage divider, and the node in this voltage divider is connected to the gate of the switch 108. The effect of this voltage divider i is that the voltage applied to the gate of the switch 108 will be sufficient to turn on the switch 108. f. The cell 102 is not pre-programmed, and the capacitor 106 will have a higher impedance than the selected transistor 104. In addition, because the selection transistor 104 is turned on, the 0 volt voltage of the word line is applied to the switch 108, which causes the switch 108 to be turned off.

Page 17 200533069 V. Description of the invention (13) In the case where R 1 and C 1 are the selected columns and rows for read operation, consider the selected row and unselected in FPGA cell 1 02 The impact at the intersection of the columns (UR / UC, for example: R 2 and C 1). As shown by line 3 1 1, a voltage of 1.8 to 3.3 volts (read selection voltage) is applied through bit line C 1 to one end of capacitor 106. In addition, 1.8 volts is applied to the gate of the selection transistor 104 through the read bit line, and 1.8 volts is applied to the source of the selection transistor 104 through the word line R 1, so This will lead to the selection of the transistor "off". • In the case where R 1 and C 1 are the selected columns and rows for read operations, consider the intersection of the unselected rows and selected columns in the FPGA cell 1 02 (SR / UC, for example: R 1 and C 2). As shown by line 3 1 3, 0 volts (read selection voltage) is applied to one terminal of capacitor 106 through bit line C 2. In addition, 0 volts are also applied to the gate of the selection transistor 104 through the read bit line, and 0 volts are applied to the drain / source of the selection transistor 104 through the word line R1. Under these circumstances, no current will flow from the word line to the bit line. jjR 1 and C 1 are the selected columns and rows for read operation f, considering the intersection of unselected rows and unselected columns in FPGA cell 1 02 • (UR / UC, for example: R 2 and C 2). As shown by line 3 15, 0 volts (read selection voltage) is applied to one terminal of capacitor 106 through bit line C 2. In addition, 0 volts are also applied to the selection transistor through the read bit line

Page 18 200533069 V. Description of the invention (14); the gate of 104, and 1.8 volts is applied to the drain / source of the selection transistor \ 10 through the word line R2. In these cases, since the selected element 104 is

In the off state, no current will flow from the word line to the bit line. i j 1

I During operation, the following voltages will be used. A zigzag line voltage of 0 volts is applied first, then a bit line voltage of 1.8 volts is applied, and a bit line read voltage of 0 to 0.8 volts is applied. The unselected read voltage (Vb 1 r) of 0 to 0.8 volts is used to operate the select transistor 1 04 in a weakly turned on state, because |. This only generates very little leakage current (approximately nA level). i # In the embodiment described in the first to third figures, the gate voltage of the switch 108 will usually be equal to or slightly less than Vcc (for the 0.8 micron complementary metal-oxide-semiconductor field-effect transistor with a manufacturing process of -1.1 8 volts), so the switch 108 can only pass Vcc-Vt, which will affect the speed performance of the FPGA circuit. In another embodiment, the switch 108 and the selection transistor 104 have a thicker gate oxide layer for the input / output element. For example, the thickness of the gate oxide layer of the switch 108 and the selection transistor 104 may be 60 A or more. The gate oxide layer of the capacitor 106 should be maintained at a general thickness for use in a special complementary metal-oxide-semiconductor field-effect transistor process. For example, a 0.8-micron complementary metal-oxide-semiconductor field-effect transistor process is 30. Α. The stylized and read voltage of this example is shown in the fourth figure. :

In another embodiment, during the read and stylized operations, the above-mentioned bit | line voltage may be biased to 3.3 volts (as in the first to third embodiments I i 1.8 Volt comparison). Switch 10 8 will have a 3.3 volt gate, so

Page 19 200533069 V. Description of the invention (15) 丨 Pass the voltage V c c completely including the additional driving gate voltage. As a result, the above | programmed switches will have very low impedance to improve speed performance. Although the above FPGAs have provided significant improvements in conventional technologies, the embodiments in Figures 5 through 11 can provide improvements including dynamic repeatability. For example, in the fifth figure, FPG A includes a write transistor (T w), a programming capacitor (Cp) generated by a plurality of gates on a thin gate oxide layer, and a circuit for controlling the programming logic. Control switching element (Tsw). The structure of the fifth figure is similar to that of the first figure, but when the above memory array is used as dynamic memory, its operator ® is not different, and the operation for non-volatile memory is the same as above. A new term used in the fifth figure, where Bw (same as Blr) is a bit line for writing, Bp (same as B 1) is a bit line for non-volatile programming, WL Is the word line, and Vg-sw is the switching gate voltage.

'I The most important one is before “hard” non-volatile programming (apply voltage to capacitor Cp to crash GoX), which can be written or stored in the switch gate and capacitor by constant writing or charging The charge in Cp, come |

I

The unit cell is used as dynamic memory. In this method, the above array can also be used as a memory element in the form of dynamic random access memory (DRAM), the details of the operation of the unit cell are shown in the sixth figure. The above writing or charging (rewriting; ref res h) is performed by selecting all the WL (column word line) lines and writing the bit line (Bw) line by line.

Page 20

I 200533069

5. Description of the invention (16) I line to complete. "1" is written or cleared by setting Vwl to a high voltage (Vcc), and "0" is written or cleared by setting Vwl to a low voltage (0V). The above is not selected. The trip voltage (Vbw) is always 0V. Therefore, as shown in the sixth figure, if "1" is to be written to the cell, bit line Bw is high voltage, bit line Bp is low voltage, and word line WL is high voltage. If "0" is to be written to the cell, the bit line Bw is a high voltage, the bit line Bp is a low voltage, and the word line WL is a low voltage. In a 0.1 8 micron semiconductor process, the voltage Vcc is 1.8 volts. In order to write the transistor T w (usually an N-type metal-oxide-semiconductor transistor), the element “1” is passed. In some embodiments, a lower voltage can be used in the FPGA logic circuit. Vdd (for example between 1. 8 volts and 1.2 volts) '\ to achieve higher rates and lower power consumption. For example, suppose the memory array in the fifth figure is used as dynamic memory and writes dynamic data. For example, in this operation, the "bit stream" for a specific row (this bit stream can be the FPGA's switch control data) is externally or on-chip erasable Programmable Read Only Memory (EPROM) or Flash memory (f 1 ash) is loaded into the WL shift register (shiftregister; not shown in the figure i). If there are 10 2 word lines WL s (column), then 10 2 4 bit data will be read into the 10 2 4 bit shift register. Then, select

The voltage of Bw in the selected row will be Vcc, and the 104 bits in the above row will be written into the above shift register at the same time.

I

"1" is written and "0" is written at 0 volts. I

Page 21 200533069 V. Description of the invention (17) After writing (simultaneously charging) the first line, the bit stream used for the second line will be loaded into the above-mentioned shift register, and the above-mentioned second line ( Bw) will be selected and charged, and this operation is repeated line by line until the last line is written or charged. The above procedure will be repeated again from the first line, the second line, etc., so the above lines are continuously charged in a sequential manner. The time to write or charge a line is between a few nanoseconds (nS) to a few microseconds (uS). With 10 2 4 lines, the charging cycle time will be between a few microseconds and a few milliseconds. In one embodiment, the charge stored on the switching gate will not decrease by more than 10% in the paralysis range at this time. In the writing or refreshing process, the waveform has a time sequence 1j (sequence) above the word line WL and the write bit line Bw, and the time sequence is designed to avoid clearing. Data stored on the gate of the control switch T sw. In particular, the word line WL with "1" should become Vcc before the bit line Bw (Vblr) becomes Vc c. This Vc c voltage will turn on the N-type metal-oxide half field effect transistor (NM0S) for charging ) Switch (Tw). In addition, before the word line WL drops to 0 volts, the bit line Bw (Vblr) should already be 0 | i special, in order to turn off the above-mentioned selection of the N-type metal-oxygen half field effect transistor, as shown in the seventh figure | The writing or charging of "0" is similar to the above method, but the voltage -Vwl is 0 volts instead of Vcc. Moreover, during the period between successive charging lines, Vwl is set to a bias voltage of Vwb (low) to reduce leakage from the above-mentioned T w source drain (I d) when using a deep sub-micron process. 〇ff)

Page 22 200533069 V. Leakage current of invention description (18). It should be noted that because the writing or charging process (refreshing) is completed line by line, there is no need for a special decoding circuit for the line (bit line) in this charging process. Instead, a simple closed loop can be used. Bit register chain. The charging or overwriting used by the dynamic memory of the present invention does not require reading. The reading of the invention's dynamic memory usually destroys the stored data or interferes with the gate voltage of the controlled switch. This is paralyzed with general dynamic random access memory, which must first read out data or store a charge, and then charge it to store data. This will prevent the dynamic random access memory (DRAM) cell from being used directly in the FPGA control switch. This must be in a stable state to provide an "off" or "on" switch. The dual characteristics of the memory array described above can be used in many applications. The ability to serve as both dynamic and non-volatile memory will help prototyping applications. In the above application, the user needs to program the FPGA cell multiple times, and after completing the design, the user can permanently program F P G A as above. As shown above, the use of continuous writing to charge the above-mentioned switch memory requires the constant reading of the design bitmap (d e s i g n b i t m a p) from non-volatile memory (external or internal). For non-high density structures

Page 23 200533069___ 5. Description of the invention (19) For large FPGA chips with volatile memory, access speed, data transfer speed, charging cycle time, and input / output errors will be limiting factors. In order to solve these problems, according to another embodiment of the present invention, a parallel small sensing element (Ts), a diode (Td), and a sensing bit line (Bs) are added, as shown in FIG. This embodiment eliminates the need for continuous charging from non-volatile memory and replaces it with self-refreshing. The self-charging procedure has two operating steps: sensing and charging. During the sensing operation, all selected zigzag lines WLs will be precharged to a high voltage (~ V cc) and the selected sensing line (B s) will be reduced to a low voltage (between 0 volts and 0 volts). V cc / 2). In addition, all unselected bit lines B s will be maintained or precharged to a high voltage (between V cc-V t to V cc) to prevent any leakage current from flowing from the WL line to the unselected BS line. 1 ”cell (positive charge is stored and T s is on). In this case, only one unit cell on one word line WL will be selected. If the selected FPGA cell is in the "1" state, the sensing element (Ts) is turned on so that it can conduct the sensing electric current (Isn), and the word line WL is reduced to a low voltage state. If the above _FPGA cell is in the "0" (off) state, the above sensing element is turned off, and no current is passed, and the word line WL will remain in a high voltage state. Therefore, the sensing and charging circuit can sense and memorize (lock data) the state of the unit cell on the selected row and charge it. For sensing,

Page 24 200533069____ — V. Description of the invention (20) The bias state of writing and non-volatile programming is shown in Figure 8, and Figure 9 is a top view of the layout. It should be noted that the diode (Td) can be placed on either side of the sensing element (Ts) with the same polarity, and this diode can also be placed on the opposite electrode with a proper bias configuration 'to prevent Leakage current on unselected row. It should also be noted that the diode Td can be manufactured by using a gate diode of a metal-oxide-semiconductor field-effect transistor whose gate is connected to a source or a drain, or by using a P-N interface. This FPGA cell array can also be generated using P-type metal-oxide-semiconductor field-effect transistor (PM0S) elements placed on N-parameters or N-shaped substrates. As shown in the tenth to eleventh figures, the cell array without switching elements can also be used as a dynamic random access memory (DRAM) based on a standard complementary metal-oxide-semiconductor field-effect transistor process, but this sensing circuit will greatly To simplify. The above diode can be connected to any side of the sensing element to prevent a good leakage current from unselected elements. And this diode can be generated by a gate metal-oxide half field effect transistor element, which can also be borrowed. By P-type metal-oxide half field effect transistor (PM0S) element

The above embodiments show various structures for dual-mode memory, that is, non-volatile and dynamic memory. In another embodiment, a single (s ο 1 e 1 y) dynamic memory array can be formed. As shown in Figure 12A, by removing

Page 25, 200533069_ V. Description of the invention (21): The above capacitor (Cp) and program bit line (Bp) will be generated as dynamics: The structure of the state memory 'in addition, the electric valley is removed as Cp' crystal Cell size can be significantly reduced. The operation here is still the same as described above. Figure 12B is a top view of the circuit of Figure 12A. As shown in Figure 12A, when the Tw element is in the off state, the above-mentioned floating-point (FP) node will dynamically store the charge. In addition, this FP node can also be connected to the NM0S or PM0S gate to generate the FPGA for use. The dynamics of the chip can be programmed on and off. The above-mentioned FP node can be used as the input control of an inverter, and can be used in a look-up table (LUT) as it is used in most SRAM-based FPGAs. This extended application will be detailed below.

I

I NM0S or PM0S transistors are controlled by FP polysilicon gates, or inverters combined with Tsw (NM0S or PM0S or inverter), Ts and FP interface capacitors will be used as "capacitors" of dynamic memory ". The combination of F P and the polycrystalline silicon gate of the transistor (NM0S or PMOS or Ts) is usually sufficient to maintain the charge (signal), so it only needs to be charged at a relatively low frequency. Figures 13A, 13B, and 13C show the FP nodes connected to the NMOS transistor, the 0S transistor, and the inverter (ie, the switch Tsw). "XDM" stands for super dynamic memory, and "X" also has the meaning of using thin gate ^ flex oxide capacitor as a memory element, or represents the collapse of non-volatile memory or memory or storing dynamic charge. i

Page 26 200533069___ 5. Description of the invention (22) In another embodiment of the present invention, the stylized capacitor C p may be located on the left side of the unit cell. Figure 5A is the same for non-volatile operation. The retention (r e t e n t i ο η) of the programmable gate capacitor C p added with F P makes the above unit cell non-volatile. The memory array in Fig. 12 can be changed by removing the FPGA switch Tsw. The results are shown in Figs. 15A and 15B, which are roughly three-transistor dynamic RAM memory. In another application, as shown in Figure 16, a dedicated read option # 语 线 （WLs) will be added, so that the write and read functions can be controlled separately. This application is the same as the earlier 3T DRAM cell. For reference, please refer to the second edition of "Analysis and Design of Digital Integrated Circuits, Semiconductor Memories" by DA Hodg-es and H. Jackson. Raw H i 1 1 was published in 1988 and is similar except that a special capacitor is connected to the node to store the charge. Ts or Tsw's gate I and FP interface are used as this special capacitor.丨 This application is usually suitable for deep sub-micron semiconductor process technology (< 0.25 micron &, where the gate capacitance of Ts can be due to the gate oxide thickness (Go X is 40-50 I for 0.2 5 micron process, 30-3 5 angstroms for 0.1 8 micron process, 20-2 3. Angstroms for 0.1 3 micron process, 16-19 angstroms for 90 nanometer process, etc.) It is reduced enough to be formed sufficiently. Furthermore, it should be noted that the transistor T r can also be connected between D 3 and 0.

Page 27 200533069 V. Description of the invention (23) The cell array of Figure 16A writes and reads one column after another sequentially, and inputs and outputs data from the above bit line. It should be understood that the names of W L and B L are interchangeable. In any example, this data line can be input to the drain of T w and output from the drain of T r. Programmable gate capacitor Cp can also be added to the FP to make it non-volatile, which is based on the use of dynamic memory to control the phase of a programmable switch or inverter. Same idea, and can have various changes . • Another embodiment of the invention is shown in Figures 17A to 17B. In this embodiment, the unit cell structure of the above memory is generated in a relatively small size. In addition, the memory and the FPGA switch can be turned on by continuously writing the structure data to the floating point without outputting the sensing data. This structure can come from a variety of sources, such as on-chip memory, external SRAM, flash memory, or one-time programmable (OTP) memory. In Figure 17A, only two transistors are required for each memory cell. It should be noted that the voltage on the word line for writing "0" (V1 b) or standby is a bias voltage, and this bias voltage is within the range of the threshold voltage (V t) of the selection element (Tw) ▲ To provide subcritical leakage. For advanced process technology, the thickness of the core gate oxide layer is very thin (20 angstroms for a 0.13 micron process and 17 angstroms for a 90 nanometer process). Therefore, the tunneling current of the gate dielectric value described above can make

Page 28 200533069__ — V. Description of the invention (24) The charge is kept for a very short time, which requires relatively high frequency charging. Another embodiment uses input / output form elements in the switching element (T sw) (30 angstroms for 1.8 volts, 50 angstroms for 2.5 volts and 70 angstroms for 3.3 volts) In order to prevent leakage of the gate through the tunnel, in addition, PM0S thin inter-electrode oxidation elements can be used to reduce the gate leakage. \ | Although during the operation of the FPGA chip, the electricity stored in the FP cannot be sensed: it needs a floating point with a relatively stable potential. For "on":. "1" and for "off" it is "0" ", But it can still be read destructively to confirm that the array is functioning properly.丨

I The following points are based on observations of various embodiments of the present invention!!

1. Floating point (FP) can be achieved by turning off Tw, and it can also be used to control the polysilicon gate of I NM0S or PM0S, or the input terminal of CMOS inverter.丨 2. Non-zero bias Vwb (~ Vt) is provided to the drain of Tw (assuming the source of Ts 丨 is connected to the polysilicon gate of Ts) to reduce the above-mentioned write transistor (Tw 1) times Critical drain leakage (sub-thresh ο 1 d 1 eakage), while increasing the charge storage time or extending the above charging cycle. 3. Data is written and read from the column word line.丨 & W L and B L s can be exchanged with each other.丨 5. Floating point (f 1 〇 a t i n g η 〇 d e) can be used to control the switching element gate to generate a programmable switch applied to FPGA. 6. In order to completely pass the logic level and reduce the influence of the voltage coupled from the switching element, the potential of the floating node (V f p) should be higher than the switching source or drain voltage.

Page 29 200533069 V. Description of the invention (25) Voltage (usually logic Vcc). In one embodiment, V fp should be higher than (1 + C R) * V c c + V t, where “C R” is the coupling ratio from the switch gate to the floating node.丨 7. Writing the row to the bit line bit can excite to a high voltage to completely pass the word line voltage to the floating node to reach the required V f g. 8. The implantation of NLDD will be blocked in the transistor Td, so there will be no gate overlap between the polysilicon gate and the n + S / D diffusion. After the Cp is programmed, an inverse diode between the floating node and the program bit line (Bp) to the dynamic memory will be generated, even after the unit cell is programmed into non-volatile memory. Still works. The dynamic memory cell and array include three transistors (T w, T s, T d |), a word line (WL), and two bit lines BL (BW and BS), and i and remove the capacitor Cp and bit line Bp to reduce the area of the unit cell. 1 0. The FPG A switch is removed from the FPG A cell, making it a pure dynamic memory and memory array based on a pure CMOS logic process. Normal thin gate oxidation | Capacitors are used to store dynamic information data (charges), while floating nodes control transistors, and diodes are used to read data without destroying the stored data. 11. The dynamic memory cell includes Wlr, Wlw, B1, and GND, and is normal: The thin gate is used as a capacitor to store dynamic charges. The present invention has been described above with reference to the preferred embodiments, but it is not intended to limit the scope of patent rights claimed by the present invention. The scope of patent protection shall depend on the scope of the attached patent application and its equivalent fields. Those who are familiar with the art in this field

Page 30 200533069__ V. Description of the invention (26) Changes or modifications made without departing from the spirit or scope of this patent are all equivalent changes or designs made in the spirit disclosed by the present invention and should be included in the following applications Within the scope of the patent.

Page 31 200533069 Brief description of the drawings [Simplified description of the drawings] The first diagram is a schematic circuit diagram of a part of a field programmable gate array of the present invention. The second figure is a partial configuration diagram of the field programmable gate array of the first figure. The third figure shows the field programmable gate array voltmeters operating the first to third figures. The fourth figure shows another embodiment of a field programmable gate array cell. The fifth figure is a partial circuit diagram of another field programmable gate array of the present invention. Figure 6 shows the field programmable gate array cell voltmeter operating Figure 5-c. The seventh diagram shows the timing chart of the fifth-c diagram storing data on the unit cell. # 八 图 is a partial schematic view of another field programmable gate array of the present invention. The ninth figure is a top view of the eighth figure and the circuit. The tenth figure is a schematic diagram of a part of the dynamic memory array of the present invention. The eleventh figure is a circuit top view of the tenth figure. Figure 12A is a schematic diagram of forming a dynamic memory array according to the present invention. Figure 12B is a top view of the circuit of Figure 12A. Figures 13A-13C show the use of a floating point node and a capacitor to control N-type metal-oxide-semiconductor field-effect transistor (NM0S), P-type metal-oxide-semiconductor field-effect transistor (PM0S), and inverter, respectively. The four A-fourteen C diagrams show the use of floating point nodes and capacitors to control oxygen half field effect transistors, P-type metal oxide half field effect transistors and inverters, respectively. Fig. 15A is a schematic diagram of a dynamic memory array according to another embodiment of the present invention.

Page 32 200533069 ~ j Schematic description Figure 15B is a top view of the circuit of Figure 15A. Fig. 16 is a schematic diagram of a dynamic memory array according to another embodiment of the present invention. Fig. 17A is a schematic diagram of another field programmable gate array of the present invention, which is a real field programmable gate array switch. Figure 17B is the layout of the field programmable gate array of Figure 17A.丨 [Description of main component symbols]. Field programmable gate array 100 Memory cell 102 _ i _ Selective transistor 104 Capacitor 106-| Switch 1 0 8 Partial configuration diagram 2 0 0 | Line 3 (Π, 3 0 3 , 3 0 5, 3 0 7, 3 0 9, 3 1 Bu 3 1 3, 3 1 5, 3 1 7, | 4 (Π, 4 0 3, 4 0 5, 4 0 7, 4 0 9, 41 413, 415, 417 j

Claims (1)

200533069_ VI. Scope of patent application 1. A unit cell can be used as a dynamic memory unit cell for storing data or a field programmable gate array (FPGA) unit cell for programming. The unit cell is used to In an array of bit lines, read bit lines, and column word lines, the unit cell includes: a capacitor having a first end and a second end, the first end being connected to a row of bit lines, The second terminal is connected to a switch control node; a selection transistor has a gate, a source, and a drain, wherein the gate is connected to a write bit line, and the source is connected to the switch Control nodes, and the drain is connected to the word line; and: a switch controlled by the switch control node, wherein the switch control node 丨 _! ♦ represents a voltage of 0 or 1 to store data. 2. For example, the unit cell of the scope of the patent application, wherein the switch is a metal-oxide-semiconductor field-effect transistor (MOSFET), and one of the metal-oxide-semiconductor field-effect transistors is connected to This switch controls the node. 1 3. For example, the unit cell of the first scope of the patent application, wherein the data is located on the control node of the switch i I by turning on the selection transistor and placing the data on the word line of the column. I I j is the unit cell of item 1 of the patent application, wherein the first terminal of the capacitor, the gate of the selection transistor, and one of the switches are formed from the same polycrystalline silicon layer. Page 34 200533069__ VI. Scope of patent application 5. —A method for operating a dual-mode cell connected to a column of word lines, a line of write lines, and a bit line that reads, wherein the cell includes: a capacitor having A first terminal and a second terminal, the first terminal is connected to the row of write bit lines, and the second terminal is connected to a switch control node; a selection transistor having a gate, a source and A drain connected to the read bit line, the source connected to the switch control node, and the drain connected to a column of word lines; and a switch controlled by the switch control node; the The steps of the method include: when the unit cell is a programmable gate array (FPGA) unit cell and is programmed ... the image provides a first voltage to the row of bit lines; (2) turning on the selection transistor ; And (3) providing a second voltage to a selected word line, wherein the first voltage and the second voltage form a potential difference across the capacitor so that the dielectric layer of the capacitor collapses and becomes A resistance element; when the When the unit cell is a dynamic memory unit cell that stores data: (1) Turn on the selection transistor; (2) Provide the data to the switch control node through the word line, where the switch control node is represented by 0 Or 1 voltage to store data. For example, the method of claiming the scope of patent application, the steps of which further include charging the data periodically when the unit cell acts as a dynamic memory unit. 7. The method of the scope of application claiming the domain, in which Except the column of words on the line Page 35 200533069 -—.............. 1 --- * — t 6. Turn off the selection transistor before applying for the patent scope i. I 8. —The seed cell can be used as a dynamic memory cell for storing data or a field programmable gate array cell for programming. The cell system is used to have row bit lines, read In an array of bit lines and word lines, the unit cell includes: a capacitor having a first end and a second end, the first end being connected to a row of bit lines (Bp), and the first The two terminals are connected to a switching control node; I is a selection transistor having a gate, a source, and a drain, wherein the | gate is connected to the write bit line (Bw), and the source is connected to The switch control calls the node and the drain is connected to a row of word lines (WL); | A switch is controlled by the switch control node, wherein the switch control node stores data with a voltage of 0 or 1 And a sensing element for determining the voltage on the switch control node. 9. For example, the unit cell of the eighth patent application, wherein the switch is a metal-oxide half-field-effect transistor field-effect transistor (M0SFET), and the metal-oxide half-field-effect transistor i! The gate is connected to the switch control node. i t ^. The unit cell of item 8 in the scope of patent application, wherein the data is located on the on / off control node by turning on the selected i crystal and placing the data on the word line. 1 | 1 1. If the unit cell of item 8 of the scope of patent application, wherein the first of the capacitor: P.36 200533069__ VI. Scope of patent application The polysilicon layer of the same terminal of the selection transistor and the gate of one of the switches is the same. 1 2. If the unit cell of item 8 of the scope of patent application, wherein the sensing element is a crystal, it has a gate connected to the switch control node, a drain connected to a bit line (Bs), and the word The source of the speech line (WL) 1 3. If the unit cell of item 12 of the patent application scope, it further includes a two-pole I connected to the sensing element and located between the word line of the word and the sensing bit line. . «1 4. A unit cell that can be used as a dynamic memory cell for storing data. The unit cell is used to have an array of row bit lines, read bit lines, and column words. The unit cell includes: A capacitor having a first terminal and a second terminal, wherein the first terminal is connected to a row of bit lines (Bp), the second terminal is connected to a switch control node, and the switch control node stores the data; The crystal (T w) has a gate, a source, and a gate, wherein the gate is connected to the write bit line (Bw), the source is connected to a control node, and the drain is connected to a column of words. Speech lines; and _ • ^ sensing elements, which are used to determine the data located on the switch control node 15. For example, the unit cell of item 14 in the scope of patent application, where the transistor I is turned on and the data is set. On the word line of the column, the data is located at an inductive pole, |, i of the string, the slang line is connected to, and the pole, to the "select the open Page 37 200533069_ VI. Scope of Patent Application Above the control node. 16. According to the unit cell of claim 14, wherein the first i terminal of the capacitor, the gate of the selection transistor, and a gate of the switch are formed from a polycrystalline silicon layer with the same i. 17. The unit cell according to item 14 of the patent application scope, wherein the sensing element is a transistor having a gate connected to the switch control node and a drain connected to a sensing ΐ bit line. ΐ 6. If the unit cell of item 17 in the patent application scope further includes a diode, the string is connected to the sensing element and is located between the word line and the sensing bit line of the mushroom. Page 38