TW200524071A - Clamping and de-clamping semiconductor wafers on an electrostatic chuck using wafer inertial confinement by applying a single-phase square wave AC clamping voltage - Google Patents
Clamping and de-clamping semiconductor wafers on an electrostatic chuck using wafer inertial confinement by applying a single-phase square wave AC clamping voltage Download PDFInfo
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- TW200524071A TW200524071A TW093127134A TW93127134A TW200524071A TW 200524071 A TW200524071 A TW 200524071A TW 093127134 A TW093127134 A TW 093127134A TW 93127134 A TW93127134 A TW 93127134A TW 200524071 A TW200524071 A TW 200524071A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/687—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6831—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using electrostatic chucks
- H01L21/6833—Details of electrostatic chucks
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02N—ELECTRIC MACHINES NOT OTHERWISE PROVIDED FOR
- H02N13/00—Clutches or holding devices using electrostatic attraction, e.g. using Johnson-Rahbek effect
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- Condensed Matter Physics & Semiconductors (AREA)
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- Manufacturing & Machinery (AREA)
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Abstract
Description
200524071 九、發明說明: 〔與本案相關之申請案〕 本申請案係相關於美國申請案序號第10/642939號,於 2003年8月18日申請,(代理人之檔案編號〇2-IMp-〇56)標題 為 “MEMS Based Multi-P〇lar Electrostatic chuck”,其在此合 併作為參考,本案並且相關於美國申請案序號第1〇/66118〇 唬,於2003年9月12曰申請,代理人之檔案編號 03-IMP-002 ,標題為 “Clamping and De-Ciamping200524071 IX. Description of the invention: [Applications related to this case] This application is related to US application No. 10/642939, which was filed on August 18, 2003. (Agent's file number 02-IMp- 〇56) The title is "MEMS Based Multi-Polar Electrostatic Chuck", which is incorporated herein by reference. This case is related to the US application No. 10/66118, which was filed on September 12, 2003. Person's profile number 03-IMP-002, titled "Clamping and De-Ciamping
Semiconductor Wafers on a J-R Electrostatic Chuck Having a Micromachined Surface by Using Force Delay in Applying aSemiconductor Wafers on a J-R Electrostatic Chuck Having a Micromachined Surface by Using Force Delay in Applying a
Single-Phase Square Wave AC Clamping Voltage”。 【發明所屬之技術領域】 本發明大致上係相關於半導體處理系統,並且特別相關 於一種方法,其利用施加單一相位方波交流箝制電壓箝制及 解箝制在利用晶圓慣性限制之靜電夾盤上的半導體晶圓。 【先前技術】 靜電夾盤(ESC)已經利用在根據基於電漿或是真空之半 導體製程一段長時間,該種半導體製程係例如蝕刻,化學拋 光(CVD)以及離子植入等等。靜電夾盤包含無邊緣排斥以及晶 圓溫度控制的能力,已經證明在處理半導體基板或是晶圓上 ⑽如石夕晶圓)具有相t的價值。一種典型的靜電夹盤’舉例而 。,包含置放於一個導電電極上的一個介電質層,其中該半 200524071 導體晶圓係置放在一個靜電夾盤的表面上(例如,該晶圓係置 放於一個介電質層的表面)。在半導體處理過程中(例如電漿處 理),一個箝制電壓係通常施加在晶圓以及電極之間,其中該 晶圓係由靜電力箝制而相對於夾盤表面。另外,晶圓可以藉 由導入一種氣體例如氦氣而冷卻,並且提供在晶圓以及介電 質層。晶圓的溫度可以由調整在晶圓以及介電質層之間的反 向壓力而控制。 解箝制或是將晶圓從夾盤表面解除貼附的狀態,然而, 係一種在許多靜電夾盤申請案中都有的考量。舉例而言,在 箝制電愿被關閉之後,該晶圓一般“黏著,,於夹盤表面—段相 當長的時間,其中該晶圓不能被傳統晶圓升起裝置移除(例 如’經過靜電夾盤延伸之接腳係操作用於從介電質層表面舉 起晶圓)。此種晶圓解箝制問題會降低整個製程的生產率。一 般相信晶圓·解箝制題發生在當由箝制電壓所感應之殘餘 電荷遺留在介電質層或是晶圓表面上,因此導致不必要的電 場以及箝制力。根據-個電荷移動模型,殘餘電荷係在箱制 過程中由電荷的移動以及累積造成,其中電荷累積在介電質 表面並且/或是晶圓反向(例如,當晶圓表面包含隔離層)。 舉例而言,一個RC fl存問當童fm…丄 了 Π吊數了以被用於特徵化充電次數 /放電次數,該些次數係對應於一個 — 7㈣個時間置,係通常需要個別 罐是解箝制該晶圓之時間量。該時間常數係由介電質層 之體積電阻以及在晶圓以及介雷矣 你日_及;丨電表面之間的間隙電容乘積所 200524071 決定,亦即 (1) RC = - p(dielectnc)e0sr ^ielectric^ r gap 電夤層之電阻,cgi7p是晶圓以及夾盤表面 之間的間隙電容,7 •、人 P (Ae/ecirzc)介電質層之體積電阻,是 了工;丨電㊉數 ε r係該間隙的介電質常數, 係’I電質層的厚度,而⑽是指在介電表面以及晶圓表面之 門的距離|例而言,對於_個_般的平板靜電夾盤,如果 假設 p (心/伽今1〇15q,,“= 8 85χΐ(Γ】4]ρ/⑽, d(dieleciric) = 〇.2 mrv, ,、,n ^ a mm,以及客叩=3 μιη,就會得出常數 ' ; 心此項常數係屬非常長的充電/放電時間,其代 表的是如果箝制時間比测秒還要久,該項解箝制時間將 會至少接近於5900秒。 先别已經揭露报多種用於減輕因為使用靜電夾盤而產生 的晶圓解箝制問題。舉例而言,—種習知技術涉及提供一個 在晶圓從靜電夾盤上移除之前施加反向㈣,因此減輕了殘 留的吸引力。然而此種反向電壓’係一般高於該箝制電壓15 至2倍’並且該解箝制時間仍然相當長。另一種習知技術涉 及提供-個低頻正弦交流電壓以用於產生具有受控的振幅與 相位的正弦波場。然而此種低頻正弦交流電壓—般提供較低 的箝制力量,也造成相當長的殘餘箝制時間。 其他用於解箝制晶圓之習知技術包含決定一個相對極性 200524071 直流駆動電壓,其施加在電極上以用於取消殘餘靜電電荷的 握持效果,並且因此可以釋放晶圓。然而一般而言,此種技 術涉及相當複雜的計時電路,並且並未考慮對於晶圓慣性效 應、從冷卻氣體的反向壓力,或是靜電夾盤的整體RC時間常 數而呈現最佳化。 因此,在此項技術中需要一種用於箝制以及解箝制之系 統與方法,其可以對晶圓慣性效應,靜電夾盤之物理性質與 電力性質呈現最佳化狀態。 ' 【發明内容】 以下内容呈現一種本發 本發明之某些層面的基礎了解。此項摘要並不是本發明的廣 泛概述,也不是意欲驗證本發明之關鍵要件,亦不是闡述本 發明之範°其目的係以-種簡化的形式表示本發明之一些 觀點,一種對於稍後會呈現的更詳細敘述之内容的前言。一 本發明克服了先前技術上的挑戰,其藉由提供 相位方波交流電壓至一靜電夾盤(ESC),舉例而言,1中一個 方=«之極性轉換速度係較_個半導體晶圓被箝制之慣性 反應㈣為快。相㈣不同的f知靜電夹盤,本發明利用一 個相對簡單並且不昂貴的裝置。相較於_些習 的f圖盡可能快速的移除殘餘電荷,本發明之方二= 係设汁以整體預防殘餘電荷為第— /… “曰m ^ 馒先。較佳的方法係如同 屬性限制”,並且引用一種方波單一相位交流籍制電 200524071 壓’其可被施加至-個單極或是—個多極電極靜電夾盤。夢 由调整施加電壓的脈波寬度以及脈波上升時間,解箝制時; 可以進一步的減至最低。 根據本發明之—個層面,本方法可以應用在平板靜電失 皿以及根據Μ聽的靜電夾盤,其中該半導體晶圓係經由一 :晶圓慣性限制機制被箝制以及解箝制。經由控制例如一個 早=相位方波交流信號的上升時間,脈波寬度以及脈波重複 ^員率(prf)之參數,該半導體晶圓可以在電壓轉換期間至少部 分係被晶圓的慣性質量牢靠的箝制。並且根據本發明另—個 不範性層面,該晶圓可以在箝制電壓被關閉後幾乎瞬間被解 柑制’至少-部分原因是因為在箝制期間脈波寬度係足夠短 以至於可以顯著的預防電荷遷徙並累積至晶圓之介電前表面 並且/或是後表面。 根據本發明另一示範性層面,該靜電夹盤可以包含不同 形式的電極圖樣,其包含,舉例而言,用於一個電激環境系 統之-個簡單的單—極結構或是用於真空環境系統的—個簡 :的D形狀雙極結構。並且,本發明並不需要複雜的電極圖 樣或是複雜的信號計時控制電子電路。 為了達到上述以及相關的目的,本發明包含在之後完整 敘述的特徵’該些特徵並且會在後述φ請專·圍中特別提 =。下列的敘述以及提出的所附圖式特別詳細顯示本發明之 實施例。然而該些實施例係象徵性的,少數不同的方式可以 200524071 實現本發明之原則。I發明其他目的,優點以及顯著的特徵 將從以下本發明詳細敘述中結合圖式一起考慮而變得更加明 顯。 【實施方式】"Single-Phase Square Wave AC Clamping Voltage". [Technical Field of the Invention] The present invention is generally related to semiconductor processing systems, and is particularly related to a method that uses a single-phase square-wave AC clamping voltage to clamp and unclamp in Semiconductor wafers on electrostatic chucks utilizing wafer inertia limitation. [Prior Art] Electrostatic chucks (ESC) have been used for a long time based on plasma or vacuum-based semiconductor processes such as etching, Chemical polishing (CVD), ion implantation, etc. Electrostatic chucks include the ability of non-edge repulsion and wafer temperature control, which has proven to be of value in processing semiconductor substrates or wafers such as Shixi wafers. An example of a typical electrostatic chuck includes a dielectric layer placed on a conductive electrode, wherein the half 200524071 conductor wafer is placed on the surface of an electrostatic chuck (for example, the crystal The circle system is placed on the surface of a dielectric layer). During semiconductor processing (such as plasma processing), a clamp The voltage system is usually applied between the wafer and the electrode, wherein the wafer is clamped by electrostatic force with respect to the surface of the chuck. In addition, the wafer can be cooled by introducing a gas such as helium and provided between the wafer and the wafer. Dielectric layer. The temperature of the wafer can be controlled by adjusting the reverse pressure between the wafer and the dielectric layer. Unclamped or unattached wafer from the surface of the chuck, however, it is a kind of Considered in many applications for electrostatic chucks. For example, after clamping power is turned off, the wafer generally "sticks to the chuck surface for a considerable period of time, where the wafer cannot be Conventional wafer lifter removal (for example, 'pins extended through electrostatic chucks are used to lift the wafer from the surface of the dielectric layer). Such wafer de-clamping problems can reduce the productivity of the entire process. It is generally believed that the wafer-unclamping problem occurs when the residual charge induced by the clamping voltage is left on the dielectric layer or the wafer surface, resulting in unnecessary electric fields and clamping force. According to a charge movement model, the residual charge is caused by the movement and accumulation of charges during the box making process, where the charges are accumulated on the surface of the dielectric and / or the wafer is reversed (for example, when the wafer surface contains an isolation layer) . For example, an RC fl memory is used when the child fm ... has been counted to be used to characterize the number of charging / discharging times. These times correspond to one-7 time slots, which usually require individual tanks to be The amount of time to unclamp the wafer. The time constant is determined by the volume resistance of the dielectric layer and the wafer and the dielectric layer, and the space capacitance product between the electrical surface 200524071, which is (1) RC =-p (dielectnc) e0sr ^ ielectric ^ r gap The resistance of the electric layer, cgi7p is the gap capacitance between the wafer and the surface of the chuck, 7 • The volume resistance of the dielectric layer of P (Ae / ecirzc), is the work; The number ㊉r is the dielectric constant of the gap, is the thickness of the dielectric layer, and I is the distance between the gate on the dielectric surface and the wafer surface. For example, for a flat plate For electrostatic chucks, if p (heart / Gajin 1015q, "= 8 85χΐ (Γ) 4] ρ / ⑽, d (dieleciric) = 0.2 mrv, ,,, n ^ a mm, and customer叩 = 3 μιη, we will get the constant '; This constant is a very long charging / discharging time, which means that if the clamping time is longer than the measurement second, the de-clamping time will be at least close to 5900 seconds. Don't disclose a number of reports to alleviate wafer de-clamping problems caused by the use of electrostatic chucks. For example,- The technology involves providing a reverse chirp that is applied before the wafer is removed from the electrostatic chuck, thereby reducing the residual attractive force. However, this reverse voltage is 'generally 15 to 2 times higher than the clamping voltage' and the solution The clamping time is still quite long. Another conventional technique involves providing a low-frequency sinusoidal AC voltage for generating a sine wave field with controlled amplitude and phase. However, this low-frequency sinusoidal AC voltage generally provides lower clamping force. This also results in considerable residual clamping time. Other conventional techniques for de-clamping wafers include determining a relative polarity 200524071 DC oscillating voltage, which is applied to the electrode to cancel the holding effect of the residual electrostatic charge, and therefore The wafer can be released. However, in general, this technology involves a fairly complex timing circuit and does not take into account the effects of wafer inertia, the reverse pressure from the cooling gas, or the overall RC time constant of the electrostatic chuck Therefore, there is a need in the art for a system and method for clamping and de-clamping that can The circular inertia effect, the physical and electric properties of the electrostatic chuck are optimized. '[Abstract] The following content presents a basic understanding of some aspects of the invention. This summary is not an extensive overview of the invention It is not intended to verify the key elements of the present invention, nor is it to explain the scope of the present invention. Its purpose is to express some aspects of the present invention in a simplified form, a preface to the content described in more detail later. A present invention overcomes the challenges of the prior art by providing a phase square wave AC voltage to an electrostatic chuck (ESC). For example, the polarity conversion speed of one square = «is faster than that of _ semiconductor wafers. The clamped inertial response is fast. In contrast to known electrostatic chucks, the present invention utilizes a relatively simple and inexpensive device. Compared to some of the conventional f-graphs, the residual charge is removed as quickly as possible. The second aspect of the present invention is to prevent the residual charge as a whole — “... m ^ 馒 first. The better method is as follows Attribute limitation ", and cited a square-wave single-phase alternating current system 200524071, which can be applied to a unipolar or a multipolar electrode electrostatic chuck. The dream can be further reduced to the minimum by adjusting the pulse wave width and the pulse wave rise time of the applied voltage when de-clamping. According to one aspect of the present invention, the method can be applied to flat electrostatic plates and electrostatic chucks according to M, where the semiconductor wafer is clamped and un clamped via a wafer inertia limiting mechanism. By controlling parameters such as an early = phase square wave AC signal rise time, pulse width, and pulse wave repetition rate (prf), the semiconductor wafer can be at least partially secured by the inertial mass of the wafer during voltage conversion. Clamping. And according to another aspect of the present invention, the wafer can be decomposed almost instantaneously after the clamping voltage is turned off 'at least in part because the pulse width during the clamping is short enough to be significantly prevented Charges migrate and accumulate on the dielectric front and / or back surface of the wafer. According to another exemplary aspect of the present invention, the electrostatic chuck may include different forms of electrode patterns, including, for example, a simple single-pole structure for an electro-active environment system or for a vacuum environment. System-a simple: D-shaped bipolar structure. Moreover, the present invention does not require complicated electrode patterns or complicated signal timing control electronic circuits. In order to achieve the above-mentioned and related objects, the present invention includes features hereinafter described in its entirety, and these features will be specifically mentioned in the following section. The following description and the accompanying drawings, which are presented in particular, illustrate embodiments of the invention. However, these embodiments are symbolic, and a few different ways can implement the principles of the present invention. Other objects, advantages and significant features of the invention will become more apparent from the following detailed description of the invention in conjunction with the drawings. [Embodiment]
本發明係針對一個系統以及一個方法,用於利用一靜電 夾盤(esc)箝制以及解箝制—個晶圓。因Λ,本發明將會參考 圖式而作說明’其中類似的參考元件符號係用於參考整體中 類似的元件。必須了解的是,該些層面的說明係僅僅用於顯 不性,並且不應該被視作一種限制性的了解。在下列用於解 釋的目的的敘述巾’大4特定細節係提以用於提供—個本發 明整體的了解。缺而對;^羽A -u· a 1 . …、對於自知技術者而言係明顯的是,本發 明可以不需用該些特定細節而實作。 " 本發明克服先前技術的挑戰,係提供一種系統以及一 方法’以用於箝制以及解箝制—個晶圓(例如,—個半導體The present invention is directed to a system and a method for clamping and unclamping a wafer using an electrostatic chuck (ESC). Because of Λ, the present invention will be described with reference to the drawings', wherein like reference numerals are used to refer to like elements in the whole. It must be understood that these levels of explanation are for explicitness only and should not be viewed as a restrictive understanding. Specific details are provided below for the purpose of explanation, 'Big Four', for the purpose of providing an overall understanding of the invention.羽 A -u · a 1... It is obvious to those skilled in the art that the present invention can be implemented without these specific details. " The present invention overcomes the challenges of the prior art by providing a system and a method 'for clamping and unclamping a wafer (eg, a semiconductor
板),其中-個預定的方波電壓係施加在該靜電夹盤,因此 擇性的箱制晶圓於其上。根據本發明之—示範性實施例中 該預定的方波電屢係一種晶圓之慣性性質的函數,靜電夾 之電现性質以及有關於在晶圓以及靜電央盤之間的冷卻幻 之反向壓力。 見在 '考圖式’第一圖顯示_個示範性籍制系、统⑽之 方h圖’其中该箝制系統包含—個靜電夾盤1〇5,用於選擇性 繼卜個晶圓U0於其上。舉例而言,電壓源115係操作 10 200524071 以用於廷擇性的提供電壓F至靜電夾盤1〇5,其中該電壓可 紅作以达擇ϋ的以靜電方式箝制晶圓i丨〇至一個靜電夾盤之 ;丨電層125的表面12〇,以及從一個靜電夾盤之介電層 的表面120解箝制晶圓丨丨〇。根據本發明之一示範性層面,該 電>1源1 1 5係可操作以提供一個單一相位方波交流箝制電壓 =該靜電夾盤105。舉例而言,提供一個單一相位方波交 抓箝制電[K ’可以將用於晶gj i ( 〇之解箝制時間最小化, 其中一個有關於該方波之脈波寬度以及脈波上升時間係可操 作以㈣該解箝制時間,將會在以下被討論到。系統100,舉 J 口進步包含一個氣體供應器13 0,可操作以提供一個 反向虱體壓力P(也參照為冷卻氣體反向壓力心至晶圓 ⑴° β «I體供應H 13〇 ’舉例而言,係可操作以提供一個冷 部軋體(並未顯示),例如氦氣,於靜電夾盤105之表面12〇 以及晶圓1 ίο之間。一個控制器135,舉例而言,係進一步可 操作以控制該冷卻氣體之塵力ρ,其中壓力控制係進一步可 操作以控制在靜電夾盤1〇5以及晶圓u〇之間的熱轉移量。 ㈣器U5,舉例而言,係進一步可操作以控制由電麼源⑴ 柑制電壓例如,一個電源供應器)至靜電夾盤⑻。 提供一個方波箝制電塵K至該靜電夾盤1〇5以用於有效 的㈣以及解籍制晶圓110之方法包含克服數個難題。舉例 而口 ’ -個方波箝制電I厂施加至靜電夾盤ι〇5係可操作以 感應-靜電箝制力4於晶圓11〇上,其中將晶圓吸引至靜 200524071 電夾盤之表面120。鈇而太 …、在拇制電壓V之極性被反向斯間(例 如,當方波箝制電屢超過〇伏特時),該冷卻氣體反向壓力‘ 曰超過柑制力Feic ’並且該晶圓J 1〇可以加速遠離靜電夾盤 之表面120。因為由冷卻氣體反向壓力;定義的排斥 力’晶® 11〇可以移動一段距離z遠離靜電央盤1〇5,如果該 靜電夾盤係上側朝下的話,可以並且/或是由於其他力量,例 如重力(並未顯示)而遠離晶圓。晶圓"〇不能以一無限速度v 移動’然而’其晶圓係受限於其慣性質量。如同牛頓第二定 律所敘述的,〜,…係箝制力‘以及反向愿力‘ 之總和,例如係相等於晶圓11〇之慣性質量所乘以晶圓之加 速度a,其中該加速度係定義為由速度以及距離所引生出,亦 尽? a=dWdt = d2x/dt2 〇 士根據本發明之一層面,晶圓11〇之一個位置係可以決定 為^曰1 /之函數,其中可以決定不會錯失晶圓的一個最小時 間里(例如,該晶圓係限定在接近於靜電夹盤105之一個區域 内)。必須注意的是箝制力F…以及冷卻氣體反向壓力。W, :例而言,通常會在箝制電M r超過。伏特時變化,因為該 :制電壓具有一個上升時間,其係一個時間,的函數,以及 2在晶圓110以及靜電夾盤105之表面12〇之間的冷卻氣體 月豆積擴大或是壓縮時,該反向壓力係可操作以隨著時間變化。 數學上,靜電夾盤之慣性限制動力學可以如下所表示。 晶圓110之移動通常觀察牛頓第二定律,F =所α,其中只係 12 200524071 晶圓上的淨力。該淨力f,舉例而言,可以表示為氣體反向 壓力y以及箝制力ΑκΓχ,y之總和,其中F係距離J 以及時間ί之函數,因此導出 F(x,t) = Fsas(x,t)-Fesc(x,t) = m^±。 ⑵ 剛開始當晶圓110並未移動時,氣體反向壓力,以 ,柑制力F㈣通常為常數,使得一個靜態氣體反向壓力p… ⑶ 其中户係氣體反向壓力(單位為陶爾,Torr),其施加以用 於冷部曰曰圓,以及4係晶圓之半徑。靜態箝制力〜肩係 進一步表示如下 (4) L l:R^s〇(k'v〇)2_ 2(d + k-gap)2 二中Q係真空介電常數(例如’。=&以…尸/w〇 絶緣介電質層125之介電f常數1 糸 係於靜電夾盤⑼之表面以及晶丨電/層之厚度,卿 产W去強一 w 衣囬乂及曰曰_ U〇之表面的靜態間隙長 Γ :二由冷卻氣體所佔據),並且〜係被施加 Μ靜態間隙長度客叩,舉例而言,可 電夹㈣之表面m的表面粗糙度。Ύ以有關於靜 13 200524071 當所施加之單一相位方波箝制電壓F超過〇伏特時,舉 例而言,該晶1] 110可能會損失箝制力4並且開始: 離靜電夾盤105之表面12〇,直中哕名 ^ π w U,、T該軋體反向壓力F州係定義 為距離X以及時間/之函數, 厂抑(义,0 =Plate), where a predetermined square wave voltage is applied to the electrostatic chuck, so a selective box wafer is applied to it. According to the present invention—the predetermined square wave power in the exemplary embodiment is often a function of the inertial properties of a wafer, the electro-occurrence properties of the electrostatic clamps, and the inverse effects on the cooling between the wafer and the electrostatic disk.向 压力。 To pressure. See the first picture of the 'Examination Schema', which shows _ an exemplary system and system of the system, where the clamping system contains an electrostatic chuck 105 for selective follow-up of a wafer U0 On it. For example, the voltage source 115 is operated 10 200524071 for selectively supplying the voltage F to the electrostatic chuck 105, wherein the voltage can be used to electrostatically clamp the wafer i to reach the selective voltage. An electrostatic chuck; the surface 120 of the electrical layer 125; and the wafer 120 from the surface 120 of the dielectric layer of an electrostatic chuck. According to an exemplary aspect of the present invention, the electric > 1 source 1 1 5 series is operable to provide a single phase square wave AC clamping voltage = the electrostatic chuck 105. For example, providing a single-phase square wave AC grasping clamp [K 'can minimize the unclamping time for crystal gj i (〇, one of which is related to the pulse width and pulse rise time of the square wave. Operable to de-clamp this time, as will be discussed below. System 100, J port progress includes a gas supply 130, operable to provide a reverse lice body pressure P (see also the cooling gas reaction P Supplying H 13〇 to the pressure center to the wafer β ° β body. For example, it is operable to provide a cold-rolled body (not shown), such as helium, on the surface 12 of the electrostatic chuck 105. And wafer 1. A controller 135, for example, is further operable to control the dust force ρ of the cooling gas, wherein the pressure control system is further operable to control the electrostatic chuck 105 and the wafer The amount of heat transfer between u0. Unit U5, for example, is further operable to control the voltage from an electric source (such as a power supply) to an electrostatic chuck. Provide a square-wave clamped electric Dust K to the electrostatic chuck 105 The method for efficient plutonium and decomposing wafer 110 includes overcoming several problems. For example, a square wave clamped by a factory I was applied to the electrostatic chuck. The 055 system is operable to induce an electrostatic clamping force. 4 On the wafer 110, the wafer is attracted to the surface 120 of the static 200524071 electric chuck. But too ..., the polarity of the thumb voltage V is reversed (for example, when the square-wave clamped electricity repeatedly exceeds 0). Volts), the reverse pressure of the cooling gas 'say exceeds the force of manganese Feic' and the wafer J 10 can accelerate away from the surface of the electrostatic chuck 120. Because of the reverse pressure of the cooling gas; 110 can move a distance z away from the electrostatic central disk 105, if the electrostatic chuck is on the top side, it can be and / or away from the wafer due to other forces, such as gravity (not shown). Wafer & quot 〇 Can't move at an infinite speed v. However, its wafer system is limited by its inertial mass. As described in Newton's second law, ~, ... is the sum of the clamping force and the inverse willingness force, such as Equivalent to the inertial mass of wafer 11 Take the acceleration a of the wafer, where the acceleration is defined as derived from the speed and the distance, which is also the best? It is a function of 1 /, in which it can be determined that the wafer will not be missed for a minimum time (for example, the wafer is limited to an area close to the electrostatic chuck 105). It must be noted that the clamping force F ... And the reverse pressure of the cooling gas. W, for example, usually changes when the clamping voltage M r exceeds. Volts, because the: voltage has a rise time, which is a function of time, and 2 on the wafer When the moon gas product between 110 and the surface 120 of the electrostatic chuck 105 expands or compresses, the reverse pressure is operable to change over time. Mathematically, the inertia-limiting dynamics of an electrostatic chuck can be expressed as follows. The movement of wafer 110 is usually observed by Newton's second law, F = so α, which is only the net force on the wafer. The net force f, for example, can be expressed as the sum of the gas reverse pressure y and the clamping force ΑκΓχ, y, where F is a function of the distance J and time ί, so F (x, t) = Fsas (x, t) -Fesc (x, t) = m ^ ±.开始 At the beginning, when the wafer 110 is not moving, the gas reverse pressure is usually constant, so that a static gas reverse pressure p ... ⑶ Where the household gas reverse pressure (unit is Taoer, Torr), which is applied to the circle of the cold section and the radius of the 4 series wafer. The static clamping force ~ shoulder system is further expressed as follows (4) L 1: R ^ s〇 (k'v〇) 2_ 2 (d + k-gap) 2 The Q series vacuum dielectric constant (such as'. = &Amp; Based on the dielectric constant f1 of the insulating dielectric layer 125, it is related to the surface of the electrostatic chuck and the thickness of the crystal / layer. The static gap length Γ on the surface of U0: 2 is occupied by the cooling gas), and the static gap length M is applied, for example, the surface roughness of the surface m that can be electrically clamped. For example, when the applied single-phase square-wave clamping voltage F exceeds 0 volts, for example, the crystal 1] 110 may lose the clamping force 4 and start: 12 away from the surface of the electrostatic chuck 105. , 哕 中 哕 名 ^ π w U ,, T The rolling body reverse pressure F state is defined as a function of distance X and time /, factory suppression (meaning, 0 =
Fgas(°)-gCip x + gap (5) 之函數 並且藉制力也係一個X以及 ^(,5〇=4^£^i(C (6) 2(“灸♦ +卿))2, ⑹ 其中F⑺係一個箝制電壓,其跨過晶圓1〇5以及有關於 靜電夾盤105之電極14〇。或者是,F⑴係一個箝制電壓,在 兩個或是更多有關於靜電夾盤1〇5之電極14〇。並且,舉 例而言’不再是一常數值而是會根據與系統1〇〇有關之時 間常數呈現指數型變化,其中Λ係晶圓丨〇5之電阻,並且c 是在晶圓以及電極14 0之間的電容。 因此,該箝制電壓F⑺可以以下式表示: m-v0 1 一 2 · exp ⑺ 將方程式(5)以及(6)結合至方程式(2),晶圓110之慣性限 剎的動力學可以表示為一個差分方程式 14 (8) 200524071 D(x,t) d2x _ 1 dt2 m x +gap 2(d^k^(x + gap)f 對於-般⑼軸的晶圓’該差分方程式(8)可以藉由利用 一個電腦化差分方程式計算器,例如由Mathsoft Engineering and Education,Inc.所生產的胸㈤,肖數值方式解決晶圓 Ί置X⑴在獲持位1 χ⑴後,該速度v⑴=办仙,以 及加速度= 可以被進一步導出。 、第2A至2D圖顯示一示範性單一相位方波箝制電壓卜 其被施加在第1圖中一個典型的平板靜電夾盤心在電壓轉 換期間’藉由控制參數’例如上升時間, 一相位方波交流箝制《信號的脈波重複㈣ 少部分是)晶圓慣性質量該晶圓11G可以被牢靠的箝制。第Μ 圖,舉例而言,圖示—施加的箝制…以及跨於第ι圖的 晶固105以及電極140的吻。第2八_之該示範性方波 箝制電…常定義箝制力‘,以及第2b圖說明解決吻 的結果,其中-個最大值,(例如’該晶圓移動的最大距離)以 至0所需的時間(例如’晶圓的初始位置)可以被決 疋?曰曰圓離開並且回返到其初始位置之間的消逝時間,舉 例而& ’係稱為晶圓衝擊時間。第 及2D圖個別說明晶 圓的^度,及加速度响,並且係以參考的目的而說明。 作為-範例,第2A-2D圖的圖表利用—個第^之平板 15 200524071 靜電失盤105,其具有一個15〇mm半徑以及一個〇 2mm絕緣 介電質層125(例如,氧化鋁層),其中一個幾近於3m的間隙 於晶圓110以及靜電夾盤105之間,其維持將近2〇〇陶爾的 氣體反向壓力P。施加一個幾近於±2000伏特的箝制電壓Γ, 其中提供一個幾近於250陶爾的靜態箝制力。電容c係幾近 於3。4nF,電阻及係幾近於2〇ω,在此時間常數定義為 及C = 6.8 X 1(Γ8 秒。 根據本發明另一個示範性層面,第i圖中—個以mems 為基礎之靜電夾盤105也可以根據本發明而利用。第3圖說 明一個示範性以MEMS為基礎之靜電夾盤15〇的平面圖,其 中靜電夾盤之一個表面155包含多個微結構16〇。該多個微 f構160’舉例而言,係可操作以維持一個前後一致的間隙於 晶圓(並未顯示)以及靜電夾盤15〇之表面155之間。再一次, 在電壓轉換期間,藉由控制參數,例如上升時間,脈波寬度, 以及單一相位方波交流箝制電壓信號的脈波重複頻率,由於 (至少部分是因為)晶圓慣性質量該晶圓110可以被牢靠的箝 制二,而,利用一個以MEMS為基礎之靜電夾盤15〇,通常 隹"午粉制電壓^係顯著的小於第1圖之典型平板靜電 105 〇 χ顯示於第4八_40圖之圖表,舉例而言,對於一個根據本 又月第3圖之以MEMS為基礎的靜電夾盤^ ,個別描述示 範性箝制電壓κ之波形’晶圓位置χ,速度v,以及加速“, 16 200524071 其皆為一個時間函數。舉例而言,利用一個以MEMS為基礎 之靜電夾盤150,其具有150mm半徑,其中幾近於1μηι的間 隙位於晶圓(並未顯示)以及靜電夾盤之間,其維持一幾近於 200陶爾的反向壓力尸,以及一個幾近於土U2伏特的箝制 電壓厂,其中提供幾近於4〇〇陶爾的靜態箝制力。電容c,舉 例而言,係幾近於78。2nF,電阻i?係幾近於2〇Ω,在此定 義AC時間常數為= 1。56 X 1(Γ6秒。 再次參考第2Α以及4Α圖,根據另一個本發明之示範性 層面,箝制電壓F之脈波寬度可以具有一個相當大的範圍。 一個脈波寬度的較低限制,舉例而言,如同先前所述係較佳 大於晶圓衝擊時間。另外,在另一個範例中,該脈波寬度較 佳的係大於10倍的晶圓衝擊時間,以用於提供一個用於靜電 夾盤之較高可靠度的因數。舉例而言,最短的脈波寬度1於 上述傳統的靜電夾盤和以MEMS為基礎的靜電夾盤而言係個 別幾近於1.3pSec以及llpSec。脈波寬度的較高上限,舉例 而言,係由與靜電夾盤生產率規格相關的一個預定的解箝制 時間所決定,因為解箝制時間係正比於在一個特定箝制電壓 下的箝制時間。如果希望一個短於0.5秒的解箝制時間,舉 例而言,對於上述傳統靜電夾盤的脈波寬度範圍例子而言, 必須k將近於1.3psec到幾近於0 5|Llsec,對應到幾近於 300kHz到1Hz的脈波重複頻率。根據上述以Mems為基礎之 靜電夹盤範例,其脈波寬度範圍必須在將近於UMec至〇.5 17 200524071 秒之間’其對應至將近於術1Hz的脈波重複頻率。 根據本發明之另一個示範性層面,有關於第 二’沒有存在嚴格的限制則數。舉例而言,"二 的電阻,並會在-個起伏不大的範圍内變化。 楚:靜電夹盤15°,舉例而言…The function of Fgas (°) -gCip x + gap (5) and the borrowing force is also X and ^ (, 5〇 = 4 ^ £ ^ i (C (6) 2 (“Moxibustion ♦ + 卿)) 2, ⑹ Wherein F⑺ is a clamping voltage across the wafer 105 and the electrode 14 of the electrostatic chuck 105. Alternatively, F⑺ is a clamping voltage at two or more of the electrostatic chuck 1〇 5 of the electrode 14〇. And, for example, 'is no longer a constant value but will show an exponential change according to the time constant related to the system 100, where Λ is the resistance of the wafer 〇〇5, and c is The capacitance between the wafer and the electrode 14 0. Therefore, the clamping voltage F⑺ can be expressed by the following formula: m-v0 1-2 · exp ⑺ Combining equations (5) and (6) to equation (2), the wafer The dynamics of the inertial limit brake of 110 can be expressed as a difference equation 14 (8) 200524071 D (x, t) d2x _ 1 dt2 mx + gap 2 (d ^ k ^ (x + gap) f for- Wafer 'The difference equation (8) can be calculated by using a computerized difference equation calculator, such as the chest and shawl produced by Mathsoft Engineering and Education, Inc. After the wafer X is held at 1 χ⑴, the speed v⑴ = do cents, and the acceleration = can be further derived. Figures 2A to 2D show an exemplary single-phase square wave clamping voltage that is applied. In Figure 1, a typical flat electrostatic chuck core is “controlled by a parameter” such as the rise time during a voltage conversion. A phase square wave AC clamps the “signal pulse repetitions. A small part of it.) The circle 11G can be securely clamped. Figure M, for example, the illustration-applied clamp ... and the kiss of the solid 105 and electrode 140 across Figure ι. This exemplary square wave clamp Electricity ... often defines the clamping force ', and Figure 2b illustrates the results of the kiss resolution, where a maximum value (for example,' the maximum distance the wafer moves) to zero time (for example, the initial position of the wafer) Can it be determined? The elapsed time between the circle leaving and returning to its original position, for example, & 'is called the wafer impact time. The 2D and 2D figures individually illustrate the degree of the wafer, and the acceleration response, And reference For the purpose of illustration, as an example, the diagrams in Figures 2A-2D use a plate 15 200524071 Electrostatic Loss Disk 105, which has a 150mm radius and a 02mm insulating dielectric layer 125 (for example, oxidation Aluminum layer), one of which has a gap of approximately 3m between the wafer 110 and the electrostatic chuck 105, which maintains a gas reverse pressure P of nearly 200 Taoer. A clamping voltage of approximately ± 2000 volts is applied Γ, which provides a static clamping force of approximately 250 Taoer. Capacitance c is close to 3.4nF, resistance is close to 20ω. Here, the time constant is defined as and C = 6.8 X 1 (Γ8 seconds. According to another exemplary aspect of the present invention, FIG. I— A mems-based electrostatic chuck 105 can also be used in accordance with the present invention. Figure 3 illustrates a plan view of an exemplary MEMS-based electrostatic chuck 15, where one surface 155 of the electrostatic chuck contains a plurality of micro Structure 16. The plurality of microstructures 160 ', for example, are operable to maintain a consistent gap between the wafer (not shown) and the surface 155 of the electrostatic chuck 15. Again, in During voltage conversion, by controlling parameters such as rise time, pulse width, and pulse repetition frequency of a single-phase square-wave AC clamped voltage signal, the wafer 110 can be secure due to (at least in part) the inertial mass of the wafer The second clamp, and the use of a MEMS-based electrostatic chuck 15 〇, usually "" PM powder voltage ^ is significantly smaller than the typical flat electrostatic 105 ○ χ shown in Figure 1 is shown in Figure 4-8_40 Graphs, for example, For an MEMS-based electrostatic chuck according to Figure 3 of this month, the waveforms of the exemplary clamping voltage κ 'wafer position χ, speed v, and acceleration' are individually described, 16 200524071, all of which are a function of time For example, using a MEMS-based electrostatic chuck 150, which has a radius of 150mm, where a gap of approximately 1 μm is located between the wafer (not shown) and the electrostatic chuck, which maintains a close to A 200 Taur reverse pressure body, and a clamping voltage plant close to U2 volts, which provides a static clamping force close to 400 Taur. Capacitor c, for example, is almost 78. 2nF, the resistance i? Is almost 20 Ω. Here, the AC time constant is defined as 1. 56 X 1 (Γ6 seconds. Referring again to Figures 2A and 4A, according to another exemplary aspect of the present invention, the voltage is clamped. The pulse wave width of F can have a considerable range. A lower limit of the pulse wave width, for example, is preferably greater than the wafer impact time as previously described. In addition, in another example, the pulse wave Better width is greater than 10 Times the wafer impact time to provide a higher reliability factor for electrostatic chucks. For example, the shortest pulse width is 1 compared to the conventional electrostatic chucks and MEMS-based electrostatic chucks described above. Disks are individually close to 1.3 pSec and llpSec. The higher upper limit of the pulse width, for example, is determined by a predetermined de-clamping time related to the electrostatic chuck productivity specification, because the de-clamping time is directly proportional For a clamping time at a specific clamping voltage. If a de-clamping time shorter than 0.5 seconds is desired, for example, for the above example of the pulse width range of the conventional electrostatic chuck, k must be approximately 1.3 psec to several Close to 0 5 | Llsec, corresponding to pulse repetition frequency of nearly 300kHz to 1Hz. According to the Mems-based electrostatic chuck example above, its pulse width must be between approximately UMec and 0.5 17 200524071 seconds', which corresponds to a pulse repetition frequency of approximately 1 Hz. According to another exemplary aspect of the present invention, there is no strict limitation regarding the second '. For example, the resistance of "two" will change within a small range. Chu: Electrostatic chuck 15 °, for example ...
"〃以及^曰圓之間的間隙所決定(並未顯示),其中箝制 係進一步可以更直接的由間隙所決定。然:而,對於 第=平板靜電夹盤而言’電容c以及籍制〜系通 二由弟1圖之間隙以及介電質層125之組合所決 數由曰圓之雷B节 可能的小’然而通常此時間常 心門二·以及夾盤表面狀況所限定。通常,較短的 曰1吊數,會造成較小的晶圓移動量X, 衝擊時間。相似的,較長的π時門較紐的晶圓 移動量x,會造成較大的晶圓" 〃 and ^ 曰 are determined by the gap between the circles (not shown), and the clamping system can be more directly determined by the gap. However, for the plate electrostatic chuck, the capacitance c and the system are determined by the combination of the gap in the figure 1 and the dielectric layer 125, and the number is determined by the section B of the circle of lightning. 'However, this time is usually limited by the door 2 and the surface condition of the chuck. In general, a shorter number of hoists of 1 will result in a smaller wafer movement X and impact time. Similarly, when the gate is moved by a longer π, the wafer movement x will result in a larger wafer.
圓的移動量X越ΙΓΙ衝擊時間。此時間常數越大,晶 數长 '’且日日圓衝擊時間越長。如果時間常 距離(例:舉例而言’晶圓110可以從靜電夾盤105移動-個 夠由),核㈣足夠遠使得其不能 :吸引’然後該靜電夾盤係’’漏失”了該晶圓。根據 上升S 時間常數將會影響單一相位方波籍制《的 的 由以上範例可知 其中當箝制電壓 ’傳統平板靜電夾盤係較容易容許失誤 F轉換極性並且高於〇伏特時,出現 18 200524071 7x10 m (0.0007μιη)的一個晶圓移動量i以及} 2χ1〇·6秒 的第一曰曰圓衝擊時間。當與平均的3,靜態間隙比較,此距 離可以考慮忽略。U MEMS為基礎之靜電夾盤範例相較之 下’較不能容忍誤差,因為電容c係幾近於大於一階的量測 階次,而具有一個lxl〇·7 m(〇 1μπι)的晶圓移動量X以及 X10心的a日圓衝擊時間。然而,以MEMS為基礎之靜電 夾盤超過傳統靜電夾盤的優點在於,卩mems為基礎之靜電馨 夾孟而σ ,靜電夾盤以及晶圓之間的間隙可以被良好的控 制,使得可能具有-個較小的間隙以及較低的箝制電壓以或 是^相同電壓下一個較大的箝制力)。舉例而言,較低的箝制 電壓F’會降低具有危害性的放電風險,並且也降低形成會 污染靜電夾盤的微粒物質的風險。 根據另個|a例,時間常數的較高上限係使得晶圓移 動!“、於初始間隙的十分之一,因為該間隙舉例而言係具 、子於氣體冷卻此力較大的影響。然而’因為脈波寬度在— 個大的範圍内變化,可以選擇較長的脈波寬度(較低的脈波重 複頻率)以將晶圓移動量的影響減至最小。較佳的是,脈波寬 度j於〇·1秒,以及方波箝制電壓的上升時間係小於2μ秒, =別對於傳統靜電夹盤以及以MEMS為基礎之靜電夾盤而 言二具有幾近於〇·5μπι的最大移動量χ以及〇上_的最大移 動量%。當脈波寬度不是這麼絕對時,〇1毫秒至〇1秒的脈 波重複頻率將會提供一個一般快速的解箝制時間。 19 200524071 根據本發明之另一個示範性層面,第丨圖以及第3圖之 月?電夾盤可以進一步包含不同形式的電極圖樣,包含,舉例 而言,一個用於一個電漿環境系統的簡單單一極結構或是一 個用於真空環境系統的簡單D形狀雙極結構。並且,本發明 亚不而要複雜的電極圖樣或是複合信號計時控制電子電路。 在推制電壓v關閉後晶圓可以幾乎即刻的被解箝制,因為(至 >某種私度上)在箝制期間脈波寬度足夠短以致於顯著的預 防電荷遷移以及累積至介電質前表面以及/或是晶圓的後表 面。 田次月了示範性方法以及在此所敘述的一連串的動作或 :事件’將可了解的是本發明並不限於所說明的此種動作或 是事件之順序,根據本發明—些步驟可以以不同的順序發 生,並且/或是與其他並未在此顯示及說明的步驟—起發生。 ^外’並非所有顯示的步驟可以需要根據本發明之法則實 —匕外冑可了解的是本方法可以由相關於在此說明並顯 、本系、先而實現’也可以由並未在此顯示的其他系統實現。 如見在多考第5圖,用於籍制—個半導體晶圓至一靜電夾 、方法2〇0係根據本發明之一示範性層面而說明。開始205 时料,根據(至少某種程度上)晶圓的慣性反性時間決定-個 攻相位方波拆制電壓。在動作21G中,晶圓係置放在靜電 二個箝制表面上。該箝制表面,舉例而言,可以包含 固平板著電夾盤表面,或是一個以μεμ§為基礎之靜電 20 200524071 夾&表面’其包含一從該夾盤表面延伸的多個微結構。在動 作215中’決定單一相位方波箝制電壓係施加在該靜電夾盤, ^中遠晶圓係通常被箝制在該靜電夾盤。被決定的箝制電 【舉例而& ’係可操作以感應在靜電夾盤以及晶圓之間的 個虎電力,在此係吸引晶圓到靜電夾盤的表面。在步驟2如 中單才Μ立方波|甘制電壓係停止,在此從豸靜電爽盤解籍The amount of movement X of the circle increases the impact time. The larger this time constant, the longer the crystal number '' and the longer the impact time of the yen and yen. If the time is constant (for example: 'wafer 110 can be moved from the electrostatic chuck 105-enough reason), the core is far enough so that it cannot: attract' then the electrostatic chuck system `` misses '' the crystal According to the rising S time constant, it will affect the single-phase square wave system. From the above example, it can be known that when the clamping voltage 'conventional flat electrostatic chuck system is easier to tolerate the error F conversion polarity and higher than 0 volts, 18 200524071 7x10 m (0.0007μιη) wafer movement i and} 2 × 10.6 second round impact time. When compared with the average 3, static gap, this distance can be considered ignored. U MEMS-based The electrostatic chuck example is less tolerant of errors because the capacitance c is a measurement order that is almost greater than a first order, and has a wafer movement X of 1 × 10 · 7 m (〇1μπι) and The impact time of a yen of X10 core. However, the advantage of MEMS-based electrostatic chucks over traditional electrostatic chucks is that 卩 mems-based electrostatic chucks and σ, the gap between the electrostatic chuck and the wafer can be Be good Control makes it possible to have a smaller gap and a lower clamping voltage or a larger clamping force at the same voltage). For example, a lower clamping voltage F 'will reduce the harmful The risk of discharge also reduces the risk of forming particulate matter that can contaminate the electrostatic chuck. According to another example, a higher upper limit of the time constant causes the wafer to move! ", One tenth of the initial gap, because Gap, for example, has a large effect on the force of gas cooling. However, because the pulse width varies within a large range, a longer pulse width (lower pulse repetition frequency) can be selected to minimize the effect of wafer movement. Preferably, the pulse width j is 0.1 seconds, and the rise time of the square wave clamping voltage is less than 2 μs, which is almost the same as the traditional electrostatic chuck and the MEMS-based electrostatic chuck. The maximum amount of movement χ at 0.5 μm and the maximum amount of movement% above _. When the pulse width is not so absolute, a pulse repetition frequency of 0.01 milliseconds to 0.01 seconds will provide a generally fast de-clamping time. 19 200524071 According to another exemplary aspect of the present invention, Fig. 丨 and the month of Fig. 3? The chuck may further include different forms of electrode patterns, including, for example, a simple unipolar structure for a plasma environment system or a simple D-shape bipolar structure for a vacuum environment system. In addition, the present invention requires complicated electrode patterns or a composite signal timing control electronic circuit. The wafer can be un-clamped almost immediately after the push voltage v is turned off, because (to> some degree of privacy) during the clamping the pulse width is short enough to significantly prevent charge migration and accumulation before the dielectric Surface and / or the rear surface of the wafer. Tian Jiyue demonstrated the exemplary method and a series of actions or events described herein. It will be understood that the present invention is not limited to the sequence of such actions or events described. According to the present invention, some steps can be This happens in a different order and / or together with other steps not shown and explained here. ^ Externally, not all the steps shown may need to be implemented according to the principles of the present invention-what is known is that this method can be implemented by related to the description and display here, this system, first, or it can also be achieved by Other system implementations shown. As shown in FIG. 5 of the multi-test, the method 2000 for manufacturing a semiconductor wafer to an electrostatic clip is described according to an exemplary aspect of the present invention. At the beginning of 205, it is determined based on (at least to a certain extent) the inertia time of the wafer-an off-phase square wave disassembly voltage. In action 21G, the wafer system is placed on two static clamping surfaces. The clamping surface, for example, may include a flat plate on the surface of an electrical chuck, or an electrostatic based on µεµ§ 20 200524071 Clamp & Surface 'which includes a plurality of microstructures extending from the surface of the chuck. In action 215, it is determined that a single-phase square-wave clamping voltage system is applied to the electrostatic chuck. COSCO wafer systems are usually clamped to the electrostatic chuck. The clamped electricity determined [for example, & 'is operable to sense the power between the electrostatic chuck and the wafer, where the wafer is attracted to the surface of the electrostatic chuck. In step 2, the M cube wave is stopped. The voltage system is stopped.
制該晶圓。解箝制時間,舉例而言,係由於在動作205實現 的箝制電壓而可以降至最小。Manufacture the wafer. The de-clamping time, for example, can be minimized due to the clamping voltage achieved in action 205.
雖然本發明已經針對特定的實施例或是實施例顯示以7 說明’明顯的是習知技術者在閱讀並且了解本說明書以及附力 圖式後,等效變異以及修改將會發生。在特定相關於由上述力 ^組件’裝置’電路,等等)所實現的不同功能,除非特則 疋否則用於“述该些組件的特定用語(包含參照為“裝置 的)係' 意欲對應至任何可實現所述㈣的特定功能的元件,(边 即’意指功能上的等效),即使沒有功能性等效至所揭示結構, :其貫現在此所揭示的本發明示範性實施例的功能。除此之 夕’當-個本發明之特定特徵可以針對於數個實施例其中一 ^此種特徵可以對於—給^的或是特定的中請案所欲求並且 有i的結合一或是其他實施例更多的其他特徵。 【圖式簡單說明】 統層級方塊圖,其 第1圖係一示範性靜電夾盤之一個系 係根據本發明之某一層面。 21 200524071 第 圖至第2D圖係圖表,顯示根據本發明另一層面之 -示範性典型靜電夾盤,其箝制電壓之波形,晶圓位置,速 度以及加速度,其中波形,晶圓位置,速度,以及加速度 係為時間的函數。 第3圖顯示根據本發明另一示範性層面的 MEMS為基礎之靜電夾盤。Although the present invention has been described with reference to a specific embodiment or embodiment, it is obvious that after reading and understanding this specification and the attached drawings, those skilled in the art will have equivalent variations and modifications. In particular related to the different functions implemented by the above-mentioned components (devices, devices, circuits, etc.), unless specified otherwise, the terms used to describe the components (including those referred to as "devices") are intended to correspond To any element that can achieve the specific function of the ㈣ (edge means 'equivalent to a functional equivalent'), even if there is no functional equivalent to the disclosed structure, which is now an exemplary implementation of the invention disclosed herein Example function. In addition to this, when a specific feature of the present invention can be directed to several embodiments, one such feature can be for-given or a specific claim and have a combination of i or other Embodiments have other features. [Brief Description of the Drawings] A system-level block diagram, FIG. 1 of which is an exemplary electrostatic chuck according to a certain aspect of the present invention. 21 200524071 Figures 2D are diagrams showing the exemplary typical electrostatic chuck according to another aspect of the present invention, its clamping voltage waveform, wafer position, speed, and acceleration, among which waveform, wafer position, speed, And acceleration is a function of time. Figure 3 shows a MEMS-based electrostatic chuck according to another exemplary aspect of the invention.
一: 圖至第4D圖係圖表,顯示根據本發明另一層面 一不範性典型靜電夾盤,其 八柑制電壓之波形,晶圓位置,: 又’以及加速度,1 φ、、由游 係A 士 八波形,日日圓位置,速度,以及加速, 你為日可間的函數。 苐5圖顯示根據本發明另 拆制一個晶圓的示範性方法。 【主要元件符號說明】 一不範性層面用於箝制以及解 100 105 110 115 120 125 130 135 示範性箝制系統 靜電夾盤A: Figures to 4D are diagrams showing a typical electrostatic chuck according to another aspect of the present invention. The waveform of the voltage and the wafer position are: and the acceleration, 1 φ, For A Shiba waveform, Japanese yen position, speed, and acceleration, you are a function of the time between day and day. Figure 5 shows an exemplary method of disassembling another wafer according to the present invention. [Explanation of Symbols of Main Components] A non-standard level is used for clamping and solving 100 105 110 115 120 125 130 135 Demonstration clamping system Electrostatic chuck
晶圓 電壓源 介電層表面 介電層 氣體供應器 控制器 電極 22 140Wafer Voltage Source Dielectric Surface Dielectric Gas Supply Controller Electrode 22 140
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US10/657,449 US6947274B2 (en) | 2003-09-08 | 2003-09-08 | Clamping and de-clamping semiconductor wafers on an electrostatic chuck using wafer inertial confinement by applying a single-phase square wave AC clamping voltage |
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TWI358784B TWI358784B (en) | 2012-02-21 |
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CN1655022A (en) * | 2004-02-14 | 2005-08-17 | 鸿富锦精密工业(深圳)有限公司 | Substrate applying device |
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US20070195482A1 (en) * | 2006-02-23 | 2007-08-23 | Varian Semiconductor Equipment Associates, Inc. | Johnsen-Rahbek electrostatic chuck driven with AC voltage |
US8270142B2 (en) * | 2008-12-10 | 2012-09-18 | Axcelis Technologies, Inc. | De-clamping wafers from an electrostatic chuck |
US8592786B2 (en) * | 2012-03-23 | 2013-11-26 | Varian Semiconductor Equipment Associates, Inc. | Platen clamping surface monitoring |
GB201321463D0 (en) | 2013-12-05 | 2014-01-22 | Oxford Instr Nanotechnology Tools Ltd | Electrostatic clamping method and apparatus |
US10923379B2 (en) * | 2017-02-15 | 2021-02-16 | Lam Research Corporation | Methods for controlling clamping of insulator-type substrate on electrostatic-type substrate support structure |
CN108861614B (en) * | 2018-07-10 | 2020-11-27 | 成都青山利康药业有限公司 | Moving method of natural biological film material |
US11437262B2 (en) * | 2018-12-12 | 2022-09-06 | Applied Materials, Inc | Wafer de-chucking detection and arcing prevention |
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KR20060065714A (en) | 2006-06-14 |
EP1665365A1 (en) | 2006-06-07 |
KR101130514B1 (en) | 2012-03-28 |
CN1875471A (en) | 2006-12-06 |
CN100459093C (en) | 2009-02-04 |
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