TW200521837A - Method for switching to boot multi-processor computer system - Google Patents

Abstract

The present invention provides a method for switching to boot multi-processor computer system, which employs a baseboard management controller (BMC) to manage booting exception problems of a multi-processor computer system. The present invention employs an operation status of a central processing unit (CPU) or a BIOS stored in a ROM, and uses a CPU switching procedure or a ROM switching procedure to switch to an available CPU and BIOS for booting, so as to effectively improve the system stability.

Description

200521837 V. Description of the invention α) [Technical field to which the invention belongs] The present invention relates to a method for managing a boot abnormality of a multiprocessor computer system, in particular, a CPU or ROM switching program by a BMC (Baseboard Management Controller), To manage abnormal boot problems. [Previous technology] In the computer system, based on the high-availability (High Available) system design concept of 'in order to maintain the system to continue to operate without the need for any human # work to troubleshoot' there is a need for a backup system, this is One of the reasons for a multiple processor system. Reprocessing physical computer systems such as servers (s e v e r), because they have multiple central processing units το (CPU) ′, can improve the overall processing performance, and can be used as a substitute when a specified CPU error occurs. — As a general rule, the boot process for a multiprocessor computer system is to designate a single boot CPU (Boot strap Processor) to provide the computing function 'responsible for processing the basic input and output system (B 丨 〇s) instructions at boot time to perform The computer system is initialized and loaded into the operating system (0s); of which, the “boot BI 0S” is stored in the “Read Only Memory of the Basic Input Output System” (BIOS ROM), and other CPUs are defined as “applications when booting ^ U (appiicati〇n pr〇cess〇rs) ", and is set at. "Wait state". When the boot CPU cannot be used, the existing method is to write a program for switching the CPU at boot time in BI0S to switch from the boot CPU to other application CPUs. The switching mechanism is shown in Figure 1. "Another possible problem is that B 丨 os has switched to all

200521837 V. Description of the invention (2) CPU0 was attempted but still unable to boot; this situation may be caused by a BIOS ROM problem. In order to solve the problem of MOS abnormality, one or more backups are read-only. Backup. ROM is used as an alternative solution; the booting BI0s are switched to the backup 81 stored in the backup ROM, and the booting process is continued. The switching mechanism is shown in FIG. 2. However, the disadvantage of the aforementioned method is that special β 丨 〇s must be used for switching, or “read-only memory boot switching” (r〇m Β〇〇ί Swap) is performed, and BI0s ROM is performed. The electronic circuit of switching is more complicated, so it is really too cumbersome and not cost-effective. [Summary of the Invention] The technical problem to be solved by the present invention is that in conventional technology, rewriting B 开机, designing ROM switching, and other methods to switch the abnormality of the startup abnormality are not cost-effective and work requirements. In view of the problems of the above-mentioned conventional technologies, the present invention provides a method for switching on and off a computer system, which is managed by a substrate management controller. Judgment and execution of CPU and ... CPU switchover during abnormal startup, including = next step: confirm booting through a BMC (Baseboard Management Controller): c'PU enters a CPU (Central Processing Unit) switching program and restart;

Mel's new booting steps; Among them, the CPU switching program is switched by sequence-Λ machine cpu and at least one application cpu; Furthermore, the _cut machine ROM sequence is passed, the BIOS that executes the boot process is stored in a Copy B ^ S — Power on ^ 08, switch to one of the backups stored in at least 1 ^

Page 6 200521837 V. Explanation of the invention (3) The effect achieved by the present invention is that the BMC can manage the abnormal startup problem. The system B I 0 S and R 0 M do not need to make additional design, which can further improve the system stability. [Embodiment] The present invention is a booting switching method for a multiprocessor computer system, which mainly uses a baseboard management controller (BMC) to manage the judgment and execution of CPU and BIOS switching during abnormal booting. BMC was originally applied to the intelligent platform management interface (IPMI), the interface between the management software of the control system and the platform management hardware, providing independent monitoring, event recording and recovery control functions, and can be used as the system management software and intelligent platform management convergence Use the network gateway between the Intelligent Platform Management Bus (IPMB) and the Intelligent Chassis Management Bus (ICMB) interface. The reason why the BMC can be used to manage system abnormality is because the system can obtain the system status information from the BMC through the "Low Pin Count (LPC) Interface". The present invention is another brand-new application field of B MC. The following is a description of a processing method for managing an abnormal situation of booting through BMC with reference to FIG. 3. The execution priority sequence is basically a CPU switch and a reboot, if not, then a ROM switch and a reboot. First, after the system power is turned on, confirm that the BMC has not received a power-on message from one of the booting BIOS (step 11); if it receives a power-on message, it means

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The system boots normally (step 120). The BMC is powered by the system's backup power. Therefore, the BMC is ready before the system power is turned on. In this way, the system can receive the operating status of the boot process as soon as the system and system power is turned on. / 、 Next, confirm that the CPU switching program and ROM switching program are not completed (step 130). If the system has completed the cpu and r 0μ switching programs but cannot boot, it means that all CPUs have errors and the system cannot boot. (Step 1 4 〇), can only manually troubleshoot, such as replacing the cpu. Secondly, confirm that the CPU switching program is not completed (step 5o), and the CPU switching program is printed (step 1 60). The CPU switching procedure of step 160 includes two detailed processes; it is to change the SMI state of all CPUs to change the BSP CPU (the so-called BSP CPU is in the ~ boot strap processor). Start the CPU that is booted, which is the CPU that is preset to boot; in the second and subsequent cpu switching procedures, the CPU that was booted the previous time) is isolated from the cpu bus (step 161), and then the BMC generates a CPU Switch the signal and a restart signal to the boot BI 0S or backup BI 0S (step 16 2). After restarting, return to step 11 0 to confirm the power-on status. After the determination in step 150, if the CPU switching has been performed, the ROM switching procedure is performed (step 170). This program is to switch on the BI 0 S 'in B 10 SR 0 Μ from the booting of BI 0 S' to the backup BIOS in backup r 0 μ, and restart the computer with the backup BIOS. BMC generates rm switching signal to a complex programmable logic device CPLD (Complex

Programmable Logic Device) to switch to the backup ROM and generate a system restart signal to the backup BIOS. After rebooting, it also returns to step

Page 8 200521837 V. Description of the invention (5) 11 0 Confirm the startup state. Please refer to FIG. 4 to illustrate the execution flow in the BMC when performing CPU switching, which can prove the feasibility of the present invention. SM 11 and SM 2 are two "System Management Interrupts (SMI)" on the BMC. The SWAP status indicates the switching status. STBY_PGD, R0M_SWAP, STATE_CHANGE, SYS_PGD, CPU_SWAP, etc. are the functional parameters of the control program in the BMC; STBY_PGD is the standby power-on state, R0M_SWAP is the ROM switching state, STATE_CHANGE is the state transition, SYS_PGD is the system restart state, and CPU_SWAP is the CPU switching state. The CPU switching in the figure includes four states, which allows the BMC to know the number of CPUs to switch to. The execution content of each state is described as follows: (1) The execution content of the first state includes: a. Set SMI 1 to LOW ( Low level); b. Set SMI2 to HIGH; c. Set SWAP state to the second state; d. Set STATE_CHANGE to CHANGE. (2) The implementation of the second state includes: a. Set SMI 1 to HIGH; b. Set SMI2 to LOW; c. Set SWAP state to the third state; d · Set STATE_CHANGE to CHANGE ° (3) in the third state The execution contents include: a. Set SMI1 to LOW; b. Set SMI2 to LOW;

Page 9 200521837 V. Description of the invention (6) c. Set SWAP state to the 4th state; d. Set STATE_CHANGE to CHANGE ° (4) The implementation of the 4th state includes: a. Set the SWAP state to the 4th state; b . Set STATE_CHANGE to CHANGE ° Figure 5 illustrates the detailed process of the invention when using the BMC for ROM switching (ROM SWAP), and can also be used to verify the feasibility of the invention. Among them, BACKUPR0M represents a backup ROM state. In the present invention, the backup ROM may be in a normal state or a backup state; ROMswitch represents a function parameter of a ROM switching state. With the CPU and ROM flow in Figures 4 and 5, the BMC can follow the flow in Figure 3 'to switch the CPU in Figure 4 when the boot is abnormal, and then perform the ROM switch in Figure 5 when it fails to boot. Managing abnormal startup conditions is indeed feasible. The above-mentioned ones are merely preferred embodiments of the present invention, and are not intended to limit the scope of implementation of the present invention. Those who are familiar with this technique after the disclosure of the present invention 'are modified based on the technical ideas of the present invention. Derivative works. Therefore, equivalent changes and modifications made without departing from the technical scope of the present invention should all be covered by the scope of patent application of the present invention.

Page 10 200521837 Schematic illustration of the first mechanism;

2 is a diagram showing the booting switching of the multiprocessor system in the prior art. 3 is a diagram illustrating the booting switching mechanism of the multiprocessor system managed by the BMC according to the present invention; FIG. 4 is a diagram illustrating the process of switching the multiprocessor CPU by the BMC according to the present invention ; And 糸 ,, Figure 5 of the first boot is to illustrate the present invention to restore the ROM switch process using b MC. [Schematic symbol description] when the processor system is turned on. Step 110 The BMC has not received one of the boot messages of BI0S. Step 1 2 0 The system starts normally. Step 130 The CPU switching process and the ROM switching process are not completed. Step 1 4 0 The system cannot boot. Step 150 Confirm that the CPU switching procedure is not completed. Step 1 6 G Perform the CPU switching procedure. Step 161 Change the SMI status of all CPUs to isolate BSP cpu ^ cpu. / Step 16 2 The BMC generates a CPU switching signal and a BIOS or backup. BIOS step 1 7 0 R 0 Μ switch program CPU central processing unit BIOS basic input output system ROM read-only memory BMC baseboard management controller restart signal to boot

200521837 Schematic description

BSP CPU default boot CPU SMI 1, SMI 2 System management interrupt SWAP state switching state STBY_PGD Standby power-on state R0M_SWAP ROM switching state STATE_CHANGE state transition SYS_PGD System restart state CPU.SWAP CPU switching state LOW Low HIGH High BACKUPR0M Backup ROM status ROMswitch ROM switching status

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Claims (1)

200521837 1 · A method for switching on a multiprocessor computer system, including the following steps: confirming a boot abnormality through a BMC (Baseboard Management Controller); and performing a CPU (Central Processing Unit) switching procedure and restarting the system; wherein, the CPU switching procedure It uses the BMC to switch between _booting the cpu and at least one application CPU; ^ Wherein, when the booting process cannot be started through the cPU, it also includes the steps of performing a ROM (read-only memory) switching process and restarting. ^ Among them, the ROM switching program is to use the BMC to save the BIOS that executes the booting procedure from a boot! ^ (^ One boot 6103, switch to a backup BIOS stored in at least one backup ROM. '2 · If requested The method for switching on a multi-processor computer system according to item 1 of the patent scope, wherein the CPU switching procedure further includes: changing the SMI (System Management Interrupt) state of each CPU to connect the CPU and a CPU that were previously powered on The bus is isolated; and a CPU switching signal and a restart signal are generated to the boot BIOS or the backup 8103 through the BMC. 3. As described in the first item of the scope of patent application Processor computer system booting switching method 'wherein the ROM switching procedure is to generate a ROM switching signal from the BMC to a complex programmable logic device CPLD (Complex Programmable Logic Device) to switch to the backup ROM and generate a system Reboot signal to the backup BI 0S. 4. The booting switching method of the multiprocessor computer system as described in item 1 of the scope of patent application, wherein the boot abnormality means that the BMC has not received the boot from 200521837 VI. Patent application scope BIOS or one of the backup BIOS has booted message. 5. The method for switching on a multiprocessor computer system as described in item 1 of the scope of the patent application, further comprising a step of confirming that the CPU switching program and the ROM switching program are not completed after confirming the abnormal startup. 6. The method for switching on a multiprocessor computer system as described in item 5 of the scope of patent application, further comprising a step of confirming that the CPU switching procedure has not been completed before the CPU switching procedure is performed. Page 14