TW200514081A - System and method of calibrating a read circuit in a magnetic memory - Google Patents

System and method of calibrating a read circuit in a magnetic memory

Info

Publication number
TW200514081A
TW200514081A TW093108849A TW93108849A TW200514081A TW 200514081 A TW200514081 A TW 200514081A TW 093108849 A TW093108849 A TW 093108849A TW 93108849 A TW93108849 A TW 93108849A TW 200514081 A TW200514081 A TW 200514081A
Authority
TW
Taiwan
Prior art keywords
magnetic memory
calibrating
method includes
read circuit
includes performing
Prior art date
Application number
TW093108849A
Other languages
Chinese (zh)
Other versions
TWI317127B (en
Inventor
Kenneth K Smith
Frederick A Perner
Richard L Hilton
Original Assignee
Hewlett Packard Development Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hewlett Packard Development Co filed Critical Hewlett Packard Development Co
Publication of TW200514081A publication Critical patent/TW200514081A/en
Application granted granted Critical
Publication of TWI317127B publication Critical patent/TWI317127B/en

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/50—Marginal testing, e.g. race, voltage or current testing
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/14—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using thin-film elements
    • G11C11/15—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using thin-film elements using multiple magnetic layers

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Mram Or Spin Memory Techniques (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Digital Magnetic Recording (AREA)

Abstract

A method of calibrating a read circuit (46) in a magnetic memory (10) is disclosed. The method includes measuring a calibration value. The method includes performing a large error calibration if the calibration value is within a maximum range. The method includes performing a small error calibration if the calibration value is within a minimum range. The method includes performing a first read operation on the magnetic memory. The method includes performing a second read operation on the magnetic memory.
TW093108849A 2003-10-03 2004-03-31 Method of calibrating a read circuit in a magnetic memory TWI317127B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US10/678,322 US6894938B2 (en) 2003-10-03 2003-10-03 System and method of calibrating a read circuit in a magnetic memory

Publications (2)

Publication Number Publication Date
TW200514081A true TW200514081A (en) 2005-04-16
TWI317127B TWI317127B (en) 2009-11-11

Family

ID=34393897

Family Applications (1)

Application Number Title Priority Date Filing Date
TW093108849A TWI317127B (en) 2003-10-03 2004-03-31 Method of calibrating a read circuit in a magnetic memory

Country Status (4)

Country Link
US (1) US6894938B2 (en)
EP (1) EP1526549B1 (en)
DE (1) DE602004015697D1 (en)
TW (1) TWI317127B (en)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100988087B1 (en) * 2003-11-24 2010-10-18 삼성전자주식회사 Analysis Apparatus of Magnetic Random Access Memory and Analysis Method Thereof
KR100721581B1 (en) * 2005-09-29 2007-05-23 주식회사 하이닉스반도체 Multi port memory device with serial input/output interface
US7372753B1 (en) * 2006-10-19 2008-05-13 Unity Semiconductor Corporation Two-cycle sensing in a two-terminal memory array having leakage current
US7379364B2 (en) * 2006-10-19 2008-05-27 Unity Semiconductor Corporation Sensing a signal in a two-terminal memory array having leakage current
US20090234767A1 (en) * 2008-03-12 2009-09-17 Steidlmayer J Peter Cost-based financial product
US7719876B2 (en) 2008-07-31 2010-05-18 Unity Semiconductor Corporation Preservation circuit and methods to maintain values representing data in one or more layers of memory
US7830701B2 (en) * 2008-09-19 2010-11-09 Unity Semiconductor Corporation Contemporaneous margin verification and memory access for memory cells in cross point memory arrays
US10839900B1 (en) 2019-06-12 2020-11-17 International Business Machines Corporation Parasitic voltage drop compensation in large cross-point arrays
US11200297B2 (en) 2019-06-12 2021-12-14 International Business Machines Corporation Integrator voltage shifting for improved performance in softmax operation

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6262625B1 (en) * 1999-10-29 2001-07-17 Hewlett-Packard Co Operational amplifier with digital offset calibration
US6188615B1 (en) * 1999-10-29 2001-02-13 Hewlett-Packard Company MRAM device including digital sense amplifiers
US6504779B2 (en) * 2001-05-14 2003-01-07 Hewlett-Packard Company Resistive cross point memory with on-chip sense amplifier calibration method and apparatus
US20030023922A1 (en) * 2001-07-25 2003-01-30 Davis James A. Fault tolerant magnetoresistive solid-state storage device
US6606262B2 (en) * 2002-01-10 2003-08-12 Hewlett-Packard Development Company, L.P. Magnetoresistive random access memory (MRAM) with on-chip automatic determination of optimized write current method and apparatus
US7049577B2 (en) * 2002-09-30 2006-05-23 Teradyne, Inc. Semiconductor handler interface auto alignment

Also Published As

Publication number Publication date
TWI317127B (en) 2009-11-11
DE602004015697D1 (en) 2008-09-25
US6894938B2 (en) 2005-05-17
EP1526549B1 (en) 2008-08-13
EP1526549A1 (en) 2005-04-27
US20050073890A1 (en) 2005-04-07

Similar Documents

Publication Publication Date Title
TW200610940A (en) Method and apparatus for measuring magnetic offset of geomagnetic sensor and portable electronic apparatus
AU6218201A (en) Detecting errors in the determination of magnetic location or orientation
JP2720718B2 (en) Semiconductor sensor device
EP1260988A3 (en) Resistive cross point memory device with calibration controller for a sense amplifier
EP1204074A3 (en) Apparatus for automatically setting measurement reference element and measuring geometric feature of image
EP1275933A3 (en) Portable electronic apparatus with azimuth measuring function, magnetic sensor suitable for the apparatus, and azimuth measuring method for the apparatus
EP1241678A3 (en) Built-in self test circuit employing a linear feedback shift register
AU5999201A (en) Continuously updated data processing system and method for measuring and reporting on value creation performance
WO2006044960A3 (en) Position detection apparatus and method for linear and rotary sensing applications
WO2003029804A1 (en) Measurement instrument and concentration measurement apparatus
AU4557799A (en) On-chip circuit and method for testing memory devices
TW200739598A (en) System and method for providing temperature data from a memory device having a temperature sensor
WO2002075334A3 (en) Apparatus and method for measuring and probability estimating for clock skews
TW200514081A (en) System and method of calibrating a read circuit in a magnetic memory
AU2001251499A1 (en) Methods, systems, wireless terminals, and computer program products for calibrating an electronic clock using a base reference signal and a non-continuous calibration reference signal having greater accuracy than the base reference signal
WO2004066095A3 (en) Method and system for calibrating a location system
GB0127165D0 (en) Circuit and method for generating fixed point data with reduced circuit scale
EP1333446A3 (en) Circuit and method for testing a ferroelectric memory device
EP2204647A3 (en) Potentiometric sensor for pH measurement
EP1251520A3 (en) Random access memory
EP1220230A3 (en) Circuit and method for testing a ferroelectric memory device
SE9003888D0 (en) SAM DATA ACCESSING CIRCUIT INVOLVING LOW OPERATING CURRENT, AND METHOD THEREOF
AU2001231718A1 (en) Measuring applications for an electronic reading device
TW200517856A (en) Prefetch control in a data processing system
AU2001267319A1 (en) Testing and calibrating device for an evaluation circuit of a linear oxygen probe (lambda probe)

Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees