TW200513961A - Apparatus and method for selectively overriding return stack prediction in response to detection of non-standard return sequence - Google Patents

Apparatus and method for selectively overriding return stack prediction in response to detection of non-standard return sequence

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Publication number
TW200513961A
TW200513961A TW093122812A TW93122812A TW200513961A TW 200513961 A TW200513961 A TW 200513961A TW 093122812 A TW093122812 A TW 093122812A TW 93122812 A TW93122812 A TW 93122812A TW 200513961 A TW200513961 A TW 200513961A
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TW
Taiwan
Prior art keywords
return
btac
return stack
response
instruction
Prior art date
Application number
TW093122812A
Other languages
English (en)
Other versions
TWI281121B (en
Inventor
Glenn G Henry
Thomas Mcdonald
Original Assignee
Ip First Llc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US10/679,830 external-priority patent/US7237098B2/en
Application filed by Ip First Llc filed Critical Ip First Llc
Publication of TW200513961A publication Critical patent/TW200513961A/zh
Application granted granted Critical
Publication of TWI281121B publication Critical patent/TWI281121B/zh

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TW093122812A 2003-10-06 2004-07-30 Apparatus and method for selectively overriding return stack prediction in response to detection of non-standard return sequence TWI281121B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US10/679,830 US7237098B2 (en) 2003-09-08 2003-10-06 Apparatus and method for selectively overriding return stack prediction in response to detection of non-standard return sequence

Publications (2)

Publication Number Publication Date
TW200513961A true TW200513961A (en) 2005-04-16
TWI281121B TWI281121B (en) 2007-05-11

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TW093122812A TWI281121B (en) 2003-10-06 2004-07-30 Apparatus and method for selectively overriding return stack prediction in response to detection of non-standard return sequence

Country Status (2)

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CN (1) CN1291311C (zh)
TW (1) TWI281121B (zh)

Families Citing this family (31)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101449256B (zh) 2006-04-12 2013-12-25 索夫特机械公司 对载明并行和依赖运算的指令矩阵进行处理的装置和方法
EP2523101B1 (en) 2006-11-14 2014-06-04 Soft Machines, Inc. Apparatus and method for processing complex instruction formats in a multi- threaded architecture supporting various context switch modes and virtualization schemes
CN100442226C (zh) * 2007-07-02 2008-12-10 美的集团有限公司 微波炉返回键的设定方法
US10228949B2 (en) 2010-09-17 2019-03-12 Intel Corporation Single cycle multi-branch prediction including shadow cache for early far branch prediction
CN103282874B (zh) 2010-10-12 2017-03-29 索夫特机械公司 用于增强分支预测效率的指令序列缓冲器
EP3306466B1 (en) 2010-10-12 2020-05-13 INTEL Corporation An instruction sequence buffer to store branches having reliably predictable instruction sequences
WO2012135041A2 (en) 2011-03-25 2012-10-04 Soft Machines, Inc. Register file segments for supporting code block execution by using virtual cores instantiated by partitionable engines
TWI520070B (zh) 2011-03-25 2016-02-01 軟體機器公司 使用可分割引擎實體化的虛擬核心以支援程式碼區塊執行的記憶體片段
WO2012135031A2 (en) 2011-03-25 2012-10-04 Soft Machines, Inc. Executing instruction sequence code blocks by using virtual cores instantiated by partitionable engines
WO2012162188A2 (en) 2011-05-20 2012-11-29 Soft Machines, Inc. Decentralized allocation of resources and interconnect structures to support the execution of instruction sequences by a plurality of engines
CN103649931B (zh) 2011-05-20 2016-10-12 索夫特机械公司 用于支持由多个引擎执行指令序列的互连结构
WO2013077876A1 (en) 2011-11-22 2013-05-30 Soft Machines, Inc. A microprocessor accelerated code optimizer
KR101703401B1 (ko) 2011-11-22 2017-02-06 소프트 머신즈, 인크. 다중 엔진 마이크로프로세서용 가속 코드 최적화기
US8930674B2 (en) 2012-03-07 2015-01-06 Soft Machines, Inc. Systems and methods for accessing a unified translation lookaside buffer
US9740612B2 (en) 2012-07-30 2017-08-22 Intel Corporation Systems and methods for maintaining the coherency of a store coalescing cache and a load cache
US9710399B2 (en) 2012-07-30 2017-07-18 Intel Corporation Systems and methods for flushing a cache with modified data
US9916253B2 (en) 2012-07-30 2018-03-13 Intel Corporation Method and apparatus for supporting a plurality of load accesses of a cache in a single cycle to maintain throughput
US9229873B2 (en) 2012-07-30 2016-01-05 Soft Machines, Inc. Systems and methods for supporting a plurality of load and store accesses of a cache
US9678882B2 (en) 2012-10-11 2017-06-13 Intel Corporation Systems and methods for non-blocking implementation of cache flush instructions
US9891924B2 (en) 2013-03-15 2018-02-13 Intel Corporation Method for implementing a reduced size register view data structure in a microprocessor
US9886279B2 (en) 2013-03-15 2018-02-06 Intel Corporation Method for populating and instruction view data structure by using register template snapshots
WO2014150971A1 (en) 2013-03-15 2014-09-25 Soft Machines, Inc. A method for dependency broadcasting through a block organized source view data structure
EP2972836B1 (en) 2013-03-15 2022-11-09 Intel Corporation A method for emulating a guest centralized flag architecture by using a native distributed flag architecture
US10140138B2 (en) 2013-03-15 2018-11-27 Intel Corporation Methods, systems and apparatus for supporting wide and efficient front-end operation with guest-architecture emulation
WO2014151018A1 (en) 2013-03-15 2014-09-25 Soft Machines, Inc. A method for executing multithreaded instructions grouped onto blocks
WO2014150991A1 (en) 2013-03-15 2014-09-25 Soft Machines, Inc. A method for implementing a reduced size register view data structure in a microprocessor
WO2014150806A1 (en) 2013-03-15 2014-09-25 Soft Machines, Inc. A method for populating register view data structure by using register template snapshots
US9811342B2 (en) 2013-03-15 2017-11-07 Intel Corporation Method for performing dual dispatch of blocks and half blocks
US9904625B2 (en) 2013-03-15 2018-02-27 Intel Corporation Methods, systems and apparatus for predicting the way of a set associative cache
US9569216B2 (en) 2013-03-15 2017-02-14 Soft Machines, Inc. Method for populating a source view data structure by using register template snapshots
US10275255B2 (en) 2013-03-15 2019-04-30 Intel Corporation Method for dependency broadcasting through a source organized source view data structure

Also Published As

Publication number Publication date
CN1291311C (zh) 2006-12-20
TWI281121B (en) 2007-05-11
CN1581070A (zh) 2005-02-16

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