TW200512644A - Synchronous periodical orthogonal data converter - Google Patents

Synchronous periodical orthogonal data converter

Info

Publication number
TW200512644A
TW200512644A TW093127265A TW93127265A TW200512644A TW 200512644 A TW200512644 A TW 200512644A TW 093127265 A TW093127265 A TW 093127265A TW 93127265 A TW93127265 A TW 93127265A TW 200512644 A TW200512644 A TW 200512644A
Authority
TW
Taiwan
Prior art keywords
vector
bank
data converter
components
register files
Prior art date
Application number
TW093127265A
Other languages
Chinese (zh)
Other versions
TWI263934B (en
Inventor
Boris Prokopenko
Timour Paltachev
Original Assignee
Via Tech Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US10/666,083 external-priority patent/US7284113B2/en
Application filed by Via Tech Inc filed Critical Via Tech Inc
Publication of TW200512644A publication Critical patent/TW200512644A/en
Application granted granted Critical
Publication of TWI263934B publication Critical patent/TWI263934B/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30036—Instructions to perform operations on packed data, e.g. vector, tile or matrix operations

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Mathematical Physics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Complex Calculations (AREA)

Abstract

An orthogonal data converter for converting the components of a sequential vector component flow to a parallel vector component flow. The data converter has an input rotator configured to rotate corresponding vector components of the sequential vector component flow by a prescribed amount, and a bank of register files configured to store the rotated vector components. The converter also has an output rotator configured to rotate the position of the vector components read from the bank of register files by a prescribed amount A controller of the converter is operative to control the addressing of the bank of register files and the rotating of the vector components. In this regard, the controller is operative to write the vector components to the bank of register files in a prescribed order and read the vector components in a prescribed order to generate the parallel vector component flow.
TW093127265A 2003-09-19 2004-09-09 Synchronous periodical orthogonal data converter TWI263934B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US10/666,083 US7284113B2 (en) 2003-01-29 2003-09-19 Synchronous periodical orthogonal data converter

Publications (2)

Publication Number Publication Date
TW200512644A true TW200512644A (en) 2005-04-01
TWI263934B TWI263934B (en) 2006-10-11

Family

ID=34619749

Family Applications (1)

Application Number Title Priority Date Filing Date
TW093127265A TWI263934B (en) 2003-09-19 2004-09-09 Synchronous periodical orthogonal data converter

Country Status (2)

Country Link
CN (1) CN100517212C (en)
TW (1) TWI263934B (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8659611B2 (en) * 2010-03-17 2014-02-25 Qualcomm Mems Technologies, Inc. System and method for frame buffer storage and retrieval in alternating orientations
CN104011664B (en) * 2011-12-23 2016-12-28 英特尔公司 Use super multiply-add (super MADD) instruction of three scalar items

Also Published As

Publication number Publication date
TWI263934B (en) 2006-10-11
CN100517212C (en) 2009-07-22
CN1591316A (en) 2005-03-09

Similar Documents

Publication Publication Date Title
CN101799705B (en) High-speed DDS signal generator
TW200623125A (en) Clock signal generation apparatus for use in semiconductor memory device and its method
ATE512399T1 (en) REGISTER BASED MOVEMENTS FOR A UNIDIRECTIONAL ROTATOR
WO2010051621A8 (en) Bridge device having a virtual page buffer
WO2006026526A3 (en) Memory system and method for strobing data, command and address signals
EP2026186A3 (en) Storage controller and method for controlling the same
WO2009097677A8 (en) Non-volatile memory device having configurable page size
SG166731A1 (en) Pcm memories for storage bus interfaces
TW200502756A (en) Memory device
BRPI0712109A8 (en) METHOD FOR COMMUNICATION WITH A MULTIFUNCTIONAL MEMORY CARD
EP1818941A3 (en) Semiconductor memory and data access method
TW200713651A (en) Method and structure for peltier-controlled phase change memory
KR20180005081A (en) Memory device having command window generator
ATE363715T1 (en) MEMORY MODULE WITH MULTIFUNCTIONAL STROBE CONNECTIONS
BRPI0408411A (en) mobile equipment for non-stationary use
TW200933643A (en) Semiconductor memory input/output device
TWI263934B (en) Synchronous periodical orthogonal data converter
TW200705167A (en) Power saving electronic device in microprocessor pipeline and method therefor
TW200746167A (en) Memory systems capable of reducing electromagnetic interference in data lines
DE502008003379D1 (en) DOCUMENT WITH AN INTEGRATED DISPLAY DEVICE
WO2002095592A3 (en) Method and apparatus to provide real-time access to flash memory features
CN107395002B (en) Inhibit the method and device of harmonic voltage
Smit Strategic planning: Readings
CN106897114A (en) A kind of digital analog interface and its driving method of the real-time simulator based on FPGA
WO2008154064A3 (en) External interface access control