TW200511727A - Interface circuit and signal clamping circuit using level-down shifter - Google Patents
Interface circuit and signal clamping circuit using level-down shifterInfo
- Publication number
- TW200511727A TW200511727A TW093121415A TW93121415A TW200511727A TW 200511727 A TW200511727 A TW 200511727A TW 093121415 A TW093121415 A TW 093121415A TW 93121415 A TW93121415 A TW 93121415A TW 200511727 A TW200511727 A TW 200511727A
- Authority
- TW
- Taiwan
- Prior art keywords
- circuit
- power
- level
- down shifter
- output
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0175—Coupling arrangements; Interface arrangements
- H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
- H03K19/018507—Interface arrangements
- H03K19/018521—Interface arrangements of complementary type, e.g. CMOS
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/003—Modifications for increasing the reliability for protection
- H03K19/00323—Delay compensation
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
- H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
- H03K3/356—Bistable circuits
- H03K3/356104—Bistable circuits using complementary field-effect transistors
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
- H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
- H03K3/356—Bistable circuits
- H03K3/356104—Bistable circuits using complementary field-effect transistors
- H03K3/356113—Bistable circuits using complementary field-effect transistors using additional transistors in the input circuit
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Mathematical Physics (AREA)
- Logic Circuits (AREA)
Abstract
This invention reveals an interface circuit and a signal clamping circuit using a level-down shifter. The interface circuit comprises the level-down shifter. The level-down shifter is built between a first power circuit and a second power circuit. The first power circuit is driven by a first power. The second power circuit is driven by a second power. The level-down shifter converts the output of the first power circuit that has a voltage level of the first power into the output of a voltage level of the second power. The level-down shifter includes a first circuit unit, a second circuit unit, a third circuit unit, and a fourth circuit unit. The first circuit unit is driven by the first power and receives the output of the first power circuit. The second circuit unit is driven by the second power, and receives the output of the first power circuit. The third circuit unit is driven by the second power and receives the output of the first power circuit. The fourth circuit unit is driven by the second power, it receives the output of the third circuit unit, and connects with the output of the second circuit unit.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR20030050268 | 2003-07-22 | ||
KR1020030084196A KR100585113B1 (en) | 2003-07-22 | 2003-11-25 | Interface circuit including level down shifter |
Publications (2)
Publication Number | Publication Date |
---|---|
TW200511727A true TW200511727A (en) | 2005-03-16 |
TWI336562B TWI336562B (en) | 2011-01-21 |
Family
ID=37223680
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW093121415A TWI336562B (en) | 2003-07-22 | 2004-07-16 | Lnterface circuit and signal clamping circuit using level-down shifter |
Country Status (2)
Country | Link |
---|---|
KR (1) | KR100585113B1 (en) |
TW (1) | TWI336562B (en) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR101004670B1 (en) * | 2008-12-01 | 2011-01-04 | 한국전자통신연구원 | Power gating circuit and semiconductor device comprising the same |
US9076510B2 (en) | 2012-02-02 | 2015-07-07 | Samsung Electronics Co., Ltd. | Power mixing circuit and semiconductor memory device including the same |
-
2003
- 2003-11-25 KR KR1020030084196A patent/KR100585113B1/en not_active IP Right Cessation
-
2004
- 2004-07-16 TW TW093121415A patent/TWI336562B/en not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
KR100585113B1 (en) | 2006-06-01 |
TWI336562B (en) | 2011-01-21 |
KR20050011650A (en) | 2005-01-29 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
GD4A | Issue of patent certificate for granted invention patent | ||
MM4A | Annulment or lapse of patent due to non-payment of fees |