TW200507719A - Conducting plate having top and bottom conductor layers electrically connected by vias - Google Patents

Conducting plate having top and bottom conductor layers electrically connected by vias

Info

Publication number
TW200507719A
TW200507719A TW093118373A TW93118373A TW200507719A TW 200507719 A TW200507719 A TW 200507719A TW 093118373 A TW093118373 A TW 093118373A TW 93118373 A TW93118373 A TW 93118373A TW 200507719 A TW200507719 A TW 200507719A
Authority
TW
Taiwan
Prior art keywords
vias
electrically connected
conducting plate
conductor layers
bottom conductor
Prior art date
Application number
TW093118373A
Other languages
Chinese (zh)
Other versions
TWI277379B (en
Inventor
Shigeki Miura
Original Assignee
Fcm Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fcm Co Ltd filed Critical Fcm Co Ltd
Publication of TW200507719A publication Critical patent/TW200507719A/en
Application granted granted Critical
Publication of TWI277379B publication Critical patent/TWI277379B/en

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0286—Programmable, customizable or modifiable circuits
    • H05K1/0287—Programmable, customizable or modifiable circuits having an universal lay-out, e.g. pad or land grid patterns or mesh patterns
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/03—Use of materials for the substrate
    • H05K1/0393—Flexible materials
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/095—Conductive through-holes or vias
    • H05K2201/09609—Via grid, i.e. two-dimensional array of vias or holes in a single plane
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/42—Plated through-holes or plated via connections
    • H05K3/425—Plated through-holes or plated via connections characterised by the sequence of steps for plating the through-holes or via connections in relation to the conductive pattern
    • H05K3/426—Plated through-holes or plated via connections characterised by the sequence of steps for plating the through-holes or via connections in relation to the conductive pattern initial plating of through-holes in substrates without metal

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
  • Structure Of Printed Boards (AREA)
  • Insulated Metal Substrates For Printed Circuits (AREA)

Abstract

The present invention relates to a conductor having top and bottom conductor layers electrically connected by vias. The conducting plate 7 pertains to one formed with conductor layers 6 on the top and bottom layers of the insulated substrate 1. The top and bottom conductor layers 6 are electrically connected by the vias 2 disposed in a manner penetrating the insulated substrate 1. The conducting plate 7 is characterized by forming a conductor layer 6 with an identical composition on the top and bottom sides of the insulated substrate 1 and the walls of the vias 2.
TW93118373A 2003-06-24 2004-06-24 Conducting plate having top and bottom conductor layers electrically connected by vias TWI277379B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2003179343A JP2005019513A (en) 2003-06-24 2003-06-24 Conductive sheet

Publications (2)

Publication Number Publication Date
TW200507719A true TW200507719A (en) 2005-02-16
TWI277379B TWI277379B (en) 2007-03-21

Family

ID=33535062

Family Applications (1)

Application Number Title Priority Date Filing Date
TW93118373A TWI277379B (en) 2003-06-24 2004-06-24 Conducting plate having top and bottom conductor layers electrically connected by vias

Country Status (3)

Country Link
JP (1) JP2005019513A (en)
TW (1) TWI277379B (en)
WO (1) WO2004113065A1 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2146561A1 (en) * 2008-05-28 2010-01-20 LG Electronics Inc. Flexible film and display device including the same
EP2129199A1 (en) * 2008-05-28 2009-12-02 LG Electronics Inc. Method of manufactoring flexible film

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5637719B2 (en) * 1973-03-28 1981-09-02
JPS6295894A (en) * 1985-10-23 1987-05-02 株式会社エイト工業 Formation of through hole substrate
JPH02301187A (en) * 1989-05-16 1990-12-13 Casio Comput Co Ltd Manufacture of both-sided wiring board

Also Published As

Publication number Publication date
TWI277379B (en) 2007-03-21
WO2004113065A1 (en) 2004-12-29
JP2005019513A (en) 2005-01-20

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Legal Events

Date Code Title Description
MK4A Expiration of patent term of an invention patent