TW200500896A - Scan insertion with bypass logic in an IC design - Google Patents

Scan insertion with bypass logic in an IC design

Info

Publication number
TW200500896A
TW200500896A TW093113021A TW93113021A TW200500896A TW 200500896 A TW200500896 A TW 200500896A TW 093113021 A TW093113021 A TW 093113021A TW 93113021 A TW93113021 A TW 93113021A TW 200500896 A TW200500896 A TW 200500896A
Authority
TW
Taiwan
Prior art keywords
hdl
bypass
scan
instruction
port
Prior art date
Application number
TW093113021A
Other languages
Chinese (zh)
Inventor
Steve C Huang
I-Hao Chen
Original Assignee
Incentia Design Systems Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US10/435,329 external-priority patent/US6973631B2/en
Application filed by Incentia Design Systems Corp filed Critical Incentia Design Systems Corp
Publication of TW200500896A publication Critical patent/TW200500896A/en

Links

Abstract

A computer implemented process of inserting enhanced scan bypass in relation to a bypassed block in an integrated circuit design comprising: receiving an HDL description of the circuit design; wherein the HDL description includes a port specification HDL instruction that specifies port properties of a bypassed block; wherein the HDL description includes an enhanced bypass HDL instruction that specifies how many scan cells to provide per port of the bypassed block in a scan bypass circuit that bypasses the bypassed block; wherein the bypass HDL instruction includes a user-selectable option of at least zero or one or two scan cells per port; in response to the specification HDL instruction and the enhanced bypass HDL instruction, automatically generating a netlist portion that includes scan a bypass circuit that bypasses the bypassed block and that includes the specified number of scan cells per port.
TW093113021A 2003-05-09 2004-05-07 Scan insertion with bypass logic in an IC design TW200500896A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US10/435,329 US6973631B2 (en) 2002-07-18 2003-05-09 Scan insertion with bypass login in an IC design

Publications (1)

Publication Number Publication Date
TW200500896A true TW200500896A (en) 2005-01-01

Family

ID=57797976

Family Applications (1)

Application Number Title Priority Date Filing Date
TW093113021A TW200500896A (en) 2003-05-09 2004-05-07 Scan insertion with bypass logic in an IC design

Country Status (1)

Country Link
TW (1) TW200500896A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI466124B (en) * 2011-05-27 2014-12-21 Realtek Semiconductor Corp Testing system

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI466124B (en) * 2011-05-27 2014-12-21 Realtek Semiconductor Corp Testing system

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