TW200428757A - Driving circuit for high frequency signal - Google Patents

Abstract

A driving circuit for outputting high-frequency signal. The first NMOS transistor includes a first drain coupled to a first voltage level, a first gate coupled to the output terminal of the first operational amplifier and a first source coupled to the input terminal of the first operational amplifier. The first PMOS transistor includes a second drain coupled to a second voltage level, a second gate coupled to the output terminal of the second operational amplifier and a second source coupled to the input terminal of the second operational amplifier. The matching resistor having a predetermined resistance is coupled between the first source and the second source. The second NMOS transistor includes a third drain coupled to the first voltage level, a third gate coupled to the output terminal of the first operational amplifier and a third source. The second PMOS transistor includes a fourth drain coupled to the second voltage level, a fourth gate coupled to the output terminal of the second operational amplifier and a fourth source. The output resistor includes a first terminal, a second terminal and the predetermined resistance. The switching device connects the first terminal and the third source and the second terminal and the fourth source or connecting the first terminal and the fourth source and the second terminal and the third source.

Description

200428757 V. Description of the invention (l) [Technical field to which the invention belongs] The present invention relates to a driving circuit, and more particularly to a driving circuit that outputs a high-frequency signal in a voltage switching mode. [Prior Art] FIG. 1 is a circuit diagram showing a conventional driving circuit. The source of the PM0S transistor P1 〇 is coupled to the current source 1 〇, the complex switch T1Λ, and the pole is coupled to the NMOS transistor N10, and the source of the NMOS transistor N10 is $ + aw 〇λτ Said μΜι Λ tu you are coupled to the current source 1 2. The NM0S electric sun body N1 0 and the PM0S transistor P1 〇 gate damage bismuth pyne ^ θ U 乜 is coupled to the inverting input terminal DN. The source of the PM0S transistor P1 2 is coupled to Lei Wei ^ MUAO _ w sets the main wide current source 10, whose drain is coupled == Γ12, and the source of the transistor N10 is coupled to the current =. The gate of the transistor N12 and the transistor P12 is coupled to the non-inverting input terminal D. The output resistance 14 includes the terminal rn vn NM0S transistor N10 and the PM0S transistor p1 () * ^ φ ". In addition, it is coupled to the connection between the crystal ship 2 and the PMGS transistor, and the resistance 15A and the resistance The voltage level of the first input terminal is the average voltage level of the terminals Q and QN. And wm ^ ν, ^ ^ ^ dagger state 16 compares the difference between the 2 input level of the first input terminal and the reference voltage vref level of the second input terminal, and the average value of the voltage level of EFf i12MwQ # QN It is the same as the reference voltage F. Therefore, the voltage difference at the terminal Q_ is kept constant. The traditional driving circuit shown in the figure is operated in the general feedback current switching mode (current mode w i Α Ί

Wlth common mode feedback), at the input, the terminal D and the inverting input paste are opposite to each other, so when the input terminal D receives a high level signal, the inverting input terminal ⑽ receives

200428757 V. Description of the invention (2) === No. Therefore, the PMOS transistor P1G and the transistor N12 / P12 and NMOS transistor N10 are turned off. Therefore, the current = cake Q flows to the terminal ⑽ via the resistor 14. Therefore, the voltage level at the terminal C: C is controlled by the comparator i6, and its long-term input terminal D receives the low level and the input DN receives the high level signal. Therefore, _transistor 1 1 Βθθ ^ N10 f ^ PM0S f aBa ^ pi °-the sub-Q due to t ϋ Γ Therefore, the current flows from the terminal QN to the terminal 2 through the resistor. Therefore, a constant potential difference occurs at the terminal Q _, and The 5 levels of end-to-end power are controlled by comparator 16. When supplied to the non-inverting input terminal = when the signal is low frequency, 'comparator 16 adjusts the voltage levels of terminals Q and QN to reach the expected value. I 电 当When the data is transmitted at a high frequency, the € stream is fixed, so the potential difference between the two ends of the content TD and the inverting input DN is quite low. Provided: d: In order to solve the above-mentioned stomach problem, the main purpose of the present invention is to provide- It is enough to output a signal with a fixed potential difference and an adjustable voltage range. When the purpose of st 'is proposed, the present invention proposes a high-frequency signal to drive the electric input terminal 1 to the second input terminal, and the first-round output. Put = ”Connected to the second first input of the second reference voltage:-Input ... and the second output. The first _ crane transistor has

200428757 V. Description of the invention (3) The first drain coupled to the first voltage level, coupled to the -gate, and coupled to the first and second input terminals: the second M0S transistor Have a transfer to the second electric cap? . The first-second connection: the second closed electrode of the second output terminal, and the second / second-second and second, between the second source and the second source. The second first type_transistor has a third pole connected to the ^-voltage level, connected to the second input of the first input = the second pole of the second second to the second output terminal. Four, two two fourth source. The load impedance has a first terminal and a second terminal, and the constant resistance 胄 ° switching device is used to electrically connect the first terminal and the second source, and the second terminal and the fourth source at the same time. With the third source. f 一 四 四 4 [Embodiment] ^ Example: Refer to FIG. 2A, which shows a driving circuit according to an embodiment of the present invention. The operational amplifiers 20 and 21 include a non-inverting input terminal, an inverting input terminal, and an output terminal, respectively. The inverting input terminals of the operational amplifiers 20 and 21 are respectively coupled to the test voltages Vtop and Vbot. The gate of the NMOS transistor N20 is coupled to the output of the operation amplifier 20, the drain is coupled to the electric #Vcc, and the source is coupled to the switch 2 4 A. The gate of the PM0S transistor P20 is coupled to the output terminal of the operational amplifier 21, its drain is coupled to the ground point, and the source is coupled to the inverting input terminal of the operational amplifier 21. The source of the PM0S transistor P2〇 is always on

0697-8885TWF (Nl); P2002-045-TW-A; ROBERT.ptd Page 9 200428757 V. Description of the invention (4) The switch 2 4 B is electrically connected to the inverting input terminal of the operational amplifier 21 1 and its connection The point number is 22B, and the source of the NMOS transistor N20 is electrically connected to the inverting input terminal of the operational amplifier 20 through the always-on switch 24 A, and the connection point number is 2 2A. The functions of the changeover switches 24A and 24B will be described below. The matching resistor 23 has a predetermined resistance value and is coupled between the connection points 2 2 a and 2 2B. The gate of the NM0S transistor N22 is coupled to the output terminal of the operational amplifier 20, and the gate is lightly connected to the power source V c c. The gate of ρ μ 〇 S transistor p 2 2 is connected to the output terminal of operational amplifier 21, and its drain is coupled to the ground point. In the present invention, the NMOS transistor N20 and N22 have the same size, and the PMOS transistor P20 and P22 have the same size. One terminal Q of the resistor 25 is selectively coupled to the source of the NMOS transistor N22 or the source of the PM0S transistor P2f according to the switch 26, and the other terminal Qn of the resistor 25 is selected according to the switch 26B. It is coupled to the source of pM0s transistor P22 or the source of NMOS transistor N22. The terminal Q is connected to the connection point of the body N22; the ^ symbol is 27A, and the connection point of the terminal Qn and the pMOS transistor P22 is 27B. Here, the resistance value of the resistor 25 is the same as that of the matching resistor 23. Switch The switches 26A and 26B are switched on at the same time. When the switch 26a is electrically connected to the resistor 25 and the connection point 27A, the switch 26β must be electrically connected to the resistor 25 and the connection point 27B. In contrast, when the switch m is electrically The connection resistance 2 5 and the connection point 2 7 B 0 ^ ·, the switch 2 6 b must be electrically connected to the resistance 2 5 and the connection point 27A 1. Here, the 'change switches 24A, m, 26 and _ are the same Electronic components such as transfer gates.

0697-8885TWF (Nl); P2002-045-TW-A; ROBERT.ptd Page 10 200428757 V. Description of the Invention (5) "-The operational amplifiers 20 and 21 are turned on respectively. 05 transistor N2 () and ...? And PMOS transistors P20 and P22. Since the non-inverting input terminal and the inverting input terminal of the operational amplifier 20 are ideally coupled, the voltage level of the connection point 22 A is approximately the same as the reference voltage Vtop. Similarly, the voltage level of the connection point 22β It is approximately the same as the reference voltage Vbot. Therefore, a current flows from the connection point 2 2 A to the connection point 2 2 B through the resistor 2 3. As mentioned above, the N M 0 S transistors n 2 0 and N 2 2 have the same electronic characteristics, such as threshold voltage Vt, channel aspect ratio (W / L), bias state, and m 0s. Transconductance (gm) between transistor source and gate. And the electrical characteristics of PM0S transistor P20 and P22 are also the same. The impedance values of the resistors 23 and 25 are also the same. Therefore, when the changeover switch 2 6 A is coupled to the connection point 2 7 A and :: the changeover switch 2 6 B is connected to the connection point 27B, the connection point 27A and the reference voltage V t op have the same voltage level and are connected The electrical level of the point 2 7 B and the reference voltage vb ot is also the same. Opposite 'when the switch 2 6 A is coupled to the connection point 2 7 B and the switch 2 6 B is coupled to the connection point 27A, the voltage level of the connection point 27A is the same as the reference voltage Vbot, and the connection point 27B and the reference The voltage level of the voltage Vtop is also the same. Here, the terminals Q and Qn are output terminals of the driving circuit, and are used to output signals having a constant voltage difference and the upper and lower limits of the voltage values are the reference voltages Vt0p and several 1: 1. By switching switches 26 A and 2 6B at the same time, the voltage levels of terminals Q and Qn are switched between the reference voltages "〇1) and ¥ 1) 〇1: Figure 2B shows a display similar to the upper part of Figure 2A Circuit diagram. The gates of the nmos transistor N 3 0 and N 3 2 are connected to the output of the operational amplifier 3 0, and the drain is coupled to the power source Vcc. The inverting input of the operational amplifier 3 0 is

〇697-8885TW (Nl); P2002-045-TW-A; ROBERT.ptd Page 11 200428757 V. Description of the invention (6) = Test voltage Vtop. The source of the round s transistor N30 is connected to the switch = 4 =. The inverting input terminal of the operational amplifier 30 is connected to the other terminal of the switching switch 34A. The _ terminal of the resistor 33A is connected to the switch 34A: and the other terminal of the resistor 33A is coupled to the ground point. Here, the resistance 33A is a water-conducting it. Furthermore, the terminal of the switch 36a is lightly connected to the source of the transistor N32 and selectively electrically connects one terminal of the resistor 37A or 37β. Furthermore, the other ends of the t-resistance 37A or 37B are connected to the ground point respectively. For the reasons described above, a resistor coupled to the source of the transistor N32 or one of the terminals 37B outputs a signal having a reference voltage Vt0p level. Figure 2C shows a circuit diagram similar to the lower half of Figure 2A. The gates of the pM0s transistors P30 and P32 are coupled to the output terminal of the operational amplifier 31, and the drains thereof are coupled to the ground point. The inverting input terminal of the operational amplifier 313 receives a reference voltage Vbot. The source of the PM0S transistor P30 is connected to the switch 3 4B. The inverting input terminal of the operational amplifier 31 is coupled to the other terminal of the switch 34B. One end of the resistor 33B is coupled to the switch 34B, and the other end of the resistor 33B is coupled to the power source Vcc. Here, the resistor 33B is always on. Furthermore, one terminal of the switch 36β is coupled to the source of the four-cell transistor P32 and is selectively electrically connected to one terminal of the resistors 38A to 38B. In addition, the other ends of the resistors 38A or 38B are each coupled to the power source Vcc. For the reasons described above, one end of the resistor 38A or 38B coupled to the source of the pM0s transistor p32 has a reference voltage Vb. Quasi-signal. The circuit shown in Figures 2B and 2C constitutes the circuit shown in Figure 2A.

Circuit. As shown in Figure 2A, the output circuit according to the embodiment of the present invention uses a source (or emitter) to follow (source 〇r emitter f0ll0WS

0697-8885TWF (N1); P2002-045 · TW-A; ROBERT.ptd Page 12 200428757 V. Description of the invention (7)

), And by switching switches 27A and 27B to the output terminal, such as the output voltage, so the output impedance is quite low. Furthermore, when the data changes, the transient voltage Vgs (transient voltage) increases. Therefore, the output circuit according to the embodiment of the present invention can provide a large current and quickly switch the voltage between the output terminals q and Qn. Furthermore, the output circuit according to the embodiment of the present invention uses the same feedback architecture as the output circuit to generate a control voltage (reference voltages Vtop and Vbot), and makes the output voltages of the output terminals q and Qn and the reference voltage V top and Vbo t is the same. Therefore, the average value (median value) of the output voltages at the output terminals q and Qn remains fixed. Moreover, the output voltage values of the output terminals Q and Qn can be adjusted by changing the values of the reference voltages Vt0p and Vb0t. Therefore, the output circuit according to the embodiment of the present invention is suitable for outputting various audio signals, such as transition minimized different i signalings (TMDS), universal sgrial bus (USB), or 疋Low-voltage differential signal ing, etc. In addition, the impedance between the source and gate of the NMOS transistor N22 and the PMOS transistor P 2 2 (^ r an s c 〇 n d u c t a n c e, g m) can be adjusted to a suitable match. In addition, the output according to the embodiment of the present invention

The output of the output circuit follows the source, so its output voltage can be more independent of the input voltage. Although the present invention is disclosed as above with a preferred embodiment, it is not intended to limit the scope of the present invention. Any person skilled in the art can make some changes and decorations without departing from the spirit and scope of the present invention. The protection scope of the present invention shall be determined by the scope of the attached patent application.

〇697.8885TWF (Nl); P2002-045-TlV.A; ROBERT.ptd page 13 200428757 The diagram is briefly explained in order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy. The following is a preferred embodiment And, in accordance with the drawings, make a detailed description of the following: ° Month as illustrated: Figure 1 is a circuit diagram of a traditional drive circuit. FIG. 2A shows a driving circuit according to an embodiment of the present invention. Figure 2B is a circuit diagram similar to the upper half of Figure 2A. Figure 2C shows a circuit diagram similar to the lower half of Figure 2A. Explanation of symbols: 1 0, 1 2 ~ current source 14, 15A, 15B, 23, 25, 33A, 33B, 37A, 37B, 38A, 38B ~ resistor

1 6 to comparator 20 to 2 30 30 31 31A, 22B, 27A 24A, 24B, 26A D ~ Non-inverting input terminal DN ~ Inverting input terminal N10, Ν12, Ν20 P10, PI 2, P20 Q, QN ~ terminal VREF, V top, Vbot V cc ~ Power Q, Qn ~ Output

^ Operational amplifier 2 7 B ~ Connection points 26B, 34A, 34B 36B ~ Switch N22 P22 N30 P30 N32 P32 Reference voltage

NM0S transistor PM0S transistor ❿ 0697-8885TWF (N1); P2002 · 045 · TW-A; ROBERT.ptd page 14

Claims (1)

200428757 VI. Patent application scope I A high-frequency signal driving circuit, including: a first operational amplifier, including a first input terminal coupled to a first input terminal, a second input terminal, and a first; A second operational amplifier, which includes a coupling pin-connected to a younger brother, a younger brother, and an input terminal connected to a younger brother and a reference voltage, a first and a second terminal, and a second input terminal, and a second terminal. Output-first first drain-level coupling coupled to the first first-level calibration-coupled to two-source level and one-level-type M0S transistor having a coupling to a first The voltage level is coupled to the first gate of the first output terminal and the first source of the second input terminal; The resistance value is coupled to the first source and the first M0S transistor, and has a second gate electrode connected to a second voltage terminal: and a type M0S transistor, which has a consumption at the first voltage. Pole, which is coupled to the third gate of the first output terminal, and is a -type M0S transistor, Blessed is connected to the above-mentioned second voltage electrode, and connected to the above-mentioned Φ and a fourth source; the fourth gate of the output terminal 钿 has a first resistance value with -load impedance '; and Zhiziya has a switching device to connect the first terminal and the above-mentioned 0697-8885TWF (Nl); P2002-045-TW-A; Robert.ptd Page 15 200428757 at the same time. The scope of the patent application is the third source and the second terminal and the fourth source, or the first terminal and the fourth source and the second terminal and the third source. 2. The high-frequency signal driving circuit according to item 1 of the scope of patent application, wherein the size of the first first type M0S transistor and the second first type M0S transistor are the same. 3. The high-frequency signal driving circuit according to item 2 of the scope of patent application, wherein the size of the first and second type M0S transistors is the same as that of the second and second type M0S transistors. 4. The high-frequency signal driving circuit according to item 1 of the scope of the patent application, wherein the first first type M0S transistor and the second first type M0S transistor NM0S transistor. 5. The high || signal driving circuit as described in item 1 of the scope of the patent application, wherein the first and second type M0S transistors and the second type 2 M0S transistor system are PM0S transistors. 6. The high-frequency signal driving circuit according to item 1 of the scope of patent application, wherein the switching device includes: a first transmission gate coupled between the first terminal and the third source; a second A transmission gate coupled between the first terminal and the fourth source; a third transmission gate coupled between the second terminal and the third source; and a fourth transmission gate coupled Between the second terminal and the fourth source. 0697-8885TWF (Nl); P2002-045-TW-A; ROBERT.ptd Page 16 200428757 VI. Patent application scope 7. The high-frequency signal driving circuit as described in item 6 of the patent application scope, wherein the first transmission The gate system is turned on simultaneously with the third transmission gate. 8. The high-frequency signal driving circuit according to item 7 of the scope of patent application, wherein the second transmission gate and the fourth transmission gate are simultaneously turned on. 9. The high-frequency signal driving circuit according to item 1 of the scope of the patent application, wherein the matching impedance and the first source further include a fifth conductive gate which is permanently on. 10. The high-frequency signal driving circuit according to item 1 of the scope of the patent application, wherein the sixth transmission gate is permanently connected between the matching impedance and the second source. 0697-8885TWF (Nl); P2002-045-TW-A; R0BERT.ptd Page 17