TW200428528A - Metal damascene process - Google Patents

Abstract

A metal damascene process is disclosed. In the metal damascene process, a metal layer is formed to cover a dielectric layer and to fill up an opening in the dielectric layer by using a super-filling method. Next, a transient chemical mechanical polishing (CMP) step is performed on the metal layer to planarize the metal layer. Then, a reverse electrical plating step is performed to remove a portion of the metal layer until the dielectric layer is exposed. While the portion of the metal layer is removed, the end point of the reverse electrical plating step can be detected by monitoring the current of the electrolyte.

Description

200428528 V. Description of the invention (1) [Technical field to which the invention belongs] The present invention relates to a metal damascene process, and in particular, to a phenomenon capable of avoiding shallow metal disks (Di shing), The metal damascene process can prevent over-etching of the metal layer and the dielectric layer, the phenomenon, and the scratch on the surface of the dielectric layer. [Previous technology] Faced with the market's demand for thin, light and short electronic components, the size of the line width of integrated circuit components has been continuously reduced, and with the line width of integrated circuit components

The miniaturization of the size has caused the operation speed of the device to be significantly affected by the resistance capacitance delay (Resistance Capacitance Delay; RC Delay) and the increasingly serious electromigration (£ 16 (: 1; 1'01111 avoid ^ 1: 丨 011). Slow down. Because of the current, high-density circuit designs, it is necessary to discard traditional resistors that have lower resistance and better resistance to electromigration, such as copper (Cu) metals. As the inner interconnection of the component, the integrated electric metal layer component can be divided into copper, and the other conductive wire is currently divided into low dielectric sweat and the number of components. The calculation speed is the wire surface, and the constant material is used for the area. Copper can withstand such a degree. And the components in the process geometry are made of metal copper material to make the low resistance more dense, and the non-copper has a more up-to-date change as the circuit arrangement for the metal W ^ W Ί I ~ Therefore, it can be greatly reduced, which can only reduce the production cost, can improve the anti-electromigration ability, and can achieve a long life and better stability. The limitation of the wire material makes it difficult to change Reduce the capacitance value of the parasitic Thus, within the outer member = wiring material, more insulating material between the lines, to further

$ 5 pages 200428528 V. Description of the invention (2) Reduce the parasitic capacitance between the wires. The reduction of the parasitic capacitance value can not only greatly improve the speed performance of the device, but also reduce the power consumption (Power Dissipation) and cross-talk noise (Cross-talk Noise), and effectively improve the operation performance of the device. _ However, when copper is used as a component wire, it faces the problem that copper cannot be patterned using traditional dry etching (Dry Etching) technology. In order to solve the patterning problem of copper wires, a damascene method has been developed to make copper wires. The copper wire inlay technology first fills copper metal into the openings of the dielectric layer where the metal wire patterns have been formed, and then uses a grinding technique to remove excess copper metal outside the openings of the dielectric layer to complete the copper metal inlay. At present, the above-mentioned metal copper polishing technology generally uses chemical mechanical polishing (CMP) technology. Please refer to Fig. 1 to Fig. 3. Figs. I to 3 are cross-sectional views showing a conventional metal inlaying process. First, a semiconductor substrate 100 is provided, and then a dielectric layer 102 is deposited to cover the substrate 100. The material of the dielectric layer 102 is a low dielectric constant material. After the dielectric layer 102 is formed, a portion of the dielectric layer 102 is removed using lithography and etching techniques, and an opening 104 is formed in the dielectric layer 102 and a portion of the substrate 100 is exposed. As shown in Figure 1. Next, a 'conformal' deposition of the diffusion barrier layer 106 covers the dielectric layer 102 and the exposed substrate 100. Then, metal ^ 1 08 is formed by plating to cover the diffusion barrier layer 6 and fill the opening 4 to form a structure as shown in FIG. 9 and FIG. 2. Among them, the diffusion barrier layer 6 is used to prevent the subsequently formed metal layer 108 from diffusing into the dielectric layer 102 and the substrate 100. In addition, to ensure that the metal layer 108 can fill the opening 104, a thicker metal layer 108 needs to be formed. Head 200428528 V. Description of the invention (3) The material of the front metal layer 108 is generally steel. ΐ ΐ2: Remove part of the metal layer 108 by chemical mechanical polishing

The LtrU layer 102 'and a metal layer are formed in the opening 104 of the dielectric layer 102 as shown in FIG. 3. Because the thickness of the metal layer 108 was relatively dry in order to ensure 204, the removal of the opening 104 ”= 108 requires a considerable grinding time. In addition, since the material of the diffusion barrier layer 106 used to prevent the diffusion of copper metal is mostly a button (Ta) or a nitride button (TaN), it is quite difficult to grind either the button or the nitride button. As a result, the polishing speed between the metal layer 110 and the diffusion barrier layer 106 will cause a considerable difference, and a shallow dish area pit i 2 will be formed on the metal layer 110, as shown in FIG. 3 I . In addition, _6 is caused in the dielectric layer 102 and the metal layer 11 (), as shown in FIG. 4, and the effects of planarization and size control of the chemical mechanical polishing process are greatly reduced. In addition, since the dielectric layer is composed of a low dielectric constant material with a rather fragile structure. Therefore, the polished surface of the dielectric layer 〇 2 will produce quite severe scratches 11 4 or even crack, which will cause the process yield to decrease. [Summary of the Invention] The object of the present invention is to provide a metal damascene process, which uses super-filling (Super-Fi 11 ing) method to fill metal into the dielectric layer. A metal layer can fill the opening. In this way, not only can the time for forming the metal layer be reduced, but also the material expenditure and process cost can be reduced. Another object of the present invention is to provide a metal damascene process, which utilizes a known chemical mechanical polishing process to planarize the metal layer, and then utilizes counter-current

Page 7 200428528 V. Description of the invention (4) Reverse Electrical Plating method (ie electrolytic method) Excess metal layer except opening. In this way, the CMP process will directly act on the dielectric layer. Therefore, it is possible to effectively prevent the surface of the dielectric layer from being damaged to ensure the quality of the dielectric layer, to avoid excessive phenomena of the dielectric layer and the metal layer, and to improve the ability to control the size of the dielectric layer and the metal layer. Another object of the present invention is to provide a metal damascene process. Chemical mechanical polishing is only used to planarize the metal layer, and the metal layer in the opening 2 is removed by an anti-electroplating method. Therefore, the surface of the metal wire in the opening can be prevented from generating a shallow dish area, and the electrical quality of the metal wire can be improved, thereby further mentioning the electrical stability of the piece. In light of the above-mentioned object of the present invention, a metal inlaying process is proposed, which includes at least the following steps: First, a substrate is provided, wherein at least a dielectric layer is formed on the substrate, and at least one opening is exposed in the dielectric layer. Part I substrate. A metal layer is formed to cover the above-mentioned dielectric layer and the exposed material, and fill the opening. Wherein, before forming the metal layer, a diffusion barrier layer may be formed in a bi-composite mode to cover the dielectric layer and the exposed substrate ^ ^ and then formed by sputtering deposition (Sputtering DeposUon). Then, for example, Chemical Mechanical Research ^ The metal layer is partially removed to planarize the metal layer.然 = 二 解 液 + ’and the metal tube is used as the anode i, and the explosion i :::: is expanded; a metal wire is formed in the opening. According to a preferred embodiment of the present invention, the power-on layer may have a low dielectric constant. 200428528 V. Description of the invention (5) The material, and the metal layer may be copper. The plug of the metal layer is formed in such a manner that the metal layer has a protrusion a 5 U and is overfilled. In addition, in the reverse plating step, the current above 仏 and βϊ 1 can be used to obtain the end of the reverse plating step. Because of the electrolyte in the surgery magic, the metal layer is formed by the overfill method, so that the part can be removed. Therefore, the metal layer does not need a shovel to form a notch above the opening, and it only needs to be carried out for a short period of time; Therefore, the metal layer can be shortened so that the surface of the metal layer belongs to the material, and the purpose of reducing the cost of the process is reduced. In addition, because the chemical mechanical polishing step is only required, the extra metal layer outside the mouth is made of demetalized metal. Layer, which is not exposed to chemical mechanical polishing; remove it. Due to the wires, it is possible to prevent the dielectric metal layer and the metal dishing in the openings, and the metal layer from cracking, and the surface of the metal wires to effectively control the size of the metal wires. Therefore, it is possible to further improve the lightning protection of the component; the quality of the electrical layer and the metal wire, [implementation] The quality of the first embodiment. The present invention discloses a metal inlaying system for filling a small metal layer into an opening, followed by a garment process, which uses an overfilling method to form a gold layer, and then chemically grinds and flattenes the metal with an anti-plating method to form a metal wire. Therefore, in addition to the metal layers other than the openings, the grinding time of the openings can reduce the process and materials. 1 Reduce the plating of the metal layers and avoid the metal layer and the dielectric layer. Besides, it can prevent the dielectric layer from scratching , The surface has a shallow dish-like phenomenon. Such as excess phenomenon, and can prevent the coming of metal wires ’can improve the process reliability, up to 200428528

To the purpose of increasing product yield. In order to complete the description of the present invention, you can refer to the following description and cooperate with Figures 5 to 10 for more power ^ and please refer to Figures 5 to 10, and Figures 5 to 1 (). A cross-sectional view of a metal inlay process in a preferred embodiment of the invention. First, a semiconductor substrate 200 is provided. The substrate 200 may include components and interconnect structures. A dielectric layer 200 is formed on the substrate 200 by using a method such as chemical vapor deposition (CVD). The material of the dielectric layer 202 may be, for example, a low dielectric constant material. After the dielectric layer 202 is formed, it is defined using, for example, lithography and etching techniques, and the wire pattern is transferred to the dielectric layer 202, and an opening 204 is formed in the dielectric layer 202, and a part is exposed The substrate 200 is formed into a structure as shown in FIG. 5. After the opening 204 is formed, a thin diffusion barrier layer 206 is formed on the dielectric layer 202 and the substrate 200 exposed by the opening 204 by, for example, conformal deposition to prevent the subsequently formed metal material from diffusing to the substrate. Material 200 and the dielectric layer 200 to ensure electrical quality. After the diffusion barrier layer 2006 is completed, a relatively thin seed layer (not shown) is co-deposited on the diffusion barrier layer 2006 by means of, for example, base plating deposition. The seed layer may be made of copper, for example. Next, a metal layer 208 is formed on the seed layer by using, for example, an overfill technique and an electroplating deposition method 4, and the metal layer 208 fills the opening 204, and the metal layer 208 has a protrusion 210 above the opening 204, and is formed as Figure 6 shows the structure. The material of the metal layer 208 may be copper, for example. In the overfilling technology of a preferred embodiment of the present invention, a negative dielectric active agent is added to the electric shovel solution of the metal layer 208, so that the recessed opening area 204

Page 10 200428528 V. Description of the invention (7) The plating rate is higher than the plating rate on the planar areas on both sides of the opening 204. In this way, the protruding portion 21 0 of the metal layer 208 can be smoothly formed above the opening 204. One feature of the present invention is that the metal layer 208 is formed by the overfill method, which can accelerate the speed at which the metal layer 208 fills the opening 204. Therefore, in the case where the metal layer 208 on the dielectric-electrical layer 202 outside the opening 204 is not too thick, the opening 204 is already filled with the metal layer 208. Therefore, ′ can shorten the time of electro-mineral deposition of the metal layer 208, and can reduce the material required to form the metal layer 208. After the metal layer 208 is formed, the end point of the polishing is controlled by, for example, chemical mechanical polishing, and in a time mode, for example, and a portion of the metal layer 208 ′ is polished to flatten the surface of the metal layer 208 to form a surface as shown in FIG. 7. Knot structure. Among them, the above grinding step only needs to make the surface of the metal layer 208 flat, and there is no need to remove the metal layer 208 above the diffusion barrier layer 206. When the metal layer 208 is planarized, the surface of the metal layer 208 can be made flat only by a relatively short grinding process to remove the protrusion 210 of the metal layer 208. Another feature of the present invention is that the metal layer 208 is above the opening 204 and has a protrusion 210. Therefore, compared with the conventional co-deposition technique, most of the present invention requires only grinding when planarizing the metal layer 208. In addition to the protruding portion 21 above the opening 204, that is, two, instead of having to grind both sides of the opening 204 to complete the metal exhibition, it is possible to shorten the grinding time. After the planarization of the metallization layer 208, the substrate 200 is placed in the dielectric layer thereon. Then VV and //: 6, seed layer, and metal layer 2 ° 8 immersed in the electrolyte metal layer: as ^ and on the same day τ, immerse the electroplated cathode 2 1 2 200428528 5. Description of the invention (8) Power , And the structure shown between the cathode 212 and the metal layer 208. The material of the cathode 212 may be, for example, copper, or a general metal. By means of the two-t anti-electroplating method, that is, the electrolytic method, the original part of the electrical layer 2: the metal layer 208 on the barrier layer 206 is deposited and lost until the diffusion barrier layer 206 outside the opening 204 is exposed to form a metal. Layer 216, and a structure shown by gold ^ Γ, τ㈣ in the opening 204 is formed. The distribution of the anode electrode in the metal layer 208 is the distribution of the entire anode electrode in the metal layer 208 to control: it belongs to 208, and the thickness is uniform during the electroplating. One of the present invention is preferred < ί & η-: Γ uses a detector to measure the current of the copper ion (Cu2 +) in the electrolyte at a concentration of L = 4 3 to detect the end of the back electroplating. The end of most of the diffusion barrier layer 20 6: Ξί, Γ: There will be a significant drop, you can know the reason of the anti-plating step ^ ^ It is also possible to use other methods to detect the end of the anti-plating step, not limited to The above method. ~ Another special feature of the present invention is the 4 k ^ π A line. The grinding process is only used to flatten the metal type, that is, the square of the electrolysis. Remove the square (removed. Therefore, the extra metal layer 208 outside the opening m will not touch the opening = and will directly cause stress on the dielectric layer 002 to scratch: d 〇4. Therefore, the dielectric layer 2 ° 2 will not cause a shallow dish area due to grinding: the surface of the metal layer 214 in torpedo = 204 and the dielectric layer 20 2 and metal layer 214

Page 12 200428528 5 », description of the invention (9) Erosion occurs.

After the technique of etching in the opening 204 is performed, the metal layer 214 is removed and formed into the metal layer 214, and the diffusion barrier layer 206 outside the dielectric layer 20 ?, 204 under, for example, dry etching or wet etching is exposed and exposed. The inlaid JJ of the bottom metal layer 21: has the structure shown in FIG. 10. So far, the example has been completed, it can be known that the advantage of the present invention is that it can be deposited without: too, that is, the opening filled in the dielectric layer, and the metal layer is effectively filled with sound. Reduced gold: use, advance = and flattening time, and can reduce the material of the metal layer to the purpose of reducing process costs. It can only be seen from the example of the 车-月 moon car that the present invention has another advantage. Another advantage of the present invention is that the anti-electromechanical grinding process is used to planarize the metal layer. The mechanical action acts on the dielectric layer and contacts the opening. Therefore, the shallow force that can effectively prevent the sinking is well known, and the surface of the metal layer can be prevented from being depressed; °°, which can also prevent the over-etching of the dielectric layer and the metal layer. By increasing the quality of the dielectric layer and the metal embedded structure, and increasing the ability to control the size of the dielectric II, ΐ ::, the purpose of improving the electrical reliability and reliability of the component can be achieved. : ϊίΓ 月 f To: The preferred embodiment discloses the above, but it is not intended to limit r ^ ^ Er Ren He is eager to learn this skill, without departing from the spirit and scope of the present invention, it can be modified and retouched. Wei Dang is subject to the definition of the scope of the patent application attached. Tuyue Baoshangan 200428528 Brief Description of the Drawings [Simplified Description of Drawings] Figures 1 to 3 are cross-sectional views showing the process of the conventional metal inlaying process. Figure 4 is a top view of a conventional metal mosaic structure. Figures 5 to 10 are cross-sectional views of a metal mosaic process according to a preferred embodiment of the present invention. ] 100: Substrate 1 0 2: Dielectric layer 104: Opening I 0 6: Diffusion barrier layer 108: Metal layer 110: Metal layer II 2: Shallow dish area 11 4: Scratch 1 1 6: Excess area 2 0 0: substrate 2 02: dielectric layer 204: opening 2 0 6: diffusion barrier layer 208: metal layer 2 1 0: protrusion 2 1 2: cathode 214: metal layer 2 1 6: metal layer

Page 14

Claims (1)

200428528 VI. Scope of patent application 1. A metal damascene process at least includes: providing a substrate, wherein at least a dielectric layer has been formed on the substrate, and at least one opening in the dielectric layer is exposed; Part of the substrate;-forming a metal layer to cover the dielectric layer and the exposed substrate, and filling the opening; removing part of the metal layer, thereby flattening the metal layer; and performing a Reverse Electrical Plating step until the metal layer outside the opening is removed. Pass 2. The metal damascene process as described in item 1 of the scope of patent application, wherein the material of the dielectric layer is a low dielectric constant material. 3. The metal inlaying process described in item 1 of the scope of patent application, wherein the material of the metal layer is copper (C u). 4. The metal damascene process according to item 1 of the scope of patent application, wherein before the step of forming the metal layer, it further comprises forming at least a diffusion barrier layer to cover the dielectric layer and the exposed substrate. 4 5. The metal damascene process as described in item 4 of the scope of the patent application, wherein before the step of forming the metal layer, at least a seed layer is formed to cover the diffusion barrier layer. 200428528 6. Scope of patent application 6. The metal inlaying process as described in item 4 of the scope of patent application, wherein after the anti-plating step, it further includes removing at least the diffusion barrier layer outside the opening. 7. The metal inlaying process as described in item 1 of the scope of patent application, wherein the step of forming the metal layer is by using a super-filling method, so that the metal layer has a protrusion above the opening. 8. The metal damascene process described in item 1 of the scope of patent application, wherein the step of forming the metal layer uses an electroplating deposition method. < 9. The metal damascene process described in item 1 of the scope of patent application, wherein the step of removing a portion of the metal layer is by a chemical mechanical polishing (CMP) method. 10. The metal damascene process described in item 1 of the scope of the patent application, wherein the anti-plating step uses the metal layer as an anode. 11. The metal damascene process according to item 1 of the scope of patent application, wherein during the anti-electroplating step, the method further comprises at least: immersing the substrate, the dielectric layer, and the metal layer in an electrolyte; and A detector is used to measure the current of the electrolyte to obtain an anti-plating end point. Page 16 200428528 6. Application for patent 12. A metal inlaying process at least includes: providing a substrate, wherein at least a dielectric layer has been formed on the substrate, and at least one opening is exposed in the dielectric layer Part of the substrate; forming a diffusion barrier layer to cover the dielectric layer and the exposed substrate; _ forming a metal layer to cover the diffusion barrier layer in an overfilling manner, and — filling The opening; removing a portion of the metal layer to planarize the metal layer; and performing an anti-plating step until the metal layer outside the opening is removed. 13. The metal damascene process described in item 12 of the scope of the patent application, wherein the material of the dielectric layer is a low dielectric constant material. 14. The metal inlaying process as described in item 12 of the scope of patent application, wherein the material of the metal layer is copper. 15. The metal damascene process described in item 12 of the scope of patent application, wherein between the step of forming the diffusion barrier layer and the step of forming the metal layer, it further includes at least forming a seed layer to cover the diffusion barrier. Barrier. 16. The metal inlaying process as described in item 15 of the scope of the patent application, wherein the step of forming the seed layer is by a method called S pu 11 ering Deposition. 17. As the scope of the patent application, No. 1 2 The metal inlaying process described in item Page 17 200428528 VI. Scope of patent application After the anti-electroplating step, it includes at least removing the diffusion barrier layer outside the opening. _ 18. The metal inlaying process described in item 12 of the scope of patent application, wherein the step of forming the metal layer further includes at least making the metal layer have a protrusion above the opening. 19. The metal damascene process described in item 12 of the scope of the patent application, wherein the step of forming the metal layer is by an electroplating deposition method. • 20. The metal inlaying process described in item 12 of the scope of the patent application, wherein the step of removing a portion of the metal layer is by a chemical mechanical polishing method. 21. The metal inlaying process as described in item 12 of the scope of the patent application, wherein the step of anti-electron bonding uses the metal layer as an anode. 22. The metal damascene process according to item 12 of the scope of patent application, wherein during the anti-plating step, the method further includes at least: immersing the substrate, the dielectric layer, the diffusion barrier layer, and the metal layer. · In an electrolytic solution; and measuring the electric current of the electrolytic solution with a detector to obtain an anti-plating end point. 23. A metal ballasting process including at least: Page 18 200428528 6. The scope of the patent application provides a substrate 'wherein at least a dielectric layer has been formed on the substrate, and the dielectric layer includes at least an opening exposed portion of the substrate; using an overfill method Forming a metal layer to cover the dielectric layer and the exposed substrate, and filling the opening; performing a grinding step to planarize the metal layer; and performing an anti-plating step until removing the outside of the opening The metal layer. 24. The metal damascene process as described in item 23 of the scope of patent application, wherein the material of the dielectric layer is a low dielectric constant material. 25. The metal inlaying process as described in item 23 of the scope of patent application, wherein the material of the metal layer is copper. 26. The metal damascene process according to item 23 of the scope of patent application, wherein before the step of forming the metal layer, it further comprises at least forming a diffusion barrier layer to cover the dielectric layer and the exposed substrate. 27. The metal damascene process as described in item 26 of the scope of patent application, wherein the step of forming the metal layer further includes at least forming a seed layer to cover the diffusion barrier layer. 28. The metal damascene process according to item 26 of the scope of patent application, wherein after the step of anti-electric bonding, at least further includes removing the diffusion barrier layer outside the opening. Page 19 200428528 6. Scope of patent application 29. The metal inlaying process described in item 23 of the scope of patent application, wherein the forming of the metal layer further includes at least a protruding portion of the metal layer located above the opening. 30. The metal damascene process described in item 23 of the scope of the patent application, wherein the step of forming the metal layer is by an electroplating deposition method. 31. The metal inlaying process as described in item 23 of the patent application scope, wherein the grinding step uses a chemical mechanical grinding method. 3 2. The metal inlaying process as described in item 23 of the scope of patent application, wherein the anti-plating step uses the metal layer as an anode. 33. The metal damascene process as described in item 23 of the scope of patent application, wherein the anti-electroplating step further includes at least: immersing the substrate, the dielectric layer, and the metal layer in an electrolyte; and A detector is used to measure the current of the electrolyte to obtain an anti-electroplating φ end point. 34. A metal ballasting process, at least including: providing a substrate, wherein at least a dielectric layer has been formed on the substrate, and the dielectric layer includes at least an opening exposed portion of the substrate; 200428528 six The scope of the patent application forms a diffusion barrier layer covering the dielectric layer and the exposed substrate; a seed layer is formed to cover the diffusion barrier layer; a metal layer is formed to cover the diffusion barrier layer The seed layer is filled with the opening; a chemical mechanical polishing step is performed to planarize the metal layer; and an anti-plating step is performed until the metal layer and the seed layer outside the opening are removed. 35. The metal damascene process described in item 34 of the scope of the patent application, wherein the material of the dielectric layer is a low dielectric constant material. 36. The metal inlaying process as described in item 34 of the scope of patent application, wherein the material of the metal layer is copper. 37. The metal damascene process described in item 34 of the scope of the patent application, wherein the step of forming the diffusion barrier layer uses a conformal deposition method. 38. The metal damascene process described in item 34 of the scope of patent application, wherein the step of forming the seed layer is by a coin bond deposition method. 39. The metal damascene process described in item 34 of the scope of patent application, wherein after the anti-electroplating step, it further includes at least removing the diffusion barrier layer outside the opening. Page 21 200428528 6. Scope of patent application 40. The metal inlaying process as described in item 34 of the scope of patent application, wherein the forming of the metal layer further includes at least making the metal layer have a protrusion above the opening. 41. The metal damascene process described in item 34 of the scope of the patent application, wherein the step of forming the metal layer uses an electroplating deposition method. 42. The metal damascene process described in item 34 of the patent application scope, wherein the anti-plating step uses the metal layer as an anode. 43. The metal damascene process described in item 34 of the scope of patent application, wherein the anti-electroplating step further includes at least: the substrate, the dielectric layer, the diffusion barrier layer, the seed layer, and The metal layer is immersed in an electrolytic solution; and a detector is used to measure the current of the electrolytic solution to obtain an anti-plating end point. Page 22