TW200428388A - MRAM and methods for reading the MRAM cross-references to related applications - Google Patents

Abstract

An MRAM is provided that minimizes the limits in MRAM density imposed by utilization of an isolation or select device in each memory cell. In addition, methods are provided for reading an MTJ in a ganged memory cell of the MRAM. The method includes determining an electrical value that is at least partially associated with a resistance of a ganged memory cell of the MRAM. The MTJ in the ganged memory cell is toggled and a second electrical value, which is at least partially associated with the resistance of the ganged memory cell, is determined after toggling the MTJ. Once the electrical value prior to the toggling and after the toggling is determined, the difference between the two electrical values is analyzed to determine the value of the MTJ.

Description

200428388 Description of the invention: This is a part of the continuation application under US Patent Application No. 10/33 L058, which was filed on December 27, 2002. [Technical field to which the invention belongs] The present invention relates generally to a magnetoresistive random access memory (MrAM) 'more particularly to a MRAM with magnetic tunneling junctions (MTJs), and to take the item MRAM's M1TJ method. [Prior art] Regarding the use of most of the effects caused by electronic spin, magnetoelectronics, spin electrons, and spintromcs are synonymous terms. The magnetoelectric system is used for several information devices and provides non-volatile, reliable, anti-Kan and high-density data storage and retrieval. Several types of magnetic and electrical information devices, such as 3H, include (but are not limited to) mram. MRAM is roughly composed of a magnetoresistive memory honeycomb, word lines, and bit lines intersecting the word lines. The material memory material nest is typically composed of a magnetically penetrating interface (㈣). In addition, each of the memory honeycombs is typically composed of a 绝缘 -insulation or selection device, which is configured to read the memory honeycomb's magnetic makeup when it is turned into an evil or numerical value. With other memory hive Leong Shao Luo y, —% Kong, ,, Ba margin. For example, each of these memory honeycombs is typically made up of a singularly-bounded solar cell, such as a metal oxide field-effect transistor (MOSFET), and can be removed from the battery. The memory honeycomb in the memory and other memory honeycomb fruits are electro-emulsified. Use insulation such as insulating transistors in female memory cells

6 fate will limit the honeycomb density, and with the increased honeycomb density iMRAM you look for the brother again. Therefore, there is a need

O: \ 90 \ 90423.DOC • 6- 2004283 88 To reduce restrictions on the density of MRAM cells due to insulation in each memory cell or selection device, such as insulating transistors in each memory cell . SUMMARY OF THE INVENTION In view of the foregoing, there is a need to provide an MRAM having one or more memory honeycombs, and the memory honeycombs are not composed of an insulating device such as an insulating transistor. In addition, there is a need to provide _ a kind of fancy presenting a memory hive containing only one MTJ. Furthermore, there is a need to provide a method for reading -MTJ in -MRAM. There is also a need to improve the efficiency of the memory array, a distance measure (me㈣, which measures the size of the area dedicated to the memory), which is used as an analogy to include addressing, reading, being on or off the chip. The overall die or circuit size of the surrounding circuits of other logic circuit interfaces. For example, the charge pump circuit is required to be inversely scaled with the supply voltage due to the scaling of the supply I, and the array efficiency of FLASH memory It has been reduced. Furthermore, other required characteristics and features of the present invention can be made clear from the detailed description and the scope of the accompanying patent applications, which are related to the accompanying drawings and the background. The following detailed description of the present invention is provided for illustration only and is not intended to limit the present invention or the application and use of the present invention. Furthermore, it is not intended to be subject to any representation or meaning theory expressed in the aforementioned technical scope. 'Background or the following detailed description and accompanying accompanying limitations. Referring to FIG. 1, -MRAM 20 is named according to a first exemplary embodiment of the present invention. The MRAM 2G includes At least _ 第 _ 写 人 字 线

O: \ 90 \ 90423.DOC 200428388 (WWL) 22, and in addition to the first, written character line 22, it is preferable to include a written character line (24, 26, 28). The MRAM 20 also includes at least a first memory cell 30, which is adjacent to the first write word line 22, and a second memory cell 32, which is coupled to the first memory cell 30. When used again, proximity should mean close, close, or physical contact to promote magnetic coupling. A first end 88 of the first memory honeycomb 30 is coupled to a transistor 184. One of the first ends of the first memory hive 30 is coupled to a second end 172 of the second memory hive 32, and one of the second ends 174 of the second memory hive 32 is engaged with the third memory. One of the first end of the body honeycomb 76, the second end 1 78 of the third memory honeycomb 34 is coupled to a second end 180 of a fourth memory honeycomb 36, and the fourth memory hive 36 A first end 194 is coupled to a ground 197. Therefore, the memory honeycombs (30, 32, 34, 36) are face-bonded (for example, point-to-point electrical coupling) to form a first ganged § self-memory honeycomb 38, and preferably continuously light. Combined to form the first aggregated meristem honeycomb 38. When used herein, an aggregated memory honeycomb should refer to most memory honeycombs, which are essentially electrically insulated from other memory honeycombs of that memory. In addition to the one or more write word lines (22, 24, 26, 28) and coupling to form one or more memory hives (30, 32,%,%) of the first aggregate memory hive 38 ), The MRAM 20 includes at least a first bit write line 4 (), which is adjacent to the first σ-hidden hidden honeycomb 30 and more preferably to a memory hive of the first aggregated honeycomb hive ( 30, 32, 34, 36). Furthermore, the additional write bit lines (42, 44, 46) are preferably included in the MRAM 20, which are adjacent

O: \ 90 \ 90423.DOC 200428388 At least one of the other memory honeycombs (48, 50, 52). Furthermore, a transistor 184 is coupled to a read bit line 192, and a group read word line (GRWL) 186 is coupled to a control electrode of a group of read insulated transistors 184. Similarly, the group read insulating transistor (173, ι75, Π7) is controlled by the group read word line 186, which is coupled to the clustered memory hive (38, 48, 50, 52). A first end is for reading bit lines (192, 189, 179, 181). When four (4) memory hive (30, 32, 34, 36), four aggregate memory hive (38, 48, 50, 52), four write bit lines (40, 42, 44, 46) and Four write word lines (22, 24, 26, 28), four read bit lines (192, 188, 178, 180) and a single group read word line 186 are described in the first exemplary implementation In the exemplary embodiments and the exemplary embodiments described later, the MRAM 20 will have more than four (4) and less than four (4) memory cells, aggregate memory cells, bit lines and / or word lines, and more than one (1) Group read character lines. At least one memory hive of the first aggregate memory hive 38, such as the second memory hive 32, is composed of an MTJ 54, which is described as a resistor, and at least one memory hive is not It is composed of an insulation device, which at least substantially electrically insulates the memory honeycomb from other memory honeycombs (30, 34, 36) of the first aggregated memory honeycomb 38 (for example, an insulation device such as an insulation Crystal). Preferably, more than one of the memory honeycombs (30, 32, 34, 36) is composed of an MTJ 54 and there is no device for storing the memory honeycomb and other memories of the aggregate memory honeycomb 38. The body honeycomb is electrically insulated, and more preferably, each of the memory honeycombs is composed of an MTJ 54 and there is no device to connect the memory honeycomb to the first O: \ 90 \ 90423 D〇C -9- 200428388 The other memory honeycombs of the memory honeycomb 38 are electrically insulated. Even better, at least one memory honeycomb of the memory honeycombs (30, 32, 34, 36) is composed of -MTJ (that is, the memory honeycomb has only one μτ), no more, no less) And more preferably, each of the memory honeycombs of the first aggregate memory honeycomb 38 is composed of an MTJ 54. Furthermore, the other aggregated memory hives (48, 50, 52) shown in the diagrams and other memory hives of MRAM not shown in the diagrams preferably refer to the first The aggregated amphibian honeycomb 38 is configured as previously described. Therefore, at least N memory honeycombs can be coupled (eg, point-to-point electrical coupling) and electrically insulated from other memory honeycombs (eg, selected) with M insulation, where n & m is an integer and N is greater than M (i.e., N > M), and most memory honeycombs are preferably coupled to be electrically insulated from other aggregate memory honeycombs having an insulating device. Referring to FIG. 2, a simplified side view is provided to a first exemplary MTJ (R), which is placed between a write word line 57 and a write bit line 59. The mtj 55 has two magnetic regions (56, 58), which are ferromagnetically coupled and separated by a tunnel barrier area repair area 60. The magnetic regions (56, 58) may be single or multiple layers of ferromagnetic materials such as nickel (Ni), iron (Fe), cobalt (Co), or alloys or combinations of the above materials (such as nickel iron (NiFe ), Cobalt iron (CoFe), and cobalt nickel iron (NiFeC0)), including manganese (Mn), iridium (Ir), palladium (Pd), or platinum (Pt) among them. The tunneling / barrier region 60 is preferably composed of one or more non-conductive materials, such as, for example, aluminum oxide (AhO3), hafnium oxide (HfO2), boron oxide (b2O3), and oxide ( Ta205), zinc oxide (ZnO2), and other oxides, nitrides, or other appropriate dielectrics. 0 \ 90 \ 90423.DOC -10- 200428388 Although the MTJ 55's example pass 1'Η 糸 is represented by two magnetic zones (56, 58), the MTJ 55 can be a right-hander. Evening in two magnetic regions. The two or more magnetic regions (56, 58) can be rectangular and consist of a magnetized valley easy axis with a length of 66 instead of a width of 68. Iron and Chu ..., and the magnetic field may have other shapes and easy axes formed along other dimensions of the MIT 55. For example, the bribe 55 may have a shape of a circle, an ellipse (elHpteiai), or a shape of a ㈣ (㈣ 0 The MTJ 55 can operate in many modes. For example, the Cain 55 can operate in-antiferromagnetic mode and a spin valve mode. In the antiferromagnetic mode 'in the two magnetic zones (56, 58 The static magnetization state or static orientation between the magnetic moments of) is at least substantially antiparallel or at least substantially parallel. In this spin valve mode, one of the magnetic regions (56, 58) is a nail. Magnetic field, and the other magnetic field is a free magnetic field, which can be switched to connect the free magnetic field with the pinned magnetic field (that is, two The magnetic moment provides a parallel or anti-horizontal orientation. When used herein, a free magnetic zone should refer to a magnetic zone with a composite magnetic moment that rotates freely in the presence of an applied magnetic field, and a Pinned or fixed magnetic domains should mean that a magnetic domain has a composite magnetic moment that typically cannot be rotated in the presence of an applied magnetic field that can rotate the free magnetic domain. Figure 2 and Figure 3. The magnetic zones (56, 58) are separated by the tunnel barrier area 60 to create a tunnel junction, where the relative orientations of the magnetic moments (7 (), 72) (ie The magnetization state) will affect the measurable resistance of the MTJ 55. Therefore, when the orientation between the magnetic moments (70, 72) of the magnetic regions (56, 58) changes, the resistance of the MTJ55 will change, and Different values related to these different orientations (ie different O: \ 90 \ 90423.DOC -11-2004283 88 magnetization state) can be assigned many values. For example, according to an exemplary embodiment of the present invention, the value of the MTJ 55 is Is a binary value (that is, 0 or 1.) One of these binary values is equivalent to the magnetic moment 70, 72) are essentially parallel orientations (ie, a first magnetization state), and the other binary value is equivalent to a substantially anti-parallel orientation between the magnetic moments (70, 72). (Ie, a second state of magnetization). The resistance of the MTJ 55 with a substantially anti-parallel orientation between the magnetic moments (70, 72) provides a first resistance value, and 70, 72) The resistance of mtj 55 in a substantially parallel orientation provides a second resistance value. Therefore, the binary value can be determined by measuring the resistance or electrical properties related to the resistance of MTJ 5 5 (Ie, read the MTJ), it may have thousands of ohms (Ω). However, the mtj55 can be configured to provide a resistance of less than several thousand ohms, or to provide a resistance of more than several thousand ohms. In a specific example, the tunneling barrier region 60 is composed of alumina (Al2O00) and has a thickness 74 of less than about 40 angstroms (40 A). In addition, a magnetic region 56 is composed of cobalt (Co) Composition, which has a thickness 62 of about one thousand angstroms (10 ⑻), and the other magnetic region 58 is composed of nickel iron (NiFe) and has a thickness of about one thousand angstroms (1000 A). The configuration of 耵 55 provides resistance change to resistance (AR / R), which is approximately fifteen percent (15%). However, other materials, combinations of materials, and thicknesses according to the present invention can also be used. Other MTJs according to the present invention can also be used. For example, 'MTJ 76 of a second exemplary embodiment is illustrated in FIG. 4, which is inserted between a write bit line 78 and a write word line 80. The MTJ% is described in U.S. Patent No. 6,545,906, entitled " A Method of

O: \ 90 \ 90423.DOC -12- 200428388

"Writing to a Scalabe Magnetoresistance Random Access Memory Element", published on April 8, 2003, Leomd Savtchenk〇 is the inventor and hereinafter refers to the Savtchenk reference. The Savtchenko reference is hereby incorporated by reference in its entirety The method is incorporated herein. Generally, the MTJ 76 has two magnetic regions (82, 84) and a tunneling barrier region 86 'The tunneling barrier region is inserted between the two magnetic regions (82, 84). In this example, the two magnetic regions (82, 84) are multilayer structures, and the tunneling barrier region 86 is a single-layer structure. The multilayer structure of one magnetic region 82 is a two-layer structure, and the structure has A non-magnetic layer 88 is inserted between two ferromagnetic skins (90, 92), and the other magnetic region 84 is a double layer, which has an anti-ferromagnetic layer 94 and a ferromagnetic layer 96. However, the magnetic regions (82, 84) and the tunneling barrier region 86 may have additional layers to form other multilayer structures instead of the two-layer structure, double-layer structure, and single-layer structure. For example, the magnetic fields Area (82, 84) and / or the tunneling obstacle area% may have one or more credits An antiferromagnetic layer, a ferromagnetic layer, a substrate layer, a seed layer, and / or a template layer. The nonmagnetic layer 88 may be composed of many suitable nonmagnetic materials or antiferromagnetic materials, such as ruthenium (ru), iron ( 〇s), baht (Re), chromium (Cr), rhodium (Rh) or copper (Cu), or a combination thereof, and the antiferromagnetic layer 94 may be composed of many suitable antiferromagnetic materials, such as Manganese alloys (such as iridium manganese (IrMn), iron manganese (FeMn), rhodium manganese (RhMn), platinum manganese (PtMn), and manganese palladium (PtPdMn)). These ferromagnetic layers (90, 92, 94) may be composed of many suitable ferromagnetic materials, such as nickel (Ni), iron (Fe), or cobalt (c0), or a combination thereof (e.g., nickel iron (NiFe), cobalt iron) (FeCo), or cobalt nickel iron (NiFeCo)), and the tunnel barrier region 86 may be made of one or more non-conductive

〇: \% \ 9〇423 D0C -13-200428388. For example, the tunneling obstacle region 86 may be made of aluminum oxide (Al2O3), hafnium oxide (Hf2), oxide (B2O3), oxide button (D04), zinc oxide (ZnO2). ) And other oxides, nitrides or other suitable dielectrics. However, other materials or combinations of materials may be used in these layers in accordance with the present invention. The non-magnetic layer 88 is interposed between the two ferromagnetic layers (90, The formation system between 92) allows the free magnetic region 82 to have a combined magnetic moment 98 that can rotate freely in the presence of an applied magnetic field. In addition, the formation system of the antiferromagnetic layer 94 and the ferromagnetic layer 96 allows the pinning The magnetic region 84 has a composite magnetic moment 100, and the magnetic moment is typically rotated in the presence of an applied magnetic field capable of rotating the free magnetic region of the composite magnetic moment 98. The composition of the pinned magnetic region 84 The magnetic moment 100 is essentially pinned in a predefined direction, which can be many directions according to the present invention, and the combined magnetic moment% of the free magnetic region 82 is the ferromagnetic layer (90, As a result of the magnetic moment (102, 104) of 92), both of them are preferably free to rotate. The free magnetic region 82 The magnetic moments (102, 104) are preferably non-parallel relative to each other, and more preferably at least substantially anti-parallel. In addition, the magnetic moments (102, 104) are preferably The earth system is balanced, which when used herein means that the fractional balance ratio (Mbr) as proposed in equation (1) is in the range of approximately zero (0) to approximately one tenth (1/10) ( (0SMbrS0.1).

Mbr = AM / Mlotal = (I Μ2 Μ Μ! I) / (I Μ! I + I M21) ⑴ At this point, IMJ is the size of a magnetic moment 102, and | m2 | is another magnetic moment 104 Its size. However, other configurations of the MTJ 76 are available using unbalanced magnetic moments. The magnitude of the magnetic moment (102, 104) of the free magnetic region 82 can be selected using a number of techniques well known in the art. For example, these

O: \ 90 \ 90423.DOC -14- 200428388 The thickness (ι06, 108) of the ferromagnetic layer (90, 92) can be adjusted so that the magnitude of the magnetic moment can provide this balance or an imbalance. The magnetic moments (102, 104) are preferably coupled to the non-magnetic layer 88. Although the non-magnetic layer 88 is antiferromagnetically coupled to these magnetic moments (102, 104), it should be understood that other mechanisms can be configured for the antiferromagnetic coupling. For example, the mechanism of antiferromagnetic coupling can be a magnetic static field. The combined magnetic moment 100 of the pinned magnetic region 84 and the combined magnetic moment 98 of the free magnetic region 82 (which is the magnetic moment of the ferromagnetic layer (92, 96) adjacent to the tunneling obstacle region 86) The relative orientation will affect the tunneling resistance of this blade. Therefore, when the combined magnetic moment% of the 4 free magnetic region 82 rotates and the combined magnetic moment 98 of the pinned magnetic region 84 remains unchanged, the mTj% resistance will change and the change resistance values can be assigned Many values. According to an exemplary embodiment of the present invention, the value of the MTJ 76 is a binary value (for example, 0 or 1). One of the binary values corresponds to a substantially flat orientation between the 30% magnetic moment 98 of the free magnetic region 82 and the composite magnetic moment 100 of the pinned magnetic region 84 (that is, a first Magnetization). The other binary value is equivalent to an anti-parallel orientation between the combined magnetic moment 98 of the free magnetic region 82 and the combined magnetic moment 100 of the pinned magnetic region material (ie, a second magnetization state). . The resistance of MTJ 76 with anti-parallel orientation on Bebe provides a first resistance value and the resistance of MTJ 76 with substantially parallel orientation provides a second private resistance value. Therefore, the binary value can be measured by measuring the resistance of the MTJ 76 at a first time (that is, reading the MTJ), and changing the position of the composite magnetic moment 98 of the free magnetic field 82 at a second time 02. Change a carry value stored in the MTJ 76 (ie write to the MTJ), measure the mtj at a second time (h)

O: \ 90 \ 90423.DOC -15-2004283 88 76 (that is, read the MTJ), and at a third time, the resistance of the MTJ 76 measured at the first time (t |) and the Compare the measured resistance of MTJ 76 at the second time i). “As shown in FIG. 5, the combined magnetic moment% of the free magnetic region 82 is preferably positioned in one direction along an anisotropic easy axis 110, which direction is relative to the write bit: line 78 or write character At least one angle (φ ^ φΒ) of line 80 " a. More preferably, the composite magnetic moment 98 is positioned in one direction along an anisotropic easy axis u, which direction is relative to the written word Element line 80 (ie, writing bit line 78 (ie, 0345.) is clamped at about 45 degrees (45 °), and preferably the writing bit line 78 and writing word line 80 are clamped This angle (that is, ω: 45. and ① b = 45). However, other orientations of the composite magnetic moment 98 with respect to the writing bit line π and / or writing word line 80 can be added according to the present invention. Except for the preferred orientation of the synthetic magnetic moment 98 relative to the write bit line 78 and / or the write word line 80, the write bit line 78 is preferably positioned relative to the write Enter the character line 80 with an angle (□) 1} 4. Preferably, the angle (□) II4 is greater than about 60 degrees (60.) and less than about no degrees 0 2 0.). More preferably, the angle (□) 114 is about 90 (90.). The orientation of the writing bit line 78 and the writing word line 80, and where these lines (78, 80) are close to the] MTJ 76 provides a configuration where the two lines (78 , 80) The two magnetic fields (116, 118) emitted will change the magnetic moments (102, 104) of the ferromagnetic layers (90, 92), and thus change the orientation of the composite magnetic moment 98, and then change The binary value stored in the MTJ 76 (that is, written into the MTJ). A magnetic field 11 6 is preferably generated by introducing a current 丨 20 into the write bit line 78 to generate 'and another magnetic field 11 8 is preferably generated by introducing a current 1 22 into O: \ 90 \ 90423.DOC -16- 200428388 in the write word line 80. Therefore, for convenience, the write bit line The magnetic field i 丨 6 generated by the current (Ib) 120 in 78 should be referred to as the magnetic field (HB) 1 and the magnetic field 11 8 generated by the current 122 written in the word line go should be referred to as The character magnetic field (Hw) 11 8. The second study of Figure 6 '^ shows a chart to illustrate the mtj 76 shown in Figures 4 and 5 and the bit magnetic field ιΐ6 and characters shown in Figure 5 Element magnetic field (Hw) 118 Application related write areas (124, 126) and non-switching area 128. These two types of write areas are the direct write area 124 and the trigger write area 126. Related to these non-switch areas 128 The combination of magnetic fields (ιΐ6, 118) will not affect a write, because the combination of magnetic fields related to these non-switching regions does not change the respective positions of the synthetic magnetic moments of the free magnetic zone, XI will be detailed in this one after another Described and explained. However, the combination of the magnetic fields (116, 118) in the direct write region 124 and the trigger write region 126 has the possibility of changing the respective positions of the composite magnetic moments by changing the position of the composite magnetic moments of the free magnetic region. . Without the existing position of the synthetic magnetic moment of the MTJ, the combination of the magnetic field (116, 118) related to the trigger write area 126 (which is referred to as a trigger write or trigger here) will cause these synthetic magnets Moment repositioning. For example, if the combined magnetic fields of the free magnetic zone and the pinned magnetic zone are at least substantially parallel and a triggered write is processed, the combined magnetic moments will be changed to the at least substantial after the triggered write. Up is anti-parallel orientation. Conversely, if the synthetic magnetic moments are at least substantially anti-parallel and a trigger writing system is processed, the synthetic magnetic moments are changed to the at least substantially parallel orientation after the triggered writing. So no matter when the trigger

O: \ 90 \ 90423.DOC -17- 200428388 The binary value stored at the beginning of writing. The trigger write will change the binary value to the other binary value. With respect to the triggered writing, only the required orientation of the synthesized magnetic moment found by the direct writing is different from the existing orientation of the synthesized magnetic moment before the direct writing, and the magnetic field related to the direct writing region 1 24 ( The combination of 丨 丨 6, 1 丨 8) (herein referred to as a direct write) will cause the relocation of these synthetic magnetic moments. For example, assuming that the synthetic magnetic moments are at least substantially parallel, and the direct write system is processed to request a parallel orientation between the synthetic magnetic moments on the Babe, then the synthetic magnetic moments Keep a parallel orientation on the emperor eve. However, provided that the synthetic magnetic moment systems are at least substantially parallel and a direct write system is processed to request an at least substantially anti-parallel orientation between the synthetic magnetic moments, the synthetic magnetic moment systems 疋The position is β-parallel to ^ 'on the shell as an anti-parallel orientation. Conversely, if the synthetic magnetic moment systems are at least substantially antiparallel, and a direct write system is processed to request an at least substantially antiparallel orientation between the synthetic magnetic moments, then The magnetic moments will remain at least substantially anti-parallel, and if the synthetic magnetic moments are at least substantially anti-parallel, the direct write system is processed to request that there be at least one between the synthetic magnetic moments. Substantially parallel to the direction, the synthetic magnetic moments are positioned such that they are at least substantially parallel in orientation. The required orientation in a direct write is roughly determined by the polarity of these magnetic fields (116, 118). For example, assuming a flattened orientation is found between the synthetic magnetic moments, then the two magnetic fields (6, 118) are positive, and assuming that the a-magnet moments are obtained * anti-parallel orientations, then Wait for two magnetic fields (11 $,

O: \ 90 \ 90423.DOC -18- 200428388 11 8) is negative. However, iMTJ% as shown in Figure 4 and Figure 5 can be configured for direct write configurations with other polarities. Referring to FIG. 5, in the exemplary embodiment, the polarities of the magnetic fields (116, 118) that are directly written and triggered to write and the magnitudes of the magnetic fields (116, 118) are introduced and adjusted at the bit line 78 And the word line 80 has a current (120, 122) with a corresponding polarity and magnitude. This is known to those skilled in the art, the introduction of a current into a line will generate a corresponding magnetic field for the line. Therefore, introducing the current 120 into the bit line 78 and the current 122 into the word line 80 will generate the bit magnetic field i 16 and the character magnetic field 118 respectively. Furthermore, a positive current 130 and a negative current 132 (these are arbitrarily defined for the sake of explanation) in the bit line 104 will generate a positive bit magnetic field 134 and a negative bit magnetic field 136, respectively. In addition, a positive current 138 in the word line 80 and a negative current 140 in the word line 80 (these are arbitrarily defined for the sake of illustration) will generate a positive character magnetic field 142 and a negative character magnetic field, respectively. 144. Furthermore, an increase in the magnitude of the current 122 in the word line 80 and an increase in the magnitude of the current 120 in the bit line 78 will result in an increase in the magnitude of the character magnetic field 11 8 and the The magnitude of the bit magnetic field 116 increases. Furthermore, a reduction in the magnitude of the current 122 in the character line 80 and a reduction in the magnitude of the current 12 0 in the δ xuanziyuan line 7 8 will lead to a reduction in the magnitude of the character magnetic field 11 8 and the bit, respectively. The magnitude of the elementary magnetic field u 6 decreases. Referring to FIG. 7, a sequence illustrates that a magnetic field is generated by applying a current to the word line and the bit line to perform a direct write or a trigger write in the MTJ 76 illustrated in FIGS. 4 and 5. . A character magnetic field of 146 having a first character size (| HW1 |) 146 uses a current to be introduced into the character line and O: \ 90 \ 90423.DOC -19- 200428388 is generated at a first time point ( t |) 148, and a bit magnetic field having a first bit size of 150 is generated at a second point in time by introducing a current into the bit line i) 152. After the bit magnetic field with the first character Z small (丨 HB1 |) 150 is generated at the second time point ⑴) 丨 52, the current in the character line will be adjusted to reduce the character magnetic field To a second bit size (| Η ^ |) 154, which is preferably about zero (0), occurs at a third time point ⑹156. -Once the magnetic field of the character is reduced to the size of the second bit (| HW2 |) 1 54 ', the current in the bit line will be adjusted to a fourth time point (U) 160, and the bit The element magnetic field is reduced to the second bit size (丨 ⑸. The character magnetic field is reduced to the second character A / j, (| Hw2 |) i54 to complete the demonstration sequence. When this sequence or many other sequences are completed, Depending on the magnitude of these magnetic fields, the magnetic moments of the two ferromagnetic layers of the free magnetic layer and thus the combined magnetic moments of the free magnetic layer will be rotated to a position other than the existing position prior to the sequence, or maintained Existing relative positions prior to the sequence 'because the small A of these magnetic fields will choose the direct writer or trigger the write, as shown in Figure 6. Figure 8-12 illustrates from the first binary value to An example of trigger writing of the second binary value. Figure 13-17 illustrates an example of trigger writing from the second binary value to the first-binary value. Figure 18_22 illustrates from the first binary value to An example of the direct writing of the second binary value, and FIG. 23_27 illustrates a direct writing of | 巳 {Column, which When the first binary value of 3H is written and the system of Figure 4 has been written, 'the worker is in the position where the first-binary value can be provided. These writing methods are optional' when from the bit line and The two magnetic fields of the current line are required to write MTJ 76 in Figure 4 (see the magnetic fields illustrated in Figure 28_32).

O: \ 90 \ 90423.DOC • 20- 2004283 88 rotations of moments (102, 104) and combined magnetic moments 98 are used for the unit magnetic field sequence shown in Fig. 33 to illustrate the optional characteristics of Fig. 4) . The MTJ 76 of Figures 4 and 5, the MTJ of Figures 2 and 3, and / or any other bribes may be coupled or connected as illustrated and described for the mraMs of the present invention. For example, referring to FIG. 1, the memory honeycombs of the aggregated memory honeycombs (38, M, 50, 52) are connected in series, and more preferably one of the first demonstrations of the MRAM 20 according to the present invention. The examples are connected in series. For example, according to the previous description in the detailed description, the first MTJ terminal 170 of the first-memory hive 30 is connected to the second mtj terminal 172 of the second memory hive 32, the second memory hive The first MTJ terminal i74 of 32 is connected to the first MTJ terminal 1 76 of the second §memory honeycomb 34, and the second MTJ terminal 178 of the second memory hive 340 is connected to the fourth memory The second MTJ terminal 180 of the hive. XI is known to those skilled in the art, the resistance (R of the first aggregate memory honeycomb 38 and other aggregate memory honeycombs (38, 40, 50, 52) with MTJs coupled in series) (R ) Is as follows: R = Rmtji + Rmtj2 +… + Rmtjk (2) where RMT; K is the resistance related to the Kth MTJ in the aggregate memory hive, and K is the aggregate memory The number of MTJs connected in tandem in the body honeycomb. This will be continuously described in more detail. The resistance of an aggregate memory honeycomb can be determined by changing the magnetic state of one of the MTJs in the aggregate memory honeycomb (that is, changing the combined magnetic moment of the free magnetic zone with the The orientation between the combined magnetic moments of the pinned magnetic zone, which generally affects the resistance), and the resistance can be determined by changing the honeycomb in the aggregate memory O: \ 90 \ 90423.DOC -21 > 2004283 88 After the magnetized state of MTJ Beehive. The change in resistance (which is essentially a change in resistance due to the change in the resistance of M D J with the change in the magnetization state) can be determined according to the present invention ', which will be described in more detail later. Referring to FIG. 34, a cross-sectional view is used to illustrate FIG. The cross-section view illustrates the channels and intersecting lines, which are illustrated as T-shaped structures, which are the memory honeycombs (30, 32, 34 '36) of the first aggregate memory honeycomb 38. Coupled to a substrate 182, which is preferably a semiconductor substrate. A group of insulated transistors 184 were developed using standard semiconductor technology as metal oxide semiconductor field-effect transistors (MqsfeTS). However, other transistors can also be used according to the invention. A read word line 186 is formed and configured to operate as a gate terminal of the group read insulated transistor 184. The source 198 of the group read insulating transistor i is connected to the first MTJ terminal 188 of the first memory honeycomb 30, and the group reads the drain 84 of the transistor 910. It is preferably connected to the read bit line 192. In addition, the write bit line 40, that is, the write word line (22 24 26 28) is formed using metallization steps using standard semiconductor technology to locate the write bit adjacent to the write bit line 40. The MTJs 54 of the non-exclusive memory honeycomb of the element line (22, 24, 26, 28) are as previously described in the detailed description of the present invention. The writing word lines (22, 24, 26, 28) and the writing bit line 40 are preferably positioned close to the MTJs 54 to reduce writing to adjacent columns or rows. Character current and magnetic field interact. Consider FIG. 35 and FIG. 36. One of the second exemplary embodiments of the MR AM 2 0 is an aggregated hidden limb honeycomb (38, 48, 50) which is coupled in parallel (preferably connected in parallel) by a maggot or the like. , 52). For example, this

O: \ 90 \ 90423.DOC -22- 2004283 88 The second MTJ terminal 170 of the first memory hive 30 is connected to the second MTJ 172 terminal of the second memory hive 32 and the second memory hive 32 The second MTJ terminal 172 is connected to the second MTJ 178 terminal of the third memory hive 34, and the second MTJ terminal 178 of the third memory hive 34 is connected to the second MTJ of the fourth memory hive 36 180 terminals. In addition, a first MTJ terminal 188 of one of the first memories 30 is connected to a first MTJ terminal 174 of the second memory cell 32, and a first MTJ terminal 174 of one of the second memories 32 is connected to the first MTJ terminal 174. The first MTJ terminal 176 of the three-memory honeycomb 34 and the first MTJ terminal 176 of one of the third memory 34 are connected to the first MTJ terminal 194 of the fourth-memory honeycomb 36. This is understood by those skilled in the art, the resistance of the first aggregate memory honeycomb 38 and other aggregate memory honeycombs (38, 40, 50, 52) with MTJs coupled in parallel ( R) is as follows: 1 / R = l / RMTjl + i / Rmto +… + 1 / Rmtjk (3) RMTjK at 4 places is the resistance related to the Kth 〖h mtj in the aggregate memory hive K is the number of MTJs connected in parallel in the aggregate memory hive. The resistance of the aggregate memory honeycomb can be used to read the state of the MTJ in the 5th memory honeycomb of Lishui City, and other MTJs couplings can be used according to the present invention, including parallel and series combination of MTJs. Considering FIG. 37 and FIG. 38, a third exemplary embodiment of the present invention is an aggregate memory honeycomb (38, 48, 48, 48, 48, 48, 48, 48) 50, 52). Ϊ 列 士 口, dead girl ^ A 3 The memory hive 30 is connected in parallel with the second memory hive 32 to form a first memory hive group, and the third memory hive

O: \ 90 \ 90423.DOC -23- 200428388 34 is connected in parallel with the fourth memory hive 36 to form a second memory hive group 'and the first memory hive group and the second Memory honeycomb groups are connected in series. More specifically, and by way of example only, the second MTJ terminal 170 of the first memory hive 30 is connected to the second MTJ terminal 172 of the second memory hive 32, the first MTJ terminal of the first memory hive 30 The MTJ terminal 188 is connected to the first MTJ terminal 174 of the second memory hive 32, and the second MTJ terminal 78 of the second memory hive 34 is connected to the second MTJ terminal 180 of the fourth memory hive 36. The first MTJ terminal 176 of the third memory hive 34 is connected to a cable MTJ terminal 194 of the fourth memory hive 36, and one of the second MTJ terminals 172 of the second memory hive 32 is connected to the The second memory of the third memory hive 34 has the terminal 178. This is known to those skilled in the art, the first aggregate memory honeycomb 38 and other aggregate memory honeycombs (38, 40, 50) having a series combination of two parallel MTJs coupled in parallel. The resistance (R) of MTjs 54 of 52) is as follows: R = (RmTJ1 * RMTJ2 / RmTJ1 + RMTJ2) + (RMTJ3 * RMTJ4 / RmTJ3 + RMTJ4) + ⑷ ... + (Rmtj (ki) Rmtjk ' Rmtj (ki) + Rmtjk) in. Rmt] k is the resistance related to the MTJ in the aggregate memory honeycomb, and RMT; (K)) is the resistance related to the MTJ in the aggregate memory honeycomb ' The number of MTJs connected in the aggregate memory honeycomb is preferably an even number. As in these other exemplary embodiments, the resistance of the aggregate memory honeycomb can be used to read the state of the memory honeycomb in the aggregate memory honeycomb. Consumption of other MTjs with many MTJs in a clustered memory hive can be used according to the invention

〇 \ 90 \ 90423 DOC -24- 2004283 88 Combined parallel and series combination including MTJs. As described in the detailed description of the present invention, an MTJ exhibits a first resistance when the synthetic magnetic moments are positioned in the -th-azimuth or in a first magnetized state (for example, substantially antiparallel), And when the synthetic magnetic moments use the well technology (which includes the trigger write or the direct write previously described in the detailed description) to locate in a second orientation or in a second magnetized state, such as substantially (Parallel) 'The Jane exhibits a second resistance that is less than one of the first resistances. Therefore, when the synthesis of one of the mtjs of the aggregate memory honeycomb: is positioned in the -th position or is in the _magnetization state (for example, antiparallel in qualitatively), the aggregate memory honeycombs exhibit a first A resistance 'two. When the synthetic magnetic moment of one of the fat 8 of the aggregate memory honeycomb is changed to a second orientation or a second magnetization state (for example, substantially parallel), the aggregate memory honeycombs exhibit a first Two resistors. Therefore, the MTJ in an aggregate memory honeycomb can read the electrical value related to the resistance of the aggregate memory honeycomb before and after changing the orientation of the synthetic magnetic moment of the MTJ, because if the resistance of the MTJ increases , The resistance of the aggregate memory hive will increase, and if the resistance of the MTJ decreases, the resistance of the aggregate memory hive will decrease. Consider FIG. 39, which illustrates a method 200 for reading an MTJ in an MRMA according to an exemplary embodiment of the present invention. Initially, a first electrical value is determined, and the electrical value is related to the equivalent resistance of the aggregated memory cell 202. For example, a voltage is applied across the aggregated memory cell ' and the current associated with the applied voltage can be measured. However, other aspects of the aggregate memory hive are related to the resistance of the aggregate memory hive.

O: \ 90 \ 90423.DOC -25- 200428388 The electrical characteristics can be determined, such as the net time rate of charge (ie, current (Ieq)) transmission through the aggregate memory honeycomb and / or the performance of the aggregate memory honeycomb The actual equivalent resistance at (ie Req = Veq / Ieq). After determining the first electrical value of the aggregate memory honeycomb 202, the method 200 continues with the trigger write or trigger of the MTJ 204. As described in the first two of the detailed description, 'the trigger will cause the relocation of the synthetic magnetic moments', regardless of the existing orientation of the MTJ's synthetic magnetic moments (eg, assuming the free magnetic region and the pinned magnetic region) The composite magnetic moment is at least substantially parallel, and the trigger of the MTJ is processed. After the trigger, the combined magnetic moments will be changed to the at least substantially anti-parallel orientation. Conversely, assuming that Iso synthetic magnetic moments are at least substantially antiparallel, and a trigger write system is processed 'after the delta trigger, the synthetic magnetic moments will be changed to at least qualitatively parallel orientation). Therefore, the trigger changes the binary value to the other binary value, regardless of the binary value stored when the trigger started. After the MΊ7 is triggered, a second electrical value of one of the aggregate memory cells is determined, which is related to the resistance of the aggregate memory cells 206. The second electrical value of the aggregate honeycomb can be determined in a manner to determine the first electrical value, or other techniques can be used to determine the second electrical value. The difference between the 1st% gas value and the 5th second electrical value was confirmed 208 and analyzed 211 to use a number of techniques to complete the reading of the MΊ7, as previously described in the detailed description and its Techniques described later. For example, and referring to FIG. 1, the two-memory honeycomb 32 can be read in the first aggregate memory honeycomb 38 by applying a known current to the first aggregate.

O: \ 90 \ 90423.DOC • 26- 2004283 88 5 The memory honeycomb m is measured across the first-memory honeycomb 38-th-electricity ^, changes the resistance of the second memory hive 32, Know the current applied to the first aggregate memory hive 38 and where? After measuring the resistance of the second memory material nest 32, measure the pressure across the first-memory honeycomb as the first pack, and then compare and analyze the difference between the first voltage and the second voltage to The reading of the second memory hive 32 is completed. For example, if the second voltage is less than the first voltage, the impedance of the first aggregated memory honeycomb 38 decreases as the resistance of the second memory honeycomb 32 changes. Therefore, the resistance of the second memory honeycomb decreases with the change of the resistance of the second memory honeycomb 32, and the original value of the second memory honeycomb 32 is the same as the original value of the aggregated memory honeycomb 38. A value related to the larger resistance value (that is, the second memory honeycomb originally exhibits the larger resistance value). If the second voltage is greater than the first voltage, the equivalent resistance of the first aggregated memory honeycomb% increases with the change in the resistance of the second memory honeycomb 'and the first memory honeycomb 3 8 The original value is a value related to the lower resistance value of the aggregate memory honeycomb 38. However, based on the change in the equivalent resistance, other architectures can be used to confirm the value, and several devices and methods can be used to complete these different architectures and the aforementioned architecture as an example. Referring to FIG. 40, a schematic diagram of a device 300 for reading MTJ in an MRAM is illustrated according to an exemplary embodiment of the present invention. Generally, the device 300 is a sense amplifier 300 including a pre-amplifier, a gain stage 303, and a cross-coupling locker 305. The pre-amplifier 30i (which is a current-voltage converter) includes a P-channel transistor 302, N-channel O: \ 90 \ 90423.DOC -27- 2004283 88 transistor 304, transmission pole 332, and capacitor 336. This gain phase includes, for example, a P-channel transistor (306, 312, 314), an N-channel transistor (308, 31, 316), and a transfer gate 337. The cross-coupling locker 305 includes a p-channel transistor (318, 320, 322: ^ N-channel transistor (324, 326, 328). The device 300 also includes a SCB input, which is set for receiving A signal is a logical complement of a signal sent to an SC input. In addition, an EQB input is configured to receive a signal, which is the logic of an Eq signal delivered to an EQ input. Complementary, and a leb input is configured to receive a LEB signal, which is a L-series mutual signal that is delivered to the L input of the L] g input # Further '-the first voltage output and the second voltage output system It is configured to send out a first output signal (VI) and a second output signal (V2). These are logically complementary. Referring to FIG. 1, FIG. 40 and FIG. 41, a read operation using the device 300 And a trigger write is explained according to an exemplary embodiment of the present invention. The equivalent resistance representing the equivalent resistance of the bearing body σ and the hidden honeycomb is coupled to the 1 ^ channel via a transistor (not shown). Controls the source of transistor 304, which uses the decoded 彳 § number to be gated for reading The value of the aggregate memory honeycomb. For example, the first aggregate memory honeycomb is coupled to the device as shown in θ 1 by activating the insulating transistor 18o and controlling the transistor 304. Continued bit line i 92 is closed to the same gate transistor 304 as shown in Figure 40. The common gate transistor 304 receives a gate: voltage (Vcg), which results in a drain The source / source current (Icg) passes through the common gate electrode body 304. The p-channel transistor 302 source polarizes the pre-amplified current (I.), while the σ-H P-channel transistor 3 0 2 passes through Transmission gate 3 3 2 is connected by a diode

O: \ 90 \ 90423.DOC -28- 200428388, is realized during the initial read cycle, which is shown in the high sc signal in Figure 41. When the drain source (Icg) of the control transistor 4 is equal to the preamplifier current (Ip), the preamplifier 301 develops a steady state bias at a first preamplifier node 334. In the case where the transfer gate 332 is activated, the voltage on a second preamplifier section "', 333 is equal to the voltage on the first preamplifier node ^", so the "previous", magnetized state is stored On the capacitor 336. After storing the "previous" magnetization state, it is caused by the low swing of the% signal. The HT gate 332 is invalid. The value or magnetization state of the memory hive is used as a percentage (assert) The signal is triggered on the write word line (wwl) and the write bit line (WBL) 40, as described in Figure 41 and with reference to the figure}. This will cause the stored value of the memory hive to be Triggered from a certain state to the other state. When the memory honeycomb system is triggered, the resistance of the equivalent resistor 330 is increased or decreased based on the state before the memory hive was initialized. The preamplifier system The development of a different voltage on the first pre-amplifier node 334 reflects the change in the resistance (ie, the increase / decrease of the 4 # effective resistance is a corresponding increase / decrease in the voltage). In the first pre-amplifier, The voltage at point 334 and the stored voltage at the second preamplifier point 3 3 3 are applied to the input of the gain stage 3 03, which respectively correspond to the gates of the P-channel transistor 3 14 and The gates of the other two transistors (306, 312). After the memory hive is triggered, the equalization signals (ie, EQ signals and EQB signals) are de-asserted, causing the transmission gate. The pole 337 becomes non-conductive and starts the gain phase 303. The gain phase 303 is compared in the second preamp section

O: \ 90 \ 90423 DOC -29- 200428388 point 333 of the "previous" state bias and the "after" state bias on the first preamp node M *, and then amplify these to provide the first output signal The bias voltages of (V1) and the second output signal (V2) are as illustrated in Figure 41. After these two output signals (V1 / V2) are developed, the output signals represent the differential (time Fine voltage signals are added. The signal and signal are declared to activate the cross-closing lock 305 to amplify and store the first output L number (V1) and the second output signal (V2). The Gain stage 3 inverts the signal from the pre-amplifier state, so that an increase in voltage at the pre-amplification to point 334 results in a decrease in the second output signal. The gain stage 303 allows the device (ie, the sense The sense amplifier) 300 can sense a relatively small voltage change. In the case where the state of the memory honeycomb or the voltage change between the values is quite large, the use of the gain stage 303 is relatively unrelated. Figure 40 and Figure 42, according to the present invention An exemplary embodiment is used to illustrate the use. The 300 fetch operation and a twist trigger write. The sequence (in which the sensing signals are declared in FIG. 42) is similar to the reference FIG. 41 The described sequence, except that the signals on the write word line and the write bit line are differently declaratively, twisted, the selected memory hive without completing a trigger write First, before changing the state or value, the state or value of the relevant memory hive is read or measured. The "previous" value is stored on the capacitor 336. Then the memory hive will Is moved to the opposite state, which is referred to as a twist as illustrated in FIG. 42. The writing word line and the writing bit lines thereafter are declared to rotate the magnetic field polarization by about 9 °. Degrees (90 °) or less to

O: \ 90 \ 90423.DOC -30- 2004283 88 Change the resistance of the related memory hive. Then, the writing word line and the writing bit line 仏 are kept for a predetermined time to ensure that the first output signal ⑺) and the second output signal (V2) can be sufficiently separated from each other. The torque value locked by the lock 305 is coupled. After the predetermined period of time has elapsed, before the write word line signal is de-declared ', the write bit 7G line is first de-declared to allow the magnetic field polarization to return to the original orientation. Tapping operation allows the resistance value of the memory honeycomb to be determined by determining whether the resistance of the memory honeycomb is increased or decreased by changing the state of the honeycomb without actually changing the state of the honeycomb. The device effectively performs a comparison to provide a differential between the first output signal (V1) and the second output signal ⑽ without changing the state of the memory honeycomb. For example, if the resistance of the memory honeycomb during the twist is A before the twist ", the current state of the honeycomb is a low resistance. If the resistance of the memory honeycomb during the twisting period is lower than that before the twisting, the current state of the honeycomb is a high resistance. Generally, the device 300 uses a current-voltage converter , A sample and hold circuit, and a latch. The circuit may also include a gain / comparator stage: as shown in Figure 40. However, 'as discussed here to perform the type of sense amplifier function The circuit is not limited to the circuit previously described in the figure. For example, the gain stage 303 can be implemented as a differential amplifier or other type of amplifier suitable for providing the required gain. Refer to the figure 43, according to other exemplary embodiments of the present invention, a schematic diagram of a device 500 for reading MTJ in an MRAM is explained. Generally, the O: \ 90 \ 90423.DOC -31-2004283 88 The device 500 (which is a sense amplifier) includes a pre-amplifier 50, a cross-coupling lock 503, a capacitor (508, 524), and a transmission gate (506, 510, 522, 526). The device also includes a SCB Input configured to receive a SCB signal, which is a logical complement of one SC signal received at an SC input. In addition, an SC2B input is configured to receive an SC2B signal, which is an SC2 received at an SC2 input. The signals are logically complementary, and an SCMPB input is configured to receive an SCMPB signal, the SCMPB signal is logically complementary to an SCMP signal received at an SCMP input. Furthermore, an EQB input is configured to receive an EQB Signal, the EQB signal is a logical complement of an EQ signal received at an EQ input, a LEB input is configured to receive a LEB signal, the LEB signal is the logic of an LE signal received at an LE input Complementary, and a first output signal (VI) and a second output signal (V2) are logically complementary. The device 500 is similar to the device 300, as described with reference to FIG. 40, and intended to be used in When reading the MTJ in an MRAM, it is as previously described in the detailed description. However, the device 500 is different from the device 300 of FIG. 40 in which a separate capacitor is used to store the previous After the state or value of the "previous ff magnetization states or can be used to trigger the memory of the honeycomb body or the honeycomb twisting the memory is determined, as previously with reference to FIG 40. The apparatus 300 is described. Generally, reading a memory hive with one of the MRAMs of the device 500 as described includes generating a first voltage of the aggregate memory hive, the aggregate memory hive having an associated memory hive, and storing the voltage at Within a first capacitor 508. The relevant memory hive is then triggered to the other value or state of O: \ 90 \ 90423.DOC -32- 200428388. A second voltage of an aggregated memory honeycomb having an associated memory honeycomb is generated and stored in a second capacitor 524. Then, the voltage generated by the memory cell hive before the trigger operation is compared to the voltage generated by the memory hive after the trigger operation, which is observed by observing how the parent fork light closing latch 503 is stable. Come down. If the "before" voltage is greater than the "after" voltage, the original state or resistance of the memory hive is a zigzag or south resistance value. Conversely, if the voltage 'W' generated by the memory honeycomb is lower than the "after" voltage, the original state or resistance of the memory honeycomb is a low state or a low resistance value. — Referring to FIG. 1, FIG. 43 and FIG. 44, a triggered read operation with the device 500 will be described according to an exemplary embodiment of the present invention. In MRAM ,, trigger, and read period gate Mizuki. The body honeycomb resistance (represented by the equivalent resistance (Req) 53), as shown in Figure 43) is coupled to the source of the N-channel control transistor 5G4 via a transistor (not shown) These unshown transistor systems are polarized between decoded numbers to read the value of the aggregated memory honeycomb. For example, the first aggregate memory honeycomb 38 as shown in FIG. 1 is coupled to the device, which is achieved by activating the insulating transistor and the common gate transistor 504 as shown in FIG. 43. The N-channel common-mode transistor $ ⑽ receives -W-pole bias (veg), resulting in-non-polar / source current (u passes through a total of 7 gate transistors 504. The P-channel transistor 502 is Diodes are connected to provide-preamplifier current (Ip). For example, transfer idler write conduction, the read voltage through the transfer gate 506 is stored on the _ capacitor. After a predetermined period of time to After stabilizing the electric house elsewhere in the first capacitor, the SC signal and SCB signal are de-declarated, allowing the transmission

O: \ 90 \ 90423.DOC -33-2004283 88 gate, 50 ^ b sentences become non-conductive. The value or status of the related memory honeycomb is wrongly triggered by the signal on the write word line 24 and the write bit line cent, as illustrated in Fig. I and Fig. 40. This causes the relevant memory Hive ^ stored value to be triggered from an unknown state or value to another pending state or value. When the memory hive is triggered, the resistance value of the single memory hive ^ will increase or decrease, and as a result, the addition or decrease of the value of the aggregate memory hive pack I1 depends on before triggering the individual memory hive. status. The pre-amplifier 501 responds to the change in resistance by developing a different voltage across the 笮 〃, 534 (that is, increasing / decreasing the resistance will correspondingly increase / decrease > δHai voltage). The new voltage at the first node 534 is then stored in the second capacitor 524 via the transfer gate 526, after which the SC2 signal and SC2B are de-declared. After that, before " and ", the voltages were stored in the capacitors (508, 524), and the equalized signals (that is, the EQ signal and the EQB signal) were de-declarated, thus causing the The transmission gate 527 becomes non-conductive. The SCMP signal and the SCMPB signal are claimed to make the transmission gates (51, 522) conductive, and the voltage stored in the capacitors (508, 534) is provided to the cross-coupling latch. 503. The B signal and the Leb signal are declared so that the cross-coupling locker 503 can store the state or value corresponding to the original state or value of the relevant memory hive. For example, if the "previous" voltage stored in the first capacitor 508 is greater than the "after" voltage stored in the first turtle valley 524, the first output of the cross-fit latch ^ VI) and the second output signal (V2) will indicate that the original state or value of the 5 hidden body honeycomb is greater than the trigger state or value. As previously described in the detailed description, the original state or value can make O: \ 90 \ 90423.DOC -34- 200428388

A "twist" operation is used to determine, and the device 500 can also use the "twist" operation to determine the original state or value. Referring to FIG. 45, an illustrative embodiment is provided for Twist the magnetic polarization of the memory honeycomb (ie, change the magnetization state) and use the device 500 to sense the result to read the ribs in an MRAM. The sequence illustrated in FIG. 45 is similar to that previously described in FIG. : 4 except that the write word line and the write bit line signal are applied in a parental manner to twist the relevant memory hive, instead of triggering the state of the memory hive. Initially Before the magnetization state of the memory hive in the aggregate memory hive is changed, the electrical value of the memory hive is read or measured. The "previous" value is stored in the Dibaogu 508. The memory The honeycomb is then rotated toward the other magnetized state, and the "hive of the aggregated memory hive" is twisted, and the equivalent value is stored in the first capacitor 524. The write word line signal is claimed, which follows the claim of the write bit line to partially change the magnetization state of the memory honeycomb.

State (such as rotating the magnetic polarization from the original orientation to about 90 degrees (90 °)). This partial change will change the resistance of the aggregate memory honeycomb, and the related memory honeycomb is part of the aggregate memory honeycomb, and the resistance difference can be used to determine the original state, as previously described in the detailed description description. The write word line and write bit line signals then remain unchanged for a predetermined period of time to ensure that the first output signal (V1) and the second output signal (V2) can be sufficiently separated to be separated by the The twist value locked by the cross coupling locker 503. After the predetermined period of time has elapsed, the writing bit line number is de-declared before the a-line writing sub-line number is de-declared, so that the magnetic polarization can return to the original orientation. The device 500 effectively performs O: \ 90 \ 90423 DOC -35- 2004283 88 A comparison to provide a result 'The result is obtained between the-output signal (VI) and the output signal (V2) Between the differential form. If the resistance value of the twisting blade is greater than the "before" resistance value, the magnetization of the memory honeycomb ^ or the value is-a low value. If so, the twisting resistance value is less than the "before" resistance Value ', the current magnetization state or value of the memory hive is a high value, and there are other combinations of written word line signals and bit word line signals that may be invented to twist the memory hive. For example, The mouth of the memory honeycomb is turned suspiciously, so a change in the resistance of the aggregate memory honeycomb can be obtained by declaring only one of the write lines. The write bit line W may = claim And the writing word line signal is kept low. Similarly, it is assumed that the triggering and twisting currents are unidirectional. In other embodiments, the triggering and twisting currents may be bidirectional. ', Although at least-the exemplary embodiment has been shown in detail in the foregoing description of the present invention: in the second, but it should be understood that there are still a lot of changes. It should also be understood that this exemplary embodiment or entrapment-/, sacrifice embodiment is only an example, and is not intended to limit the scope of the present invention 'applicability, or configuration in any way. Rather, the foregoing detailed description provides convenient instructions for those skilled in the art to practice the present invention-an exemplary embodiment. It should be understood that various changes can be implemented in the functions and arrangements of the elements described in the example shown in # 加 山 frustration yoke, without departing from the scope of the present invention. Lei Yue put forward within the scope of the patent application for this phase. [Schematic description] This month will be described after linking the following diagrams, where the phase

O: \ 90 \ 90423.DOC -36- 2004283 88 The same numerals indicate the same elements, and FIG. 1 is a schematic diagram of a MRAM according to one of the present inventions. FIG. 2 is a simplified side view of the MRAM according to one embodiment of the present invention; FIG. 3 is an exploded view of the MTJ shown in FIG. 2; and FIG. 4 is a view according to the present invention. A simplified side view of the mtj of a second exemplary embodiment; FIG. 5 is a simplified plan view of the MRJ of FIG. 4; and FIG. In the graph, these combinations generate direct write, trigger write, and no switching in mtj in FIG. 4; FIG. 7 is a timing diagram of the magnetic field used for direct write or trigger write in __ in FIG. 4 Figure 8-12 illustrates the movement of these magnetic moments during a triggered write, which results in a change from a first binary value to a second binary value; Figure 1 3-17 The movement of the magnetic moment causes it to change from the second binary value to the first binary value; Figure 1-8-22 The movement of these magnetic moments during direct writing, which results in a first-binary The value becomes a second binary value; Figures 23-27 illustrate the movement of these magnetic moments during the direct write with the first binary value of the bribe of Figure 4 'which is already in place when the direct write begins The orientation of the first binary value; Figure 28-32 illustrates the movement of the magnetic moment in Figure 33;

O: \ 90 \ 90423.DOC -37- 2004283 88 Figure 33 is a timing diagram of applying a single magnetic field to the MTJ of Figure 4. Figure 34 is a cross-sectional view of Figure iiMRAM, which is an exemplary implementation according to the present invention Examples are formed on a substrate; FIG. 35 is a schematic diagram of a mrma according to a second exemplary embodiment of the present invention; FIG. 36 is a cross-sectional view of FIG. 35iMRAM, which is formed according to an exemplary embodiment of the present invention. On a substrate; FIG. 37 is a schematic diagram of a mrma according to a third exemplary embodiment of the present invention; FIG. 38 is a cross-sectional view of FIG. 37 iMRAM, which is formed on a substrate according to an exemplary embodiment of the present invention Fig. 39 is a flowchart of a method for reading MTJ in MRAM according to an exemplary embodiment of the present invention; Fig. 40 is a ―first embodiment of the present invention w, _ for reading A schematic diagram of a memory honeycomb (eg, a sense amplifier) device; Figure 41 is a timing diagram using the device of Figure 40 for triggering reading; Figure 42 is a device using Figure 4G for swinging Read timing diagram; Figure 43 is another exemplary implementation according to the present invention , One for reading. Fig. 44 is a schematic diagram of a device that uses a honeycomb (such as a sense amplifier); Fig. 44 is a timing diagram using the device of Fig. 43 for triggering reading; and Fig. 45 is a diagram using the device of Fig. 43 for Timing chart for wobble read. [Illustration of Symbols in the Drawings] 20 Magnetoresistive Random Access Memory 22 Writing Character Lines

O \ 90 \ 90423.DOC -38- 200428388 24 Write character line 26 Write character line 28 Write character line 30 Memory Hive 32 Memory Hive 34 Memory Hive 36 Memory Hive 38 Gather Memory Hive 40 write line 42 write line 44 write line 46 write line 48 aggregate memory hive 50 aggregate memory hive 52 aggregate memory hive 54 magnetic tunnel junction 55 magnetic tunnel junction 56 magnetic area 57 write character Line 58 Magnetic area 59 Line 60 Tunnel barrier area 62 Thickness 64 Thickness O: \ 90 \ 90423.DOC -39 200428388 66 Length 68 Width 74 Thickness 76 Magnetic tunneling interface 78 Line 80 Write word line 82 Free magnetic area 84 magnetic region 86 tunneling obstacle region 88 non-magnetic layer 94 anti-ferromagnetic layer 96 ferromagnetic layer 98 composite magnetic moment 100 composite magnetic moment 10 2 magnetic moment 104 magnetic moment 110 anisotropic axis 116 magnetic field 118 magnetic field 120 electric field 122 electric field 124 Direct write area 126 Trigger write area 128 No switching area O: \ 90 \ 90423.DOC -40- 200428388 130 Positive current 132 Negative current 134 Magnetic field 136 Magnetic field 138 Positive current 140 Negative current 142 Positive character magnetic field 144 Negative character magnetic field 170 Magnetic tunneling junction terminal 172 Magnetic tunneling junction terminal 173 Group insulated transistor 174 Magnetic tunneling junction terminal 175 Group insulated transistor 176 Magnetic tunneling junction Surface termination 177 Group insulated transistor 178 Magnetic tunneling junction terminal 179 Read bit line 180 Magnetic tunneling junction terminal 181 Read bit line 184 Group insulated transistor 186 Word line 188 Magnetic tunnel junction Terminal 189 5 Beam bit line 192 Shibei Bit line O: \ 90 \ 90423 DOC -41-200428388 194 Magnetic tunneling junction terminal 198 Source 200 Method 202 Memory honeycomb 204 Magnetic tunneling junction 206 Memory honeycomb 300 Sense amplifier 301 Pre-amplifier 302 P-channel transistor 303 Gain stage 304 N-channel control transistor 305 Locker 330 Equivalent resistance 332 Transmission gate 333 Pre-amplifier node 334 Pre-amplifier node 336 Capacitance 337 Transmission gate 500 Device 501 Pre- Amplifier 502 P-channel transistor 5 03 Locker 504 N-channel common gate transistor 506 Transistor gate O: \ 90 \ 90423.DOC -42 200428388 508 Capacitance 524 Capacitance 526 Transmission gate 527 Transmission gate 534 Node

O: \ 90 \ 90423 DOC

Claims (1)

200428388 Scope of patent application: L A method for reading MTJ in an aggregate memory cell hive of MRAM, including the following steps: determining a first electrical value, the electrical value being at least partially related to the aggregate memory cell hive The resistance is related to the triggering of the MTJ in the aggregate memory cell of the MRAM; determining a second electrical value, which is at least partly related to the resistance of the aggregate memory cell after the MTJ is triggered; analyzing the first The difference between the electrical value and the second electrical value. — 2 · The method for reading the MTJ in the aggregate memory honeycomb of the MRAM according to item 1 of the patent application scope; wherein the decision is at least partly related to the second electrical value system related to the resistance of the aggregate memory honeycomb A second voltage across one of the aggregated memory honeycombs is measured after the triggering in the aggregated memory honeycomb of the MRAM. 3. A MRAM comprising: a first memory honeycomb having a first magnetic tunneling junction (MTJ) and a second memory honeycomb having-a second MTJ and at least partially forming a An aggregated memory hive with the first-memory hive, where the first-memory hive and the second memory hive are configured so that the reading system of the first MTJ contains ... It was determined that the electrical value was at least partly related to the resistance of the production memory honeycomb; κ triggered the first MTJ of the first memory honeycomb, · O: \ 90 \ 90423.DOC 4. A second electrical value Decided that the electrical value is at least partly related to the resistance of the aggregated memory honeycomb after triggering the first MTJ; 5. An analysis of the difference between the first electrical value and the second electrical value. For example, if the MRAM of the third patent area is applied for, the reading of the first MTJ still includes a known current application to the aggregate memory hive of the MRAM. A magnetoresistive random access memory (MRAM) includes: a first bit line; a sigma cryptic honeycomb, which is adjacent to the first bit line and is formed by a first magnetic tunneling interface ( MTJ); a second memory honeycomb at least partially forms a first aggregated memory honeycomb with the first memory honeycomb, and is composed of a second MTJ connected in series with the first honeycomb; And the first word 7L line, which is adjacent to the first memory hive and the second memory hive. A type of magnetoresistive random access memory (MRAM), comprising: a first bit line;-a first-memory honeycomb, which is adjacent to a first word line, the younger-memory honeycomb has a first A plurality of memory honeycombs, including the order ^ Shizkokong_LA · »Hidden Interface (MTJ) 'Excludes an insulation device, and other memory honeycombs connected in series to this a 5th memory hive; and —Number—Ili 70 Line 'At least one of the plurality of chrome U basket honeycombs adjacent to the first aggregate memory honeycomb. For example, the 6-item MRAM of Shenyang Patent Fanyuan Shigudi, in which the first plurality of memory honeycombs are prepared-each is connected in series with the first aggregate memory O: \ 90 \ 90423.DOC -2 -200428388 of the hive /, his 5th memory hive is connected, and parallel connection with other memory hive of the first aggregate memory hive is excluded. 8. A magnetoresistive random access memory (MRAM), comprising: a first word line; a first-memory group, which is adjacent to the first word line, the first memory group contains _ Section-Memory Hive, "Matching with a Section-C Memory Hive in Parallel" and the Section-Memory Hive and the Second Memory Hive are connected by a magnetic tunnel junction (MTJ) composition; A second memory group is coupled in series with the first memory group to form a first aggregated memory hive. The second group includes a third memory hive, which is in parallel. And a first memory hive, and the third memory hive and the fourth write-off hive are composed of the MTJ, and a first bit line is adjacent to the first memory A hive, the first memory hive, the third memory hive, and the fourth memory hive; one. y · If the patent includes:-the fifth memory hive, which is connected in series with the first-= bee: coupled in parallel with the second memory hive-a sixth memory hive A series connection with the second nest and a parallel connection with the first memory honeycomb, a magnetic resistance random access memory (MRAM), which contains ·, O: \ 90 \ 90423.DOC 200428388 a first word line; a first memory group, which is adjacent to the first word line, the first memory group includes a first memory hive, which is connected in series with A second memory honeycomb is coupled, and the first memory honeycomb and the second memory honeycomb are composed of a magnetic tunnel junction (MTJ); a second memory group is parallel to The first memory group is coupled to form a first aggregated memory hive, and the second memory group includes a third memory hive which is coupled in series with a fourth memory hive. The third memory hive and the fourth memory hive are composed of the MTJ. And a first bit line which is adjacent to one of the first memory hive, the second memory hive, the third memory hive and the fourth memory hive ° O: \ 90 \ 90423.DOC- 4-