200428207 〇75 82twf.doc/006 玖、發明說明 發明所屬之技術領域 本發明是有關於非揮發性、可重寫之記憶體，且特別 是有關於用來更新（refresh)非揮發性、可重寫記憶體陣列之 系統與方法。 先前技術 典型之快閃（flash)記憶體陣列中，記憶胞係安排於 由列與行所形成之長方形陣列中，並於列與行所形成之交 叉點配置記憶胞電晶體。每一電晶體之汲極連接到對應之 位元線，源極經由陣列源極線連接至陣列源極電壓，而閘 極則連接至字組線(wordline)。 典型的快閃記憶體容許以整塊（bulk)、記憶區（sector) 或記憶頁（page)方式來程式化（program)、讀取或抹除，此 外，有些快閃記憶體可以操作於EEPROM模式，也就是從 使用者的觀點來看，記憶胞可以位元組爲單位地程式化、 讀取或抹除。習知記憶胞之程式化方法係將所選擇連接記 憶胞電晶體汲極之位元線驅動於第一電壓，且將連接所選 擇字組線之記憶胞電晶體的閘極驅動於較高之第二電壓， 以執行注入熱電子。 快閃記憶胞資料的抹除方法則將快閃記憶胞電晶體 的閘極驅動於遠較位元線上之電壓爲小之電壓來執行，如 此做時，電子將穿遂離開記憶胞電晶體之浮置閘極，以此 爲例，則抹除操作可以是抹除整個快閃記憶陣列之整塊抹 除、抹除一快閃記憶陣列記憶區之記憶區抹除、或抹除單 一記憶區列之記憶頁抹除來執行。如果快閃記憶體可以操 200428207 07582twf.doc/006 作於EEPROM模式，那從使用者的觀點來看，也可以位元 組爲單位來執行抹除。 然而，快閃記憶體於抹除和程式化操作期間卻受 干擾現象，因爲記憶胞在記憶區可能共用相同之位元線’ 位元線上之電壓會產生共用位元線記憶區之電場效應。此 外，不同記憶區中之記憶胞也可能共用字組線，而這些共 用字組線上的電壓會在共用之記憶區中造成場效應。 共用位元線和字組線上產生之電場可能會有偶然地 抹除已程式化之位元或程式化已抹除位元之結果，例如升 高字組線之電壓來程式化抹除之位元可能會將相同字組線 上先前程式化的位元之浮置閘上的一些電子移至控制閘 上’而干擾了先前程式化之位元。因此，在每一次抹除或 程式化操作之後、或在預設次數的抹除或程式化週期之 後，記憶區記憶胞便需要更新。 一種更新操作之習知技術爲在每一次抹除/程式化操 作之後執行整個記憶區之更新，其中需將要更新之記憶區 的內容緩衝起來再重寫入。然而，用來儲存記憶區內容之 緩衝區會使用大量的區域，以致必須限制記憶區規模來降 低緩衝1區大小。另一種決定何時執行更新操作之習知技術 爲使用δ十數器g十算抹除或程式化週期之數目，並於預設週 期數之後執行更新。但此種計數器經常並不可靠，因此這 些習知之更新技術無法提供有效且可靠之更新程序。 發明內容 本發明是針對例如是可以操作於EEpR〇M模式之快閃 g己憶體的非揮發性記憶體之更新方法與系統，特別地，本 200428207 〇7582twf.doc/006 發明之一實施例將更新程序內含於寫入操作中，在每—次 程式化/抹除週期之後，更新操作以所選擇位元線相關之位 元組記憶胞開始執行，並循序地處理。在一實施例中，合 量測記憶胞電流，如果記憶胞電流符合第-標準，就更新 記憶胞。 特別地，分配預設時間以執行更新程序，包括實際H 新與確認程序兩者，使用本發明之一實施例，如果與字組 線相關之記憶胞能維持多於N個週期而不需要更新，那就可 以在每一次抹除或程式化操作之後，循序地更新1/N個記憶 區，這與習知在每一次抹除或程式化操作之後，更新整個 記憶區之技術大不相同。有益地，本發明減少了更新緩衝 區所需之大小，且可將記憶區規模放大N倍而無須使用更新 週期計數器。 特別地，寫入或重寫入操作包括3個內含操作:抹除操 作、程式化操作與更新操作，在更新操作期間，經由在閘 極提供一高偏壓及汲極提供一升高偏壓，以使用通道熱電 子注入法（CHE)對快閃記億胞浮置閘注入電荷。在一實施例 中，當記憶胞電流落入預設範圍時，就更新記憶胞，因此， 更新操作係對那些記憶胞電流落入預設範圍之記憶胞而執 行，而非執行更新操作時’更新記憶區之每一記憶胞。 爲讓本發明之上述和其他目的、特徵、和優點能更明 顯易懂，下文特以較佳實施例，並配合所附圖式，作詳細 說明如下： 竇施方式： 所有圖式中，類似之參考號碼係用以參考相同或功能 200428207 07582twf.doc/006 類似之項目。 爲了槪述本發明之目的，此處描述了本發明之某些特 徵、優點與新特性’然應瞭解根據本發明之特定實施例並 無須達成所有之優點。因此，可以達成或最佳化此處所述 之一優點或一群優點之方式來具體化或實施本發明，而無 須達成如此處所述或所建議之其他優點。 本發明之較佳實施例是有關於更新可重寫之非揮發 性固態記憶體之方法與系統。特別地，更新操作內含於寫 入或重寫入操作中，如下述之更詳細描述，於實施例中， 在重寫入一位元組之後，便由重寫入操作期間所選擇之位 元線開始，於預設時間範圍內執行更新操作。 有益地，更新操作係於指定記憶胞之記憶胞電流落入 預定範圍時執行，而非更新操作執行時，更新記憶區中之 每一記憶胞。例如，也許只有百分之一記憶胞的記憶胞電 流會落入預定範圍，因此，更新程序較許多習知方法更快 且使用較少之緩衝空間，更新程序選擇性地內含於包括抹 除與程式化操作之寫入或重寫入操作中，在每一次程式化/ 抹除週期之後，更新操作以所選擇位元線相關之位元組記 憶胞開始執行，並循序地處理。 須知下述之電路、電壓、電流之類的只是爲了說明方 便，因此本發明可以使用其他電路、電壓及/或電流來具體 化或實現。 第1圖係顯示根據本發明較佳實施例之非揮發性記憶 電路100部分範例方塊圖。有益地，此記憶電路架構於 EEPROM與快閃記憶模式下操作，在EEPROM模式時，資料 200428207 07582twf.doc/006 可以一次一位元組的寫入，而在快閃模式時，資料可以一 次一記憶區或一記憶頁的寫入。此記憶電路100包括記憶胞 耦接行解碼器134與字組線解碼器130之複數個記憶區 102、104、106 ' 108、110、112，記憶區102、104、106共 用來自行解碼器134之共同位元線120,而記憶區108、110、 112共用來自行解碼器134之共同位元線122，記憶區102與 108共用來自字組線解碼器130之共同字組線124，記憶區 104與110共用來自字組線解碼器130之共同字組線126，記 憶區106與112共用來自字組線解碼器130之共同字組線 128。更一般地，每一字組線代表Μ列之一，其中每一Μ列 有Ν個字組，位元線之數目等於一列中Ν字組的數目乘以每 一字組中之位元數。 抹除/程式化/讀取電路114耦接行解碼器134與字組線 解碼器130，更新電路118耦接抹除/程式化/讀取電路114、 行解碼器134與字組線解碼器130。如下之詳細描述，更新 電路U8是用來適時地更新記憶胞以保護干擾情況改變了 資料，干擾情況可能是因爲記憶胞在記憶區共用相同之位 元線而產生，以致位元線上之電壓會在共用位元線之記憶 區產生電場效應，干擾情況也可能是因爲不同記憶區中之 記憶胞有可能共用字組線，而這些共用字組線上的電壓會 在共用字組線之記憶區中造成場效應。因此，抹除一記憶 區可能偶然地導致其他記憶區之位元値改變，以致需執行 更新操作來防止値偶然地改變。 第2圖係顯示快閃記憶電路記憶區例如是第1圖之記 憶區102的範例部分200線路圖，此範例記憶區包括每一位 9 200428207 07582twf.doc/006 元線32個記憶胞而有32條字組線（WL)’其有256位元組連接 相同字組線驅動器，每一記憶胞耦接一字組線與一位元 線，每一記憶胞配置於字組線與位元線之交叉點，記憶胞 之汲極連接到位元線’記憶胞之源極經由陣列源極線連接 至陣列源極電壓，而記憶胞之閘極則連接至字組線。例如’ 記憶胞202具有一控制閘耦接至字組線WL0、汲極耦接位元 線204，而源極連接陣列源極線（S)，在範例實施例中，特定 記憶區中之記憶胞的源極共同連接至陣列源極線（S)，第1 圖中之感測放大器132讀取選擇之位兀。 第3圖係顯示當非揮發性固態記憶體1 〇 〇操作於位元 組可抹除模式使用之重寫入程序300範例’首先以狀態302 爲啓始，抹除第一^記憶區中之一*定址位兀組’繼I買至狀悲 304，然後以希望之資料來程式化定址位元組’繼續至狀態 306，從選擇之位元線開始執行更新操作，然後至下一位元 線循序處理直到接受更新程序之整個記憶區爲止，選擇性 地，可以分配例如是lms或2ms之固定時間，以執行狀態306 之更新程序，狀態306執行之更新程序詳細說明於第4圖 中，如下所述。 請參考第4圖，其詳細說明範例更新程序306，如下所 述，自動更新操作決定是否記憶胞具有一特性，例如是電 流達到臨界値或設定之範圍値，而如果是便執行更新記憶 胞。因此，更新操作是當記憶胞電流落入預設範圍內時執 行，而不是更新記憶區之每個記憶胞。程序306由狀態402 開始並繼續至狀態404，其將記憶胞閘極設定至程式化確認 電壓準位(program verify voltage level)(Vg)並讀取記憶胞， 200428207 〇7582twf. doc/006 例如可以將Vg設定爲7伏特。 在狀態406，量測記憶胞電流Icell以決定Icdl是否大於 預設臨界値II，例如可以是20//A，如果Icdl的値小於或等 於II，那便不執行更新而程序306繼續至狀態412 ’如果Icell 的値大於II，那程序306繼續至狀態408，在狀態408 ’量測 記憶胞電流Icell以決定Icell是否小於預設臨界値12 ’例如可 以是40// A，如果Icell的値大於或等於12，那便不執行更新 而程序306繼續至狀態412,如果Icell的値小於12,那程序306 繼續至狀態410，在狀態410執行更新操作。 在狀態412，決定是否已經評估最後記憶區位元組’ 以決定是否要更新，如果是最後位元組，程序306結束於狀 態414，否則程序306繼續至狀態413，其中之記憶胞評估程 序繼續至與循序之下一位元線相關之下一位元組’然後回 至狀態404之迴圈，以重複程序。因爲並非所有指定記憶區 中的記憶胞都在相同之更新週期更新，分配給更新操作之 時間乃大幅縮短，例如在某些陣列實施例’於指定時間只 有約1%的記憶胞需要更新。 第5圖係顯示於高準位之更新順序5〇〇’由選擇之位元 線BL0開始，更新操作對於符合電流標準與程式化/抹除程 序期間選擇之位元線相關之記憶胞來執行’然後更新與隨 後之付合電流標準之記憶區位兀線相關的日2丨思胞。 例如本發明使用之實施例，如果記憶陣列胞於需要更 新前，在-6.5V之Vg具有100次的忍受度，且如果如第2圖中 之說明般地陣列之每一位元線具有32個記憶胞，那要更斩 之位元組將包括所選擇位元線與隨後之位元線相關之記憶 200428207 075 82twf.doc/006 胞。如果每位元組之一般安定時間爲5 V s，每位元組之更 新時間即爲1.5// s，那麼兩字組線連接至一字組線驅動器， 且128個位元組共用相同字組線時，需分配之更新時間低於 lms。 程式化 抹除 說明 VD 5V 浮置 VD在程式化時會干擾記憶胞狀態從高 的Vt至低的Vt VG 11V -7V VG在抹除時會干擾記憶胞狀態從高的 Vt至低的Vt，VG在程式化時影響很小 VS 0V 6V VS在抹除時會干擾記憶胞狀態從高的 Vt至低的Vt VB 0V 0V 沒有影響 表一 上面之表一包括範例EEPROM操作情形與對應記憶胞 之影響，有興趣且有意義之部分爲記憶胞狀態由高的Vt至 低的Vt的範圍，在程式化電壓設定爲5V而抹除端點浮置之 情況，VD(汲極電壓）在程式化時會干擾記憶胞狀態從高的 Vt至低的vt，在程式化電壓設定爲11V而抹除端點設定爲-7v之情況，VG(閘極電壓)在抹除時會干擾記憶胞狀態從局 的vt至低的Vt，在程式化電壓設定爲0V而抹除端點設定爲 6V之情況，VS(源極電壓）在抹除時會干擾記憶胞狀態從高 ^jVt至低的Vt，而在程式化電壓設定爲0V而抹除端點設定 爲0V之情況，則沒有影響。 第6圖係顯示在第4B圖中說明之更新決定程序期間， 12 200428207 075 82twf.doc/006 特別是狀態406與408時定義記憶胞電流之範例快閃記憶胞 I-V曲線圖，此例之讀取電壓爲7V，記憶胞電流Icell之低限 II爲20 // A，記憶胞電流Icell之高限12爲40 // A，如果 Il<lcell<12,則更新記憶胞，如果IcellS II，則不執行更新， 同樣地，如果Icell-12，則亦不執行更新。 下面之表二描述範例記憶陣列操作模式。 操作 記憶陣列操作模 式 流程 1 程式化整個記憶 區 程式化整個記憶區（不需要更新操 作） 2 重寫入一位元組 (EEPROM功能） 陣列記憶胞位元組抹除—以位元組 方式程式化陣列記憶胞—固定時間 更新 3 只抹除記憶區（以 快閃功能抹除） 抹除整個記憶區（不需要更新操作） 4 記憶區抹除和程 式化整個記憶區 (快閃操作—3 + 1) 抹除整個記憶區^程式化整個記憶 區（不需要更新操作） 表二 當在快閃模式程式化整個記憶區時，不需要更新操 作，在EEPROM位元組模式，當位元組要重寫入時，首先 抹除對應之位元組，然後程式化位元組，再執行如第4圖說 明之更新操作。 當操作於快閃模式時，抹除整個記憶區以選擇性地執 13 200428207 07582twf.doc/006 行記憶區抹除。當操作於快閃模式時，經由先執行記憶區 抹除操作，然後再執行記憶區程式化操作，來執行記憶區 抹除與記憶區程式化操作，不需要執行更新操作。 因此如上述，本發明之實施例提供更新非揮發性記憶 體之可靠而有效的方法，特別地，更新程序內含於寫入操 作中，且評估記憶胞，以決定記憶胞是否需要更新。 雖然本發明已以較佳實施例揭露如上，然其並非用以 限定本發明，任何熟習此技藝者，在不脫離本發明之精神 和範圍內，當可作各種之更動與潤飾，因此本發明之保護 範圍當視後附之申請專利範圍所界定者爲準。 圖式簡單說明= 第1圖係顯示根據本發明較佳實施例之快閃記憶電路 範例方塊圖； 第2圖係顯示快閃記憶電路範例部分線路圖； 第3圖係顯示更新快閃記憶電路之一範例方法流程 圖； 第4圖係顯示第3圖中更新快閃記憶電路的範例方法 之更詳細流程圖； 第5圖係顯示循序位元線更新方法之範例實施例；以 及 第6圖係顯示範例I-V曲線圖示。 圖式標示說明= 1〇〇非揮發性記憶電路 102、104、106、108、110、112 記憶區 114抹除/程式化/讀取 200428207 075 82twf.doc/006 118更新 120、122共同位元線 124、126、128共同字組線 130字組線解碼器 132感測放大器 134行解碼器 2 0 0範例部分線路 202記憶胞 204位元線 300〜414方法步驟 500於高準位之更新順序200428207 〇75 82twf.doc / 006 (ii) Description of the invention The technical field to which the invention belongs The present invention relates to non-volatile, rewritable memory, and more particularly to refreshing non-volatile, re-writable System and method for writing memory array. Prior art In a typical flash memory array, memory cell lines are arranged in a rectangular array formed by columns and rows, and memory cell crystals are arranged at the intersections formed by the columns and rows. The drain of each transistor is connected to the corresponding bit line, the source is connected to the array source voltage via the array source line, and the gate is connected to the wordline. Typical flash memory allows programming, reading, or erasing in bulk, sector, or page mode. In addition, some flash memories can be operated in EEPROM. Mode, that is, from the user's point of view, memory cells can be programmed, read, or erased in units of bytes. The conventional programming method of a memory cell is to drive a bit line selected to connect the drain of a memory cell transistor to a first voltage, and drive a gate of the memory cell connected to the selected block line to a higher voltage. A second voltage to perform the injection of hot electrons. The method of erasing the data of the flash memory cell is performed by driving the gate of the flash memory cell transistor to a voltage far lower than the bit line. When this is done, the electrons will pass through the memory cell transistor. Floating gate, taking this as an example, the erasing operation can be to erase the entire flash memory array, erase a memory area of a flash memory array area, or erase a single memory area Erase the memory pages to execute. If the flash memory can be operated in EEPROM mode by 200428207 07582twf.doc / 006, then from the user's point of view, the erase can also be performed in units of bytes. However, the flash memory is disturbed during erasing and stylization operations, because the memory cells in the memory area may share the same bit line ’and the voltage on the bit line will cause the electric field effect of the shared bit line memory area. In addition, memory cells in different memory areas may also share word lines, and the voltages on these shared word lines may cause field effects in the shared memory areas. The electric field generated on the shared bit line and the block line may accidentally erase the programmed bits or the result of the programmed erased bits, such as increasing the voltage of the word line to program the erased bits. The element may move some of the electrons on the floating gate of the previously programmed bit on the same block line to the control gate 'and interfere with the previously programmed bit. Therefore, after each erase or stylization operation, or after a preset number of erase or stylization cycles, the memory cells need to be updated. A known technique of update operation is to perform an update of the entire memory area after each erase / program operation, in which the contents of the memory area to be updated need to be buffered and rewritten. However, the buffer used to store the contents of the memory area uses a large number of areas, so that the size of the memory area must be limited to reduce the size of the buffer area. Another conventional technique for deciding when to perform the update operation is to count the number of erasing or stylizing cycles using a delta counter g and to perform the update after a preset number of cycles. However, such counters are often unreliable, so these known update technologies cannot provide an effective and reliable update procedure. SUMMARY OF THE INVENTION The present invention is directed to a method and system for updating non-volatile memory, such as a flash memory that can operate in EEPROM mode, in particular, one embodiment of the present invention 200428207 07582twf.doc / 006 The update procedure is included in the write operation. After each programming / erasing cycle, the update operation starts with the byte memory cells related to the selected bit line and is processed sequentially. In one embodiment, the memory cell current is measured, and if the memory cell current meets the first criterion, the memory cell is updated. In particular, a preset time is allocated to perform the update procedure, including both the actual H new and the confirmation procedure. Using one embodiment of the present invention, if the memory cell associated with the block line can maintain more than N cycles without updating , Then you can sequentially update 1 / N memory areas after each erase or program operation, which is very different from the conventional technique of updating the entire memory area after each erase or program operation. Beneficially, the present invention reduces the size required to update the buffer area, and can increase the size of the memory area by N times without using an update cycle counter. In particular, the write or rewrite operation includes three embedded operations: an erase operation, a stylized operation, and an update operation. During the update operation, a high bias is provided at the gate and a rising bias is provided at the drain. To inject charge into the flash memory cell floating gate using channel hot electron injection (CHE). In one embodiment, the memory cells are updated when the current of the memory cells falls within the preset range. Therefore, the update operation is performed on those memory cells whose current falls within the preset range, rather than when the update operation is performed. Update each memory cell in the memory area. In order to make the above and other objects, features, and advantages of the present invention more comprehensible, a detailed description is given below with preferred embodiments in conjunction with the accompanying drawings as follows: Sinus application: In all drawings, similar The reference number is used to refer to the same or similar item of 200428207 07582twf.doc / 006. For the purpose of describing the invention, certain features, advantages, and new features of the invention are described herein. It should be understood, however, that not all advantages need to be achieved in accordance with particular embodiments of the invention. Thus, the present invention may be embodied or implemented in a manner that achieves or optimizes one of the advantages or a group of advantages without the need to achieve other advantages as described or suggested herein. The preferred embodiment of the present invention relates to a method and system for updating a rewritable non-volatile solid-state memory. In particular, the update operation is included in the write or rewrite operation, as described in more detail below. In the embodiment, after rewriting a byte, the bit selected during the rewrite operation is The meta line starts and performs an update operation within a preset time range. Advantageously, the update operation is performed when the memory cell current of the specified memory cell falls within a predetermined range, instead of updating each memory cell in the memory area when the non-update operation is performed. For example, the memory cell current of only one hundredth of the memory cells may fall into a predetermined range. Therefore, the update procedure is faster and uses less buffer space than many conventional methods. The update procedure is selectively included in the erase process. In a write or rewrite operation with a program operation, after each program / erase cycle, the update operation starts with the byte memory cells associated with the selected bit line and is processed sequentially. It should be noted that the following circuits, voltages, currents and the like are only for the convenience of explanation, so the present invention can be embodied or implemented by using other circuits, voltages and / or currents. FIG. 1 is a block diagram showing an example of a part of a nonvolatile memory circuit 100 according to a preferred embodiment of the present invention. Beneficially, the memory circuit architecture operates in EEPROM and flash memory modes. In EEPROM mode, data 200428207 07582twf.doc / 006 can be written one byte at a time, and in flash mode, data can be written one at a time. Writing to a memory area or a memory page. The memory circuit 100 includes a plurality of memory areas 102, 104, 106 ′ 108, 110, 112 coupled to a row decoder 134 and a block line decoder 130, and the memory areas 102, 104, 106 share the row decoder 134. Common bit line 120, and memory areas 108, 110, 112 share common bit line 122 from row decoder 134, memory areas 102 and 108 share common word line 124 from block line decoder 130, memory area 104 and 110 share a common block line 126 from the block line decoder 130, and memory regions 106 and 112 share a common block line 128 from the block line decoder 130. More generally, each block line represents one of M columns, where each M column has N blocks, and the number of bit lines is equal to the number of N blocks in a column multiplied by the number of bits in each block . The erase / program / read circuit 114 is coupled to the row decoder 134 and the block line decoder 130, and the update circuit 118 is coupled to the erase / program / read circuit 114, the row decoder 134 and the block line decoder 130. As described in detail below, the update circuit U8 is used to update the memory cell in time to protect the interference situation and change the data. The interference situation may be caused by the memory cell sharing the same bit line in the memory area, so that the voltage on the bit line will be The electric field effect is generated in the memory area of the shared bit line, and the interference may also be because memory cells in different memory areas may share the block line, and the voltage on these shared block lines will be in the memory area of the shared block line. Cause field effects. Therefore, erasing a memory area may accidentally cause the bits of other memory areas to change, so that an update operation needs to be performed to prevent accidental changes. Figure 2 shows the flash memory circuit memory area. For example, the memory area 102 of Figure 1 is an example 200 circuit diagram. This example memory area includes 9 200428207 07582twf.doc / 006 32 lines of memory cells. 32 word lines (WL) 'which have 256 bytes connected to the same word line driver, each memory cell is coupled to a word line and a bit line, and each memory cell is arranged on the word line and bit At the intersection of the lines, the drain of the memory cell is connected to the bit line. The source of the memory cell is connected to the array source voltage via the array source line, and the gate of the memory cell is connected to the block line. For example, the memory cell 202 has a control gate coupled to the word line WL0, a drain coupled to the bit line 204, and a source connected to the array source line (S). In the exemplary embodiment, the memory in a specific memory area The source of the cell is connected in common to the array source line (S), and the sense amplifier 132 in FIG. 1 reads the selected position. Figure 3 shows an example of a rewrite procedure 300 used when the non-volatile solid-state memory 100 is operated in a byte erasable mode. 'First starts with state 302, and erases the first memory area. A * Addressing bit group 'follows I buy to state 304, and then uses the desired data to program the addressing bit' to continue to state 306, starting from the selected bit line and performing the update operation, and then to the next bit Line sequential processing until the entire memory area of the update program is accepted. Optionally, a fixed time such as lms or 2ms can be allocated to execute the update program of status 306. The update program performed by status 306 is described in detail in Figure 4. As described below. Please refer to FIG. 4 for a detailed description of the example update program 306. As described below, the automatic update operation determines whether the memory cell has a characteristic, for example, the current reaches a threshold (or a set range), and if so, the update of the memory cell is performed. Therefore, the update operation is performed when the memory cell current falls within a preset range, instead of updating each memory cell in the memory area. Program 306 starts from state 402 and continues to state 404. It sets the memory cell gate to the program verify voltage level (Vg) and reads the memory cell. 200428207 〇7582twf. Doc / 006 For example, it can Set Vg to 7 volts. In state 406, the memory cell current Icell is measured to determine whether Icdl is greater than a preset threshold 値 II. For example, it may be 20 // A. If cIcdl is less than or equal to II, then the update is not performed and the program 306 continues to state 412. 'If the Icell's 値 is greater than II, then the program 306 continues to state 408, where the 408' measures the memory cell current Icell to determine whether the Icell is less than a preset threshold 値 12 ', for example, it can be 40 // A, if the Icell's 値 is greater than Or equal to 12, then the update is not performed and the program 306 continues to state 412. If the value of Icell is less than 12, the program 306 continues to state 410 and performs the update operation in state 410. At state 412, it is determined whether the last memory region byte has been evaluated to determine whether to update. If it is the last byte, the process 306 ends at state 414, otherwise the process 306 continues to state 413, where the memory cell evaluation process continues to The next byte associated with the next lower line is then returned to the loop of state 404 to repeat the process. Because not all the memory cells in the specified memory area are updated in the same update cycle, the time allocated for the update operation is greatly reduced. For example, in some array embodiments, only about 1% of the memory cells need to be updated at a specified time. Figure 5 shows the update sequence 500 ′ at the high level starting from the selected bit line BL0. The update operation is performed on the memory cells related to the current standard and the bit line selected during the programming / erasing process. 'Then update the day 2 associated with the memory area line of the subsequent current standard. For example, in the embodiment used in the present invention, if the memory array cell needs to endure 100 times at a Vg of -6.5V before it needs to be updated, and if each bit line of the array has 32 as shown in Fig. 2 For a memory cell, the more significant byte group will include the memory of the selected bit line and the subsequent bit line 200428207 075 82twf.doc / 006 cell. If the general settling time of each byte is 5 V s, and the update time of each byte is 1.5 // s, then the two-byte line is connected to the one-byte line driver, and 128 bytes share the same word When the line is assembled, the update time to be allocated is lower than lms. Stylized erase means that VD 5V floating VD will interfere with the state of the memory cell from high Vt to low Vt during programming. VG 11V -7V VG will interfere with the state of the memory cell from high Vt to low Vt during erasure. VG has little effect when programming VS 0V 6V VS will interfere with the state of the memory cell when erasing. From high Vt to low Vt 0B 0V 0V does not affect Table 1. Table 1 above includes example EEPROM operation situations and corresponding memory cells. The impact, the interesting and meaningful part is the range of the memory cell state from high Vt to low Vt. When the programmed voltage is set to 5V and the terminal floating is erased, VD (drain voltage) is It will interfere with the state of the memory cell from high Vt to low vt. When the stylized voltage is set to 11V and the erase end point is set to -7v, VG (gate voltage) will interfere with the state of the memory cell during erasure. Vt to low Vt, when the stylized voltage is set to 0V and the erase terminal is set to 6V, VS (source voltage) will interfere with the memory cell state from high ^ jVt to low Vt when erased, and In the case where the programmed voltage is set to 0V and the erase terminal is set to 0V, there is no effect. Figure 6 shows an example of the flash memory cell IV curve during the update decision procedure described in Figure 4B, 12 200428207 075 82twf.doc / 006, especially the state of the memory cell current defined in states 406 and 408. This example reads Take the voltage as 7V, the lower limit of the memory cell current Icell II is 20 // A, the upper limit of the memory cell current Icell 12 is 40 // A, if Il < lcell < 12, then update the memory cell, if IcellS II, then No update is performed, and similarly, if Icell-12, no update is performed. Table 2 below describes exemplary memory array operation modes. Operating memory array operation mode flow 1 Program the entire memory area Program the entire memory area (no update operation required) 2 Rewrite a byte (EEPROM function) Array memory cell byte erase—program in byte mode Array memory cells-update at fixed time 3 Erase memory area only (Erase with flash function) Erase entire memory area (no update operation required) 4 Erase and program entire memory area (Flash operation—3 + 1) Erase the entire memory area ^ Program the entire memory area (no update operation required) Table 2 When the entire memory area is programmed in flash mode, no update operation is required. In EEPROM byte mode, when the byte is To rewrite, first erase the corresponding byte, then program the byte, and then perform the update operation as shown in Figure 4. When operating in the flash mode, the entire memory area is erased to selectively perform a memory area erase. 13 200428207 07582twf.doc / 006 When operating in flash mode, memory area erase and memory area program operations are performed by performing memory area erase operation first, and then memory area program operation, without performing update operation. Therefore, as mentioned above, the embodiments of the present invention provide a reliable and effective method for updating non-volatile memory. In particular, the update program is included in the write operation and the memory cells are evaluated to determine whether the memory cells need to be updated. Although the present invention has been disclosed as above with preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make various modifications and retouches without departing from the spirit and scope of the present invention. Therefore, the present invention The scope of protection shall be determined by the scope of the attached patent application. Brief description of the drawings = Fig. 1 is a block diagram showing an example of a flash memory circuit according to a preferred embodiment of the present invention; Fig. 2 is a partial circuit diagram showing an example of a flash memory circuit; Fig. 3 is a diagram showing an updated flash memory circuit An example method flowchart; FIG. 4 shows a more detailed flowchart of an example method of updating a flash memory circuit in FIG. 3; FIG. 5 shows an example embodiment of a sequential bit line update method; and FIG. 6 Shows an example IV curve diagram. Graphical description = 100 nonvolatile memory circuits 102, 104, 106, 108, 110, 112 memory area 114 erase / program / read 200428207 075 82twf.doc / 006 118 update 120, 122 common bits Line 124, 126, 128 common block line 130 block line decoder 132 sense amplifier 134 row decoder 2 0 0 example partial line 202 memory cell 204 bit line 300 ~ 414 method step 500 update order at high level