TW200426937A - Method and system for etching a high-k dielectric material - Google Patents
Method and system for etching a high-k dielectric material Download PDFInfo
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- TW200426937A TW200426937A TW93112020A TW93112020A TW200426937A TW 200426937 A TW200426937 A TW 200426937A TW 93112020 A TW93112020 A TW 93112020A TW 93112020 A TW93112020 A TW 93112020A TW 200426937 A TW200426937 A TW 200426937A
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一、【發明所屬 本發明係關 熱基板之方法。 之技術領域】 於加熱基板之方法 尤有關於利用電漿加 二、【先前技術】 在半導體產業中,微電子裝 接近深次微米範圍,以期滿足五3最丄=寸正逐漸 理器及數位電路之需東。因户In對杈快、較低功率微處 上,高介電常數材料(此處亦;為1「二金f :導體技術 取代Si〇2及氮氧化矽(SiN〇 ) 'g ,」材料)快速 代摻雜以之故,製程發展與整極材料取 疊材料及石夕化物處理之主要挑戰:之4遞係對於新閉極堆 介電材料中具介電常數大於 =高介電常數材料;另外,高介電常數材料可特::積常 丨电材枓可能併入金屬功聊七 ^匕物(如Ta2〇5 (k〜26)、Ti〇2 (k〜8〇 屬夕膠或I. [Invention belongs to the present invention relates to a method for heating a substrate. [Technical field] The method of heating the substrate is particularly related to the use of plasma plus two. [Previous technology] In the semiconductor industry, microelectronics is close to the deep sub-micron range, in order to meet the five-three-three-inch gradual processing device and digital East of the circuit. Because of the low-power, low-power, high-dielectric-constant materials (here also; 1 "two gold f: conductor technology replaces Si〇2 and silicon oxynitride (SiN〇) 'g," materials ) For the sake of rapid generation of doping, the main challenges of process development and anodic material stacking materials and petrochemical processing: the 4th system is for the new closed-electrode reactor dielectric materials with a dielectric constant greater than = high dielectric constant In addition, high dielectric constant materials can be special :: Ji Chang 丨 electric materials may be incorporated into metal work (such as Ta205 (k ~ 26), Ti〇2 (k ~ 80) Glue or
Al2〇3 (k〜9)、HfSi〇、Hf〇2 (k〜25) ) )。 2二)、 之製造期間,吾人須姓刻並移除該高介電常體裝置 進行該源Α極區域之♦化,以及降低金屬心二^ 入期間進入該源/汲極區域之風險。 貝%離子植 【發明内容】 本發明係關於加熱基板之方法 尤有關於利用電漿加Al2O3 (k ~ 9), HfSi0, Hf02 (k ~ 25))). 22) During the manufacturing process, we must carve and remove the high-dielectric constant body device to carry out the source A electrode region and reduce the risk of entering the source / drain region during the metal core's entry. [Abstract] The present invention relates to a method for heating a substrate, and more particularly
第6頁 200426937 五、發明說明(2) 熱基板之方法。 兹說明在一電漿處理系統中用於加熱在基板支座上之 基板之方法,該方法包含··導入一惰性氣體至該電漿處理 系統’該惰性氣體包含He、Ar、Xe、及Kr至少其中之一, 自該處理氣體點燃電漿;以及將該基板暴露於該電漿中達 一段足以令該基板溫度提升至2〇() t以上之時間。 兹說明在一電漿處理系統中用於加熱在基板支座上之 基,另一方法’該方法包含:在第一溫度下蝕刻該基板上 之第一層’加熱在基板支座上之基板以令該基板溫度自該 第 /jnL度&升至第二溫度,其中該加熱包括導入一惰性氣 體至該電聚處理系統,該惰性氣體包含He、、Xe、及]^ ^少其中之一,自該處理氣體點燃電漿;以及將該基板暴 露於該電漿中達一段足以令該基板溫度提升至該第二溫度 以上之時間;以及在該第二溫度下蝕刻該基板上之第二 層0 四 【實施方式】 在材料處理方法中,廣泛用於閘極堆疊之高介電常數 介電層已需要較複雜製程以蝕刻此類材料。其中,傳統之 閘極堆疊乾電漿蝕刻係利用對該基板支座之設定溫度 ',在 包含多重製程步驟之製程策略中,此設定溫度在所有步驟 均維持固定。通常,因該基板支座溫度係由一熱交換器設 定,且該熱交換器本身具有大熱慣性,故不宜在製程步驟 間改變該熱交換器溫度。Page 6 200426937 V. Description of the invention (2) Method of thermal substrate. Described below is a method for heating a substrate on a substrate support in a plasma processing system. The method includes introducing an inert gas to the plasma processing system. The inert gas includes He, Ar, Xe, and Kr. At least one of them, igniting a plasma from the processing gas; and exposing the substrate to the plasma for a period of time sufficient to raise the temperature of the substrate to above 20 ° C. Described below is a method for heating a substrate on a substrate support in a plasma processing system. Another method 'the method includes: etching a first layer on the substrate at a first temperature' and heating the substrate on the substrate support. In order to raise the temperature of the substrate from the / jnL degree & to a second temperature, the heating includes introducing an inert gas to the electropolymerization processing system, the inert gas including He, Xe, and ^^^ First, igniting a plasma from the processing gas; and exposing the substrate to the plasma for a period of time sufficient to raise the temperature of the substrate above the second temperature; and etching the first substrate on the substrate at the second temperature. Two-layer 0-four [Embodiment] In the material processing method, the high-k dielectric layer, which is widely used for gate stacking, has required a more complicated process to etch such materials. Among them, the traditional gate stack dry plasma etching uses a set temperature of the substrate support. In a process strategy that includes multiple process steps, this set temperature is maintained constant at all steps. Generally, since the substrate support temperature is set by a heat exchanger, and the heat exchanger itself has a large thermal inertia, it is not appropriate to change the temperature of the heat exchanger between process steps.
第7頁 200426937 五、發明說明(3) --一" ^ 然而’對先進閘極堆疊蝕刻而言,日益需要在一製程 策略中之不同製程步驟間具有不同基板溫度。例如··在包 含摻雜。一聚/TaN/Hf〇2/Si堆疊中,該摻雜—聚及TaN層 可於8 0 C下钱刻’ 8 0 °c為該基板支座之設定點溫度。但, 首先’在Si上Hf〇2之選擇性蝕刻可能需要遠高於丨5〇乞的溫 度,·其次,導入具有令該Hf〇2閘介電層可進行乾電漿蝕刻 而無須攻擊下方暴露之源/汲以之足夠大參數空間的電漿 化學極為重要。 根據一實施例之電漿處理系統示於圖i,豆包括一電漿 、與該電漿處理室_合之—對話系㈣、以及 與該對話系統12及該電漿處理室1〇耦合之—控制器14,該 :制器14係用以執行一包含一或更多製程步驟之製程策 ::::上述般:刻一閘極堆疊;此外 可用以 ,收來自該對話系統12之至少一端點訊號,並對該至少一 螭,訊號作前處理以期準確地決定該製程之端點。在所列 施例中,示於1之電漿處理系Μ利用電‘材料 處理,電漿處理系統1可包含一餘刻室。 根據圖2所示之該實施例,雷难_ 處理室1〇、基板支座20,其上附電/待處處理理糸統^可包含電聚 真空抽氣系統30。基板25之例可為—车之土板25以及 或-液晶顯示器;例如可配置電^严 體基板、一曰曰圓 25表面附近之處理區域15產生電^處;至10以便於在基板 統(未顯示)將-可離子化氣體;氣口;-氣體注入系 該製程壓☆,例如吾人可利用合4勿導入並調整 L制機構(未顯示)以節Page 7 200426937 V. Description of the invention (3)-a " ^ However, for advanced gate stack etching, it is increasingly necessary to have different substrate temperatures between different process steps in a process strategy. For example ... Doping is included. In a poly / TaN / Hf〇2 / Si stack, the doped-poly and TaN layer can be engraved at 80 ° C. '80 ° c is the set point temperature of the substrate support. However, firstly, the selective etching of Hf〇2 on Si may require a temperature much higher than 50 ° C. Secondly, the introduction of a Hf〇2 gate dielectric layer allows dry plasma etching without attacking the underlying Plasma chemistry of the source of exposure / sufficiently large parameter space is extremely important. A plasma processing system according to an embodiment is shown in FIG. I. The bean includes a plasma, coupled with the plasma processing chamber_hezhi—the dialogue system, and coupled with the dialogue system 12 and the plasma processing chamber 10. -Controller 14, the controller 14 is used to execute a process strategy including one or more process steps :::: as above: engraved with a gate stack; in addition, it can be used to receive at least from the dialogue system 12 An endpoint signal, and pre-processing the at least one signal in order to accurately determine the endpoint of the process. In the listed embodiments, the plasma processing system M shown in 1 utilizes electro-'material processing. The plasma processing system 1 may include an additional chamber. According to the embodiment shown in FIG. 2, the lightning treatment chamber 10 and the substrate support 20 with the electric / standby processing system attached thereto may include an electric vacuum pumping system 30. An example of the substrate 25 may be-a soil plate 25 of a car and / or a liquid crystal display; for example, an electric body substrate, a processing area 15 near the surface of the circle 25 may be configured to generate electricity; to 10 to facilitate the (Not shown) will be-ionizable gas; gas port;-gas injection is the pressure of the process ☆, for example, we can use He 4 to not introduce and adjust the L system (not shown) to save
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氣閥抑制該真空抽氣系統3 〇 ;電漿可用於生產特別用於預 定材料處理之材料,並/或幫助材枓由基板25之暴露表面 移除。該電漿處理系統la可用以處理2〇〇 mm、3〇〇㈣或更 大之基板。 例如基板25可透過一靜電夾持系統26而附於該基板支 座20上;再者,例如該基板支座2〇可更包括一含再循環冷 卻劑流之冷卻系統,該再循環冷卻劑流係接收來自於基板 支座20的熱並將熱傳送至一熱交換器系統(未顯示),或 當加熱時將熱自該熱交換器系統送出;此外,一傳熱氣體 可經由一为側氣體分佈系統2 7而送至基板2 5背侧,以提升 基板25與基板支座20間之氣體間隙熱傳導係數。當吾人欲 對該基板溫度進行調升或調降控制時及可利用此一系統。 例如·遠负侧氣體分散系統2 7可包含一個兩區或三區(或 :般的多重區)氣體分佈系統,其中該背侧氣體(間隙) 壓力可獨立地於基板25之中央與邊緣間變化。在其餘實施 例中’加熱/冷卻元件如抗加熱元件、或電熱加熱器/冷 卻器可包含於該基板支座20及該電漿處理室1〇之室壁及任 何其他該電漿處理系統1 a内之組件中。 在圖2所示之該實施例中,基板支座可包含一電極,RF 功率即透過該電極而與製程空間i 5中之該處理電漿耦合, 例如基板支座20可藉RF產生器40發射出RF功率經由一阻抗 匹配網路50至該基板支座20而電偏量於一電壓,該偏 量可作為熱電子以形成並維持住電漿。在此配置中,該系 統可作為一反應離子蝕刻(r IE )反應器,其中該室及一上An air valve inhibits the vacuum pumping system 30; a plasma can be used to produce a material specifically for a predetermined material processing and / or to help remove the material from the exposed surface of the substrate 25. The plasma processing system 1a can be used to process substrates of 200 mm, 300 mm or larger. For example, the substrate 25 may be attached to the substrate support 20 through an electrostatic clamping system 26; further, the substrate support 20 may further include a cooling system containing a recirculated coolant flow, the recirculated coolant The flow system receives heat from the substrate support 20 and transfers the heat to a heat exchanger system (not shown), or sends heat out of the heat exchanger system when heating; in addition, a heat transfer gas can be passed through a The side gas distribution system 27 is sent to the back side of the substrate 25 to raise the thermal conductivity of the gas gap between the substrate 25 and the substrate support 20. This system can be used when we want to increase or decrease the temperature of the substrate. For example, the far-negative-side gas dispersion system 27 may include a two- or three-zone (or: general multi-zone) gas distribution system, in which the back-side gas (gap) pressure may be independently between the center and the edge of the substrate 25 Variety. In the remaining embodiments, 'heating / cooling elements such as anti-heating elements, or electric heaters / coolers may be included in the substrate support 20 and the walls of the plasma processing chamber 10 and any other plasma processing system 1 a within the components. In the embodiment shown in FIG. 2, the substrate support may include an electrode, and RF power is coupled to the processing plasma in the process space i 5 through the electrode. For example, the substrate support 20 may be RF generator 40. The emitted RF power passes through an impedance matching network 50 to the substrate support 20 and is electrically biased to a voltage. The bias can be used as a hot electron to form and maintain a plasma. In this configuration, the system can be used as a reactive ion etching (r IE) reactor, where the chamber and a
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端氣體注入電極係作為接地面 圍分佈於〇·1 MHz至1〇〇 MHz, 為習於此技術者所熟知。 ,用於RF偏量之典型頻率範 而用於電漿處理之RF系統應 另一種方式,在多重頻率下將RF功率施加於該基板支 座電極;、再者,阻抗匹配網路5〇可降低功率反射以加速⑽ 功率傳送至電漿處理室10中之電漿。匹配網路技術(如[ 型、P型、T型等)及自動控制方法應為習於此技術者所熟The terminal gas injection electrode system is distributed as a ground plane around 0.1 MHz to 100 MHz, which is well known to those skilled in the art. The RF system used for the typical frequency range of RF bias and for plasma processing should be another way to apply RF power to the substrate support electrodes at multiple frequencies; further, the impedance matching network 50 may The power reflection is reduced to accelerate the transmission of the power to the plasma in the plasma processing chamber 10. Matching network technologies (such as [, P, T, etc.) and automatic control methods should be familiar to those skilled in this technology
例如真空抽氣系統3 〇可包含一可提供高達每秒5 〇 〇 〇公 升(或更南)抽氣速率之加速分子真空泵(TMp )以及一抑 制a亥至壓之閘閥,在用於乾電漿蝕刻之傳統電漿處理裝置 中,通常使用每秒1 00 0至30 00公升之TMP,例如典型上小於 50 mT〇rr之低處理即可用“1> ;對於高壓處理(亦即大於、 100 一 mT〇rr)可採用機械加壓泵。此外,用於監測室壓(未 顯不)之裝置可與電漿處理室i 〇耦合,例如該壓力量測裝 置可為MKS儀器公司(位於美國麻州And〇ver )所生產之 Bairatron 628B型絕對電容壓力計。For example, the vacuum pumping system 30 can include an accelerated molecular vacuum pump (TMp) that can provide a pumping rate of up to 5000 liters (or south) per second, and a gate valve that suppresses the pressure to the sea. In conventional plasma processing equipment for plasma etching, TMP of 1000 to 300,000 liters per second is usually used, for example, a low processing typically less than 50 mT0rr can be used "1>; for high-pressure processing (that is, greater than, 100 One mT0rr) can use a mechanical booster pump. In addition, a device for monitoring the room pressure (not shown) can be coupled to the plasma processing chamber i 0. For example, the pressure measurement device can be MKS Instruments Corporation (located in the United States) Bairatron Model 628B Absolute Capacitance Pressure Gauge manufactured by Andover, Mass.
、控制器14包含一微處理器、記憶體、以及一可產生足 以聯繫並啟動電漿處理系統丨a之輸入與監測自電漿處理系 統la輸出的控制電壓之數位1/〇崞;此外,控制器14可與rf 產生,、阻抗匹配網路50、氣體注入系統(未顯示)、真 ==軋系統30、背侧氣體分佈系統27、基板/基板支座溫 ,f測系統(未顯示)、以及/或靜電夾持系統26等耦合 亚父換訊息。例如:儲存於該記憶體中之一程式可用於根The controller 14 includes a microprocessor, a memory, and a digital 1/0 崞 that can generate an input sufficient to contact and start the plasma processing system 丨 a and monitor the control voltage output from the plasma processing system la; furthermore, The controller 14 can generate with rf, impedance matching network 50, gas injection system (not shown), true == rolling system 30, backside gas distribution system 27, substrate / substrate support temperature, f measurement system (not shown) ), And / or electrostatic clamping system 26, etc. Example: A program stored in the memory can be used for root
第10頁 200426937 五、發明說明(6) 據製程策略而啟動該輸出至前述電漿處理系統1 a之組件, 以進行蝕刻包含一高介電常數介電層之閘極堆疊的方法。 控制器1 4之一例為位於美國德州奥斯汀之戴爾公司(D e 11 Corporat i〇n)所生產之戴爾精密工作站(DELL PRECISI0N WORKSTATION ) 6i〇tm。 該對話系統1 2可包含一光學對話子系統(未顯示)’ 該光學對話子系統丨2可包含一用於測量由該電漿所發射出 光強度之偵測器,如(石夕)光電二極體或光電倍增管(PMT );該光學對話子系統丨2可更包含一濾光片如窄頻干涉濾 光片。在另一實施例中,該對話系統1 2可包含至少一直線 CCD (電荷耦合裝置)、一CID (電荷注入裝置)陣列、以 及一光分散裝置如光柵或稜鏡。此外,對話系統1 2可包含 測量一已知波長光之一單色儀(如光栅/偵測器系統)、 一測量光譜用之光譜儀(如附有旋轉式光栅),如美國專 利案號5, 888, 337中所述之裝置即為一例。 該對話系統12可包含一高解析度光發射光譜學(0ES ) 感測器如波峰感測器系統(peak Sensor Systems )或真實 儀斋公司(Verity Instruments, Inc·)所出品者。此一 0ES感測器具有跨越紫外(訂)、可見(VIS )、以及近紅 外(NIR )光光譜之寬頻譜,其解析度約為丨· 4 A,亦即該 感測器可收集自2 4 0至1 0 0 〇 nm共5 5 5 0個波長,例如··該感 測器可配備咼靈敏度微小光纖UV-v IS-NIR光譜儀,其係由 2048像素線性CCD陣列依序整合而成。 ’ 該光譜儀接收經由單一及成束光纖傳遞而來的光,其Page 10 200426937 V. Description of the invention (6) The component output to the aforementioned plasma processing system 1a is activated according to a manufacturing strategy to perform a method of etching a gate stack including a high dielectric constant dielectric layer. An example of the controller 14 is a Dell Precision Workstation (6i0tm) manufactured by Dell Corporation (D e 11 Corporat) in Austin, Texas. The dialogue system 12 may include an optical dialogue subsystem (not shown). The optical dialogue subsystem 2 may include a detector for measuring the intensity of light emitted by the plasma, such as (Shi Xi) Photoelectricity 2 A polar body or a photomultiplier tube (PMT); the optical dialogue subsystem 2 may further include a filter such as a narrow-band interference filter. In another embodiment, the dialogue system 12 may include at least a linear CCD (Charge Coupled Device), a CID (Charge Injection Device) array, and a light dispersion device such as a grating or chirp. In addition, the dialogue system 12 may include a monochromator (such as a grating / detector system) for measuring light of a known wavelength, and a spectrometer (such as a rotary grating) for measuring spectrum, such as US Patent No. 5 The device described in, 888, 337 is an example. The dialog system 12 may include a high-resolution optical emission spectroscopy (0ES) sensor such as a peak sensor systems or a product produced by Verity Instruments, Inc. This 0ES sensor has a broad spectrum spanning the ultraviolet (order), visible (VIS), and near-infrared (NIR) light spectrum, and its resolution is about 丨 · 4 A, which means that the sensor can be collected from 2 A total of 5 550 wavelengths from 40 to 100 nm, for example ... The sensor can be equipped with a UV-v IS-NIR spectrometer with a micro-sensitivity micro fiber, which is sequentially integrated by a 2048 pixel linear CCD array . ’The spectrometer receives light transmitted through a single and bundled fiber.
200426937 五、發明說明(7) " 中由該光纖所輸出的光係利用一固定光柵而分散横越該直 線CCD陣列;類似上述配置,穿越一光學真空視窗所發出的 光透過一球狀凸透鏡而聚焦於該光纖之輸入端上,而特別 調整以期適用於已知光譜範圍之三種光譜儀則各形成一製 程室所用之一感測器;最後,根據感測器的利用可於每〇 i 至1秒記錄下一完整發射光譜。 在圖3所示之該實施例中,該電漿處理系統丨b可與如圖 1或2之實施例相似,除參照圖1及圖2所述之組件外,更包 含一靜止、或機械式或電動式旋轉磁場系統丨〇 〇,以大幅增 加電漿密度與/或提升電漿處理均勻性;再者,控制器=4曰 可與磁場系統60耦合,以調節轉速及磁場強度。習於此技 術者應熟知旋轉磁場之設計及裝設。 在圖4所示之該實施例中,該電漿處理系統丨c可與如圖 1及2之實施例相似,更可包含一上端電極7〇,其中“產生 器72所發出之RF功率可透過阻抗匹配網路74而與該上端電 極70耗合’以rf功率施加於該上端電極所用之一典型頻率 可介於0· 1 MHz至20 0 MHz範圍内;另外,以功率施加於該 下端電極所用之一典型頻率可介於〇1 MHz至1〇〇 mHz範^ 内,再者,控制斋1 4須與R F產生器7 2及阻抗匹配網路7 4相 耦合,以對RF功率施加於該上端電極7〇進行控制。習於此 技術者應熟知上端電極之設計及裝設。 、 在,5所示之該實施例中,該電漿處理系統丨d可與如圖 及^之實施例相似,更可包含一感應線圈8 〇,其中RF功率 係藉由RF產生器82並透過阻抗匹配網路84而與該感應線圈200426937 V. Description of Invention (7) " The light output by the optical fiber is dispersed across the linear CCD array using a fixed grating; similar to the above configuration, the light emitted through an optical vacuum window passes through a spherical convex lens and Focus on the input end of the optical fiber, and the three spectrometers specially adjusted for the known spectral range each form a sensor for a process chamber; finally, depending on the use of the sensor, it can be adjusted from 0 to 1 Record the next complete emission spectrum in seconds. In the embodiment shown in FIG. 3, the plasma processing system 丨 b may be similar to the embodiment shown in FIG. 1 or 2. In addition to the components described with reference to FIG. 1 and FIG. 2, it also includes a stationary or mechanical Type or electric rotating magnetic field system 丨 〇〇, in order to greatly increase the density of the plasma and / or improve the uniformity of the plasma processing; Moreover, the controller = 4 can be coupled with the magnetic field system 60 to adjust the speed and magnetic field strength. Those skilled in this technology should be familiar with the design and installation of rotating magnetic fields. In the embodiment shown in FIG. 4, the plasma processing system 丨 c may be similar to the embodiments shown in FIGS. 1 and 2, and may further include an upper electrode 70, in which “the RF power emitted by the generator 72 may be Consumed with the upper electrode 70 through the impedance matching network 74. A typical frequency used by applying rf power to the upper electrode may be in the range of 0.1 MHz to 20 MHz. In addition, power is applied to the lower electrode. A typical frequency used by the electrode may be in the range of 0.001 MHz to 100 mHz. Furthermore, the control module 14 must be coupled to the RF generator 72 and the impedance matching network 74 to apply RF power. Control is performed on the upper electrode 70. Those skilled in the art should be familiar with the design and installation of the upper electrode. In the embodiment shown in 5, the plasma processing system 丨 d can be as shown in Figure and ^ The embodiment is similar, and may further include an induction coil 80. The RF power is transmitted to the induction coil through the RF generator 82 and the impedance matching network 84.
第12頁 200426937 五、發明說明(8) -- 80相耦合,RF功率透過介電視窗(未顯示)自感應線圈8〇 而與電浆處理區域15相麵合,以rf功率施加於該感應線圈 80所用之一典型頻率可介於1〇 MHz至1〇〇 mHz範圍内;同 理,以功率施加於該夾頭電極所用之一典型頻率可介於〇 j MHz至100 MHz範圍内。此外,吾人可用一開槽法拉第屏蔽 板(未顯示)以降低該感應線圈8 0與電漿間之搞合;再 者’控制器14須與RF產生器82及阻抗匹配網路84相輕合, 以對RF功率施加於該感應線圈80進行控制。在另一實施例 中,感應線圈80可為與上述該電漿處理區域15聯繫之「螺 旋形」線圈或「盤餅形」線圈,正如在轉換器耦合電槳反 應器(T C P )中。習於此技術者應熟知感應式搞合線電漿 (ICP )源或轉換器耦合電漿(TCP )源之設計及裝設。 或者,該電漿可採電子迴旋共振(ECR)形成;仍有另 一實施例,該電漿係由發射一螺旋波而形成;又在另一實 施例中,該電漿係由一傳遞表面波所形成;習於此技術者 應熟知上述各電漿源。 在下列討論中將說明利用一電漿處理裝置蝕刻含一高 介電常數介電層之閘極堆疊的方法。例如:該電襞處理裝 置可包含如圖1至5所述之各種不同元件及其組合。 一典型閘極堆疊之示範實施例可包括具TEOS硬光罩之 聚矽/Hf02 /Si〇2 /Si,該矽層(Si )係作為該源/汲極, 且該S i 02介電層包含一薄(〜5 A )界面氧化物,其間或參 與增強通道移動性,然而此將部分地犧牲整體閘一介電常 數值。表1表示蝕刻穿越該聚矽層及該Hf02層並於Si 02層停Page 12 200426937 V. Description of the invention (8)-80 phase coupling, RF power passes through the TV window (not shown) from the induction coil 80 and faces the plasma processing area 15 and is applied to the induction with rf power A typical frequency used by the coil 80 may be in the range of 10 MHz to 100 mHz; similarly, a typical frequency used in applying power to the chuck electrode may be in the range of 0 j MHz to 100 MHz. In addition, I can use a slotted Faraday shield (not shown) to reduce the coupling between the induction coil 80 and the plasma; further, the 'controller 14 must be lightly coupled with the RF generator 82 and the impedance matching network 84 In order to control the RF power applied to the induction coil 80. In another embodiment, the induction coil 80 may be a "spiral" coil or a "disc-shaped" coil in contact with the plasma processing region 15 described above, as in a converter coupled electric paddle reactor (TCP). Those skilled in this technology should be familiar with the design and installation of inductive coupling plasma (ICP) sources or converter coupled plasma (TCP) sources. Alternatively, the plasma may be formed by electron cyclotron resonance (ECR); there is still another embodiment, the plasma is formed by emitting a spiral wave; and in another embodiment, the plasma is formed by a transmission surface Wave formation; those skilled in the art should be familiar with the above plasma sources. In the following discussion, a method of etching a gate stack including a high-k dielectric layer using a plasma processing apparatus will be described. For example, the electric processing apparatus may include various components and combinations thereof as described in FIGS. 1 to 5. An exemplary embodiment of a typical gate stack may include polysilicon / Hf02 / Si〇2 / Si with a TEOS hard mask, the silicon layer (Si) is used as the source / drain, and the Si 02 dielectric layer Contains a thin (~ 5 A) interfacial oxide that may be involved in enhancing channel mobility in the meantime, however this will partially sacrifice the overall gate-dielectric constant value. Table 1 shows the etching through the polysilicon layer and the Hf02 layer and stopping at the Si 02 layer
第13頁Page 13
200426937 五、發明說明(9) 止之一示範製程策略。 表1 步哦 頊部RF 底郐RF ESC-T 間味 P ESC-伏特 ESC-He 步踢:時間 BT X 7 sor z P q 1500 V 3/3 r 10 s ME 8〇r 孫 驵 1500 V 3/3 U 规i OE 臟 80TC 卿 m 1500 V 10Λ0 m 50 s PPH 2kW 900 W 801c 80 mm 2〇〇城 2000 He 0 V 0/0 2000/1000 30 s DE 250 W 20W sot 80 mm 5铖 决 3 射:100¾¾ 成 80HBr+20 C2H4*30 HBr+50㉔此 0 V 0/0 850Λ50 冷印 0W OW 80TC SO mm 200减 2000 He 1500 V 10Λ0 0/0 30 s 例如在表1中,BT表突破該原始3丨02層之第一製程步 驟;ME表包含該聚矽主要蝕刻步驟之第二製程步驟;0E表 過度蝕刻製程步驟;PPH表電漿預熱製程步驟;DE表介電 (H f 02 )餘刻製程步驟;冷卻則表基板冷卻製程步驟。 在表1所列之實施例係利用圖4所述之電漿處理系統, 其中頂部RF表上端電極RF功率,而其中X、XX、XXX分別代 表在原始氧化物突破步驟、主要步驟、以及過度蝕刻步驟 期間傳送制該頂部電極之RF功率慣用值;底部RF表示下端 (基板支座)電極RF功率,而其中y、yy、yyy分別代表在 原始氧化物突破步驟、主要步驟、以及過度蝕刻步驟期間 傳送制該底部電極之RF功率慣用值;ESC-T表該基板支座溫 度;間隙表該上端電極與該下端電極間之分隔距離,其中 z、z z、z z z分別代表在原始氧化物突破步驟、主要步驟、 以及過度蝕刻步驟期間該頂部(上端)電極與該底部(下 端)電極間之間距慣用值;P代表該處理室溫度,其中p、200426937 V. Invention Description (9) One of the demonstration process strategies. Table 1 Step RF bottom RF RF ESC-T Pitch ESC-Volt ESC-He Step kick: time BT X 7 sor z P q 1500 V 3/3 r 10 s ME 8〇r Sun Yi 1500 V 3 / 3 U gauge i OE dirty 80TC clear m 1500 V 10Λ0 m 50 s PPH 2kW 900 W 801c 80 mm 2〇〇2000 2000 He 0 V 0/0 2000/1000 30 s DE 250 W 20W sot 80 mm 5 Shot: 100¾¾ into 80HBr + 20 C2H4 * 30 HBr + 50㉔this 0 V 0/0 850Λ50 cold printing 0W OW 80TC SO mm 200 minus 2000 He 1500 V 10Λ0 0/0 30 s For example, in Table 1, the BT table breaks through the original 3 丨 02 layer of the first process step; ME table contains the second process step of the main polysilicon etching step; 0E table over-etching process step; PPH table plasma preheating process step; DE table dielectric (H f 02) The remaining process steps; cooling means the substrate cooling process steps. The examples listed in Table 1 use the plasma processing system described in FIG. 4, where the RF power at the top electrode of the top RF table, and X, XX, and XXX respectively represent the breakthrough step, main step, and transition of the original oxide. The conventional value of the RF power of the top electrode is transmitted during the etching step; the bottom RF represents the RF power of the lower (substrate support) electrode, and y, yy, and yyy represent the original oxide breakthrough step, the main step, and the overetching step, respectively. The conventional value of the RF power of the bottom electrode is transmitted during the period; ESC-T indicates the substrate support temperature; the gap indicates the separation distance between the upper electrode and the lower electrode, where z, zz, and zzz respectively represent the breakthrough step in the original oxide , The main steps, and the conventional distance between the top (upper) electrode and the bottom (lower) electrode during the overetching step; P represents the temperature of the processing chamber, where p,
第14頁 200426937 五、發明說明(ίο) PP、PPP分別代表在原始氧化物突破步驟、主要步驟、以及 過度蝕刻步驟期間該頂部(上端)電…極與該底部(下端) 電極間之該處理室壓力慣用值;ESC-伏特代表施加於該基 板支座之該電極夾持電壓;ESC-He代表基板背侧中央/邊 緣之He壓力(Torr ) ; VPP代表在該設定rF功率下,該上端 /下端電極上所產生之典型峰間評電壓,其中r、rr、rrr 分別代表在原始氧化物突破步驟、主要步驟、以及過度鍅 刻步驟期間該底部(下端)電極上之峰間電壓慣用值;epd 表示端點偵測時間。該電漿處理系統之其餘配置可具有些 被不同之參數設定值。 該DE步驟所列之流速(q )僅為反映高流速狀況(亦即 低滞留時間)之一例,其中q、qq、qqq分別代表在原始氧 ,物突破步驟、主要步驟、以及過度蝕刻步驟期間該處理 氣體流速之慣用值,所列之氣體可用以說明達到選擇性 Hf〇2 /Si蝕刻之策略,習於聚矽蝕刻等技術者應了解βτ、 ME及0Ε製程步驟及其典型製程參數。在冷卻步驟期間,吾 人移除RF功率以停止電漿處理,且該基板係透過靜電夹持 (ESC )與背側(氦氣)熱傳氣體而冷 足以將該基板溫度降至該基板支座之溫度。 0❼鐘已 在電漿預熱(PPH )期間,該基板溫度係由適合蝕刻聚 矽之溫度(如80。(:)升高至更適合Μ%選擇性蝕刻之溫度Λ 士 40〇c)。當基板僅為倚著基板支座時(亦即並未(藉 ESC )夾持且無背側氣體),該基板實質上與該基板支座^ 該周圍處理室間均為絕熱,例如圖6表示當基板靠在維持於Page 14 200426937 V. Description of the Invention (PP) PP and PPP respectively represent the treatment between the top (upper) electrode ... and the bottom (lower) electrode during the original oxide breakthrough step, the main step, and the overetch step. Conventional value of chamber pressure; ESC-volt represents the electrode clamping voltage applied to the substrate support; ESC-He represents the He pressure (Torr) at the center / edge of the back side of the substrate; VPP represents the upper end at the set rF power / Typical peak-to-peak voltage generated on the lower electrode, where r, rr, and rrr represent the conventional peak-to-peak voltage on the bottom (lower) electrode during the original oxide breakthrough step, the main step, and the overetching step, respectively ; Epd represents the endpoint detection time. The rest of the configuration of the plasma processing system may have some parameter settings. The flow rate (q) listed in this DE step is only an example of a condition that reflects a high flow rate (that is, a low residence time), where q, qq, and qqq represent the original oxygen, material breakthrough step, main step, and overetch step respectively. The conventional value of the process gas flow rate. The listed gases can be used to explain the strategy of achieving selective Hf02 / Si etching. Those skilled in polysilicon etching should understand the βτ, ME and 0E process steps and their typical process parameters. During the cooling step, I removed the RF power to stop the plasma processing, and the substrate was cold enough to reduce the substrate temperature to the substrate support through electrostatic clamping (ESC) and backside (helium) heat transfer gas. Of temperature. 0 ° C. During the plasma preheating (PPH), the temperature of the substrate has been raised from a temperature suitable for etching polysilicon (such as 80. (:) to a temperature more suitable for selective etching by M% Λ ± 40 ° c). When the substrate is only leaning against the substrate support (that is, it is not held (by ESC) and there is no backside gas), the substrate is substantially insulated from the substrate support ^ the surrounding processing chamber is insulated, as shown in Figure 6 Means when the substrate is leaning against
第15頁 200426937 五、發明說明(Π) 一較低溫度之基板支座頂上時,基板溫度對三種不同條件 之回應’若該基板並未與該基板支產夾持且因此其未受到 背侧氣體壓力影響,則基板溫度隨時間之變化將&緩^ (圖6中所顯示之實線100 );另一方面,若該基板與該基 板支座夾持但其未受到背側氣體壓力影響,則可觀察到基 板溫度變化速率隨時間略有增加(圖6中所顯示之長虛線^ 10 2),再者,若該基板與與該基板支座夾持且受到背側氣 體壓力影響,則該基板溫度起初急速下降,之後將逐漸接 近該基板支座溫度(圖6中所顯示之短虛線1 〇 4 )。 該基板之電漿預熱(PPH )發生於該基板絕熱時(亦即 ::夾持力及背側氣體壓力);通常,離子撞擊及對流熱_ 兩者均影響該基板之加熱,而電子(包含熱式及衝擊 二芥亦對加熱程序有較前二者稍弱之影響。在高度離 擊加埶Γ ^ ί感耦合電漿(ICP)、波加熱等)中,離子撞 擊加熱之影響可凌駕對流熱-中性。 離子合電聚(ccp)中,對流熱-中性之影響可與 熱=實;;r些情況下,對流熱-中性為主 -惰性氧:例中,該電漿預熱製程包含:導入 ㈣基力K.r、xe:自該惰性氣體點燃電聚; 壓、惰性該下端電極之RF功率、惰性氣體室 率所產生之与=速、與惰性氣體原子量改變對基板加熱功 端電極=f人可知:U)加熱功率隨傳送至該下 力率~加而增加(線11()) (b)加熱功率隨惰 200426937 五、發明說明(12) 性氣體流速增加而略g 性氣體壓力增加而略男^ /線114 ) (C )加熱功率隨惰 性氣體原子量增加而域=Π線11 2 ) ( d )加熱功率隨惰 )(線11 6 )。 減^ (亦即使用氦氣較使用氬氣有效 性介電圖2二:電漿預熱(ppH)法進行選擇 厚度範圍之閘介電芦二。大多數裝置包含2〇至5〇 a );在一特定PPH製%下H 典型上極短(例如約5秒 一曰達到所欲t 4 峰基板溫度與PPH時間有關, 含較PPH為低之# | ,製輊。典型上,該Hf〇2蝕刻電漿包 於理相絶勃/ 1其4,因此將大幅減少該基板加熱速率。由 可维ίΐ值:ΐίϊ溫度於Hf〇2钱刻期間(122期間)幾乎 了、,隹持疋值冷部係於1 2 4期間發生。 之選擇性㈣而言,吾人已碟知降低刚2中 ===钮刻速率;通常,以HBr__f〇2 較早獨使用純鹵素(Βγ2或(:12 )快义亲,士 &从 办, HBr、C2H4BrJ,碳(C)及氫(H)兩者父=虫=劑, 夕卜,含籠形訐之(CH2)n聚合物可形成於叫:,=促: =程序並因此提升HfBrj成程序。所有Hf f 具相近揮發度之非揮發性物質’故若使用標 屬 (如80T:),即需要藉離子撞擊以脫附HfBr ;秋^皿度— 該源/沒石夕(Si )暴露出來,含函素電衆中x之高離子撞^ 能量將令下層矽(Si )之蝕刻速率較大,故若 程步驟’該基板溫度將上升’因為當基板溫度增加:,H衣 m^m 第17頁 200426937 五、發明說明(13) H f B rx脫附速率將呈指數增加。但在高基板溫度下,一純鹵 素環境中之Si蝕刻速率亦呈指數增加,故需要如Η及C等還 原劑的存在。 在該HBr實施例中,HBr可有效地#刻Hf02,一些氣相η 的存在可抓住Br以降低該Si蝕刻速率;在一低總RF功率條 件下使用HBr並非為一有效s i银刻方式,其強離子鍵易抓住 游離Br,為更進一步降低si蝕刻速率,可將如 專氣體加至HBr中,添加物在Si上行聚合反應,可更降低si 餘刻速率;同時,由於此聚合物之還原本質,其並不妨礙Page 15 200426937 V. Description of the invention (Π) When a substrate with a lower temperature is on the top of the substrate, the substrate temperature responds to three different conditions. 'If the substrate is not clamped with the substrate support and therefore it is not subjected to the back side The influence of gas pressure will slow the temperature of the substrate over time (the solid line 100 shown in Figure 6); on the other hand, if the substrate is clamped to the substrate support but it is not subjected to backside gas pressure It can be observed that the temperature change rate of the substrate slightly increases with time (long dashed line ^ 10 2 shown in Fig. 6). Furthermore, if the substrate is clamped with the substrate support and is affected by the backside gas pressure Then, the temperature of the substrate drops rapidly at first, and then gradually approaches the temperature of the substrate support (short dashed line 104 shown in FIG. 6). Plasma preheating (PPH) of the substrate occurs when the substrate is adiabatic (ie: clamping force and backside gas pressure); usually, ion impact and convective heat_ both affect the heating of the substrate, while electrons (Including thermal and impact mustards also have a slightly weaker effect on the heating process than the previous two. In highly ionized coupled 埶 Γ ^ ί inductively coupled plasma (ICP), wave heating, etc.), the impact of ion impact heating Can override convection heat-neutral. In ion polymerization (ccp), the effect of convective heat-neutral can be equal to heat; in some cases, convective heat-neutral is dominant-inert oxygen: in the example, the plasma preheating process includes: Introduce krypton base force Kr, xe: Ignition electropolymerization from the inert gas; pressure, inertness, RF power of the lower electrode, inert gas chamber ratio = velocity, and change in atomic weight of the inert gas to the substrate heating end electrode = f It can be seen that: U) The heating power increases with the transmission of the lower force rate (line 11 ()) (b) The heating power increases with inertia 200426937 V. Description of the invention (12) The gas pressure increases slightly with the gas pressure And slightly male ^ / line 114) (C) heating power with increasing inert gas atomic weight and the domain = Π line 11 2) (d) heating power with inertia) (line 11 6). Reduced ^ (that is, using helium is more effective than using argon. Dielectric Figure 2: Part 2: Plasma Preheating (ppH) Method for Selecting the Gate Dielectric Resin. Most devices include 20 to 50a.) H is typically extremely short at a specific PPH system% (for example, about 5 seconds to reach the desired t 4 peak substrate temperature is related to the PPH time, including # | lower than PPH, making 轾. Typically, the Hf 〇2 Etching plasma packs are excellent in the physical phase / 1, so it will greatly reduce the heating rate of the substrate. The value of dimensional value: ΐ ϊ The temperature is almost in the Hf 〇2 money engraving period (period 122). The value of the cold part occurs during the period of 1 2 4. In terms of selectivity, we have already known that the rate of the button 2 is reduced; usually, the pure halogen (Bγ2 or ( : 12) Qin Yiyi, Shi & Cong Heng, HBr, C2H4BrJ, both carbon (C) and hydrogen (H). Father = insect = agent, Xibu, (CH2) n polymer containing clathrate can form It is called :, = promote: = program and therefore promote HfBrj into a program. All Hf f non-volatile substances with similar volatility 'so if the standard genus (such as 80T :) is used, it is necessary to use ion impact to desorb H fBr; autumn degree — the source / Shi Xi (Si) is exposed, the high ion collision energy containing x in the electrical element mass will cause the lower silicon (Si) etching rate, so if the process step The substrate temperature will rise 'because when the substrate temperature is increased: H clothing m ^ m page 17 200426937 V. Description of the invention (13) H f B rx desorption rate will increase exponentially. But at high substrate temperature, a pure halogen The etching rate of Si in the environment also increases exponentially, so the presence of reducing agents such as ytterbium and C is required. In this HBr embodiment, HBr can effectively #etch Hf02, and the presence of some gas phase η can grab Br to reduce The Si etching rate; using HBr under a condition of low total RF power is not an effective si silver engraving method, and its strong ion bond is easy to catch free Br. To further reduce the si etching rate, a special gas such as HBr In addition, the polymerization of the additive in Si can reduce the Si etch rate. At the same time, due to the reducing nature of this polymer, it does not hinder
Hf〇2之蝕刻速率。或者,可加入如之氣體以降低該^蝕 刻速率;或者加入雙原子氫氣(H2 )以降低該^蝕刻速 率;或者採另一常用方法以減緩該Si蝕刻速率,亦即在高 基板航度下生長SiN或SiO,吾人可透過加入含〇及/或n物 質如%或%以期達此效應。然而,製程最適化要求含〇及/ 或N物質的存在不會對該Hf〇2蝕刻速率造成負面影響丨此 外在以〇2蝕刻期間若存在足夠C及Η將可借助還原作用而 加速該熱钱刻速率。 溫度=8 0 °C ;電極間距_ 8 〇 Α/ ·例日^人可利用下列策略以達到刚2㈣速率為1649 ί職之韻刻速率選擇度為2.2: PM步驟-上端 "—_ — 7〇〇 W ,下端電極1^功率=900 w ;基板支座 _ ;壓力=50 mTorr ;氣體流Hf02 etch rate. Alternatively, such a gas can be added to reduce the etch rate; or diatomic hydrogen (H2) can be added to reduce the etch rate; or another commonly used method can be used to slow the Si etch rate, that is, under high substrate range. To grow SiN or SiO, we can achieve this effect by adding substances containing 0 and / or n such as% or%. However, process optimization requires that the presence of 0 and / or N species will not have a negative impact on the Hf〇2 etch rate. Furthermore, if sufficient C and 存在 are present during the 0 2 etch, the heat can be accelerated by reduction. Money carved rate. Temperature = 8 0 ° C; electrode distance _ 8 〇 / / example day ^ people can use the following strategies to achieve just 2 刚 rate is 1649 职 the rate of rhyme engraving selection is 2.2: PM step-upper end " ---- 〇〇〇〇, lower electrode 1 ^ power = 900 w; substrate support_; pressure = 50 mTorr; gas flow
下端電極RF功率=50 WLower electrode RF power = 50 W
W ^二持」^間—9G秒;Hf〇2㈣—上端電極RF功率=200 基板支座溫度=8 0 °C ;電極間 _ 第18頁 200426937 五、發明說明(14) 距一80 mm ;壓力=5 mTorr ;氣體流速=105 seem HBr ; 無E S C夾持、無氦氣背側氣壓;持續-時間一 1 q秒;冷卻一基 板支座溫度= 80°C ;電極間距一 80 mm ;壓力=50 mTorr ; 氣體流速=50 0 seem He ; 1 · 5 kV ESC 失持、1 〇 Torr /1 0 T o r r中央一邊緣氦氣背侧氣壓;持續時間=3 〇秒。 就Hf 〇2對S i之選擇性#刻而言,吾人已確知電漿中 之S i 〇2钱刻在咼基板溫度下仍屬離子驅動,而jj f 勉刻卻為 一種化學钱刻本質;因此’在高基板溫度下之低下端電極 RF功率狀況可在高速下化學蝕刻Hf〇2,但卻在較低速下蝕 刻S1 〇2。首先,可打斷s i — 0鍵之離子撞擊為完成任一蝕刻 所必須者,在添加C2H4或C2H4Br2之例中,該聚合物更可保護 該Si —〇鍵免於受離子撞擊,同時更進一步減緩Si〇2蝕刻速 率〇 例如吾人可利用下列策略以達到Hf〇2蝕刻速率為1649 A/min且Hf02對Si02之蝕刻速率選擇度為25 : PPH步驟一上端 電極RF功率= 700 W ;下端電極心功率= 900 W ;基板支座 溫度=80 °C ;電極間距一80 mm ;壓力=50 mTorr ;氣體流 速=500 sccm He、2 seem Cl2 ;無ESC失持、無氦氣背側 氣壓;持續時間—90秒;Hf02蝕刻—上端電極RF功率= 200 W ;下端電極RF功率=50 W ;基板支座溫度=80 °C ;電極間 距一80 mm ;壓力=5 mTorr ;氣體流速=1〇5 seem HBr ; 無ESC夾持、無氦氣背側氣壓;持續時間一 1 〇秒;冷卻—基 板支座溫度=80 °C ;電極間距一80 _ ;壓力=50 mTorr ; 氣體流速= 500 seem He,1·5 kV ESC 失持、Torr/10W ^ 2 holding "^ 9G seconds; Hf〇2㈣-upper electrode RF power = 200 substrate support temperature = 80 ° C; between electrodes _ page 18 200426937 V. Description of the invention (14) a distance of 80 mm; Pressure = 5 mTorr; Gas flow rate = 105 seem HBr; No ESC clamping, no helium back pressure; Duration-time-1 q second; Cooling-substrate support temperature = 80 ° C; electrode spacing-80 mm; pressure = 50 mTorr; Gas flow rate = 50 0 seem He; 1 · 5 kV ESC loss, 10 Torr / 10 Torr center side edge helium back pressure; duration = 30 seconds. As far as the selectivity of Hf 〇2 to Si is concerned, I have confirmed that the etch of Si 〇2 in the plasma is still ion-driven at the temperature of the substrate, but jj f is a kind of chemical money. ; So 'low-end electrode RF power conditions at high substrate temperatures can chemically etch HfO2 at high speeds, but etch S1 02 at lower speeds. First, the ion impact that can break the si-0 bond is necessary to complete any etching. In the case of adding C2H4 or C2H4Br2, the polymer can further protect the Si-0 bond from ion impact, and at the same time go one step further. Slow down the SiO2 etching rate. For example, we can use the following strategies to achieve HfO2 etch rate of 1649 A / min and Hf02 to Si02 etch rate selectivity of 25: PPH step 1 upper electrode RF power = 700 W; lower electrode Heart power = 900 W; substrate support temperature = 80 ° C; electrode spacing-80 mm; pressure = 50 mTorr; gas flow rate = 500 sccm He, 2 seem Cl2; no ESC loss, no helium back pressure; continuous Time-90 seconds; Hf02 etching-RF power of the upper electrode = 200 W; RF power of the lower electrode = 50 W; substrate support temperature = 80 ° C; electrode spacing-80 mm; pressure = 5 mTorr; gas flow rate = 105 seem HBr; no ESC clamping, no helium back pressure; duration-10 seconds; cooling-substrate support temperature = 80 ° C; electrode spacing-80 _; pressure = 50 mTorr; gas flow rate = 500 seem He , 1.5 kV ESC loss, Torr / 10
第19頁 200426937 五、發明說明(15) 丁 〇 r r中央一邊緣氦氣背侧氣壓;持續時間=3 〇秒。 PPH中被里C丨2係為防止表面雜質。在許多例子中,電 漿處理系統可包含石英組成,例如純以ppH中之雜質可包 括該石英組成中之Si〇,PPH製程步驟中微量Cl2可避免Si〇 形成於Hf 〇2層表面上;或者,於純He ppH期間,M製程步 驟(突破)可插入於該DE步驟之前,吾人已知(^4 BT有助 於自該局"電常數介電材料表面移除該y 。 在一實施例中,餘刻高介電常數介電層如jjf%之方法 包括利用一含鹵素氣體,如HBr、Cl2、HC1、NF3、Br2、C2H Jr2及F2至少其中之一;另外,該處理氣體可更包含一還原 氣體,如H2、C2H4、C2H4Br2、CH4、C2H2、C2H6、C3H4、C3H6、C 3H8、C4H6、C4H8、C4H1Q、C5H8、C5H1Q、C6H6、(:6H1Q 及(:61112 至少其 中之一。舉例來說,一製程參數空間可包含一 1至1〇〇〇 mTorr (如5 mTorr)室壓、範圍自2〇 至 1〇〇〇 seem (如 50 seem)之含一鹵素氣體流速、範圍自1至5〇〇 sccm (如5〇 seem)之一還原氣體流速、範圍自1〇〇至2〇〇〇 w (如2〇〇 w )之一上端電極RF偏量、以及範圍自1〇至5〇〇 w (如50 W) 之一下端電極RF偏量;又該上端電極偏量頻率範圍可自〇1 MHz至200 MHz,如60 MHz ;此外,該下端電極偏量頻率範 圍可自0.1 MHz 至100 MHz ,如2 MHz 。 圖9說明在一電漿處理系統中加熱基板之流程圖4 〇 〇。 加熱該基板至一較高溫度有助於處理如用以餘刻一系列不 同層之一連串製程步驟中之預熱步驟,例如在基板上形成 一閘極堆疊之複數層,該閘極堆疊可包括如含矽層、高介Page 19 200426937 V. Description of the invention (15) D 0 r r The air pressure on the back side of the helium in the center and edge; duration = 300 seconds. In CPH2, PPH is used to prevent surface impurities. In many examples, the plasma processing system may include a quartz composition, for example, impurities in pure ppH may include Si0 in the quartz composition, and a small amount of Cl2 in the PPH process step may prevent Si0 from forming on the surface of the Hf 02 layer; Alternatively, during the pure He ppH, the M process step (breakthrough) can be inserted before the DE step, and we know (^ 4 BT helps to remove the y from the surface of the bureau " constant dielectric material. In the embodiment, the method of etching a high dielectric constant dielectric layer such as jjf% includes using a halogen-containing gas such as at least one of HBr, Cl2, HC1, NF3, Br2, C2H Jr2, and F2; in addition, the processing gas It may further include a reducing gas, such as H2, C2H4, C2H4Br2, CH4, C2H2, C2H6, C3H4, C3H6, C3H8, C4H6, C4H8, C4H1Q, C5H8, C5H1Q, C6H6, (: 6H1Q and (: 61112 at least one of) For example, a process parameter space may include a halogen-containing gas flow rate and range of 1 to 1000 mTorr (e.g. 5 mTorr) chamber pressure, ranging from 20 to 1000 seem (e.g. 50 seem). Reducing gas flow rate from 1 to 500sccm (e.g. 50seem), ranging from 1 〇 to 2000w (such as 2000w) one of the upper electrode RF offset, and range from 10 to 500w (such as 50 W) one of the lower electrode RF offset; and the upper electrode offset The measurement frequency range can be from 0 MHz to 200 MHz, such as 60 MHz. In addition, the lower electrode offset frequency range can be from 0.1 MHz to 100 MHz, such as 2 MHz. Figure 9 illustrates the heating of a substrate in a plasma processing system. Flowchart 4 00. Heating the substrate to a higher temperature is helpful for pre-heating steps, such as in a series of process steps used to etch a series of different layers, such as forming a plurality of gate stacks on a substrate, The gate stack may include, for example, a silicon-containing layer, a high dielectric
第20頁 200426937 五、發明說明(16) 2常?介電層等。該方法由41〇開始,自該基板背側移除該 “則氣體壓力,例如在傳統電漿處斑系統中,該背側氣體 分=系統包含具有至少一控制閥、壓力調節器、與流量控 制器之一氣體供應系統、以及將該背側氣體分佈通道抽氣 所用之一真空泵等。當移除該背側氣壓時,例如吾人可關 閉,該氣體供應系統連接至該背側氣體分佈通道之該控制 闕等裝置,同時該真空泵可便於將此些通道抽氣以排空氣 ,。習於此系統之裝設者應明瞭用於改良該基板與該基板 座間熱傳導之背側氣體分佈系統之設計及使用。 ι在420中,吾人已移除作用於該基板上之該夾持力。舉 =言之丄該基板可利用機械力或電力而與該基板支座夾 B厭^則例中,吾人移除該靜電夾頭上作用於該基板之機 ::,在後例中,*人移除藉高電壓叱源作用於該靜電 及兮水ί 士之電壓’在410及420中,一旦該背侧氣體壓力 柄μ t已遭移除,當該基板靠在處於真空環境之該基 ^日、,該基板與該基板支座間實為絕熱關係。 一杏中,吾人將一加熱氣體導入該電漿處理系統。在Page 20 200426937 V. Description of Invention (16) 2 Often? Dielectric layer, etc. The method starts from 41. The gas pressure is removed from the back side of the substrate. For example, in a conventional plasma spotting system, the back side gas separation system includes at least one control valve, a pressure regulator, and a flow rate. A gas supply system of the controller, a vacuum pump used to evacuate the backside gas distribution channel, etc. When the backside gas pressure is removed, for example, we can shut down, the gas supply system is connected to the backside gas distribution channel The control device and the like, and the vacuum pump can facilitate the extraction of these channels to exhaust air. The installer of this system should know the back side gas distribution system for improving the heat transfer between the substrate and the substrate holder. Design and use. In 420, I have removed the clamping force acting on the substrate. For example, the substrate can be mechanically or electrically used to clamp the substrate holder B. ^ In the example , I removed the machine that acts on the substrate from the electrostatic chuck :: In the latter example, * removed the high voltage source acting on the static electricity and the voltage of the water 'in the 410 and 420, once The backside gas pressure The handle μt has been removed. When the substrate is resting on the substrate in a vacuum environment, the substrate and the substrate support have a thermal insulation relationship. In an apricot, I introduced a heated gas into the plasma treatment System. In
Kr ^ χ =,该加熱氣體可包含一惰性氣體,如He、Ar、 包含一6、、主ζ其中之一;在另一實施例中,該加熱氣體可更 匕3 π潔氣體如ci2。 於該電士點燃電漿;在450中,該實質絕熱基板暴露 一技#f脾贫又日寸間,該電漿可參照圖1至圖5並利用上述任 與該;踹i f燃。例如可透過將RF功率作用於該上端電極 一亟至少其中之一而在一電漿處理系統内點燃該Kr ^ χ =, the heating gas may include an inert gas, such as He, Ar, including one of 6, and ζ; in another embodiment, the heating gas may be a more clean gas such as ci2. The plasma is ignited at the electrician; in 450, the substantially thermally insulating substrate is exposed to a spleen and spleen, and the plasma can refer to FIGS. 1 to 5 and use any of the above; For example, the RF electrode can be ignited in a plasma processing system by applying at least one of the upper electrodes to the upper electrode.
200426937 五、發明說明(17) 電漿,如圖4中所示者。舉例而言,一製程參數空間可包含 大於20 mTorr (如50 mTorr)之一童壓、大於或等於200 seem (如50 0 seem )之一惰性氣體流速、小於或等於10 seem (如2 seem )之一清潔氣體流速、範圍自100至2〇〇〇 w (如700 W)之一上端電極RF偏量、以及範圍自1〇〇至2〇〇〇 W (如900 W)之一下端電極rf偏量;又該上端電極偏量頻 率範圍可自0· 1 MHz至200 MHz,如60 MHz ;此外,該下端 電極偏量頻率範圍可自〇·1 MHz至100 MHz,如2 MHz。例如 將基板自室溫加熱至4 0 0 °c所需之時間範圍可為6 〇至1 2 0 秒。 圖1 〇顯示根據本發明一實施例而於一電漿處理系統中 之基板上飯刻一高介電常數介電層之方法流程圖5 〇 〇。該方 2法由5 1 0開始,先提高該基板溫度,例如該基板溫度可大於 。0(^’最好該基板溫度可介於3〇〇至5〇〇。(:範圍内(如4〇() C );該基板可利用如參照圖9及上述之預熱電漿製程 (PPH )加熱。 在52 0中,吾人將一處理氣體導入用以蝕刻一高介電常 _ ”,層如H f 〇2之該電漿處理系統中。在一實施例中,該 义理氣體包含一含鹵素氣體,如HBr、Cl2、HC1、NF3、Br200426937 V. Description of the invention (17) Plasma, as shown in Figure 4. For example, a process parameter space may include a child pressure greater than 20 mTorr (such as 50 mTorr), an inert gas flow rate greater than or equal to 200 seem (such as 50 0 seem), and less than or equal to 10 seem (such as 2 seem) One of the clean gas flow rates, one of the upper electrode RF offsets ranging from 100 to 2000w (e.g. 700 W), and one of the lower electrode rf ranging from 100 to 2000w (e.g. 900 W). Offset; and the upper electrode offset frequency range can be from 0.1 MHz to 200 MHz, such as 60 MHz; in addition, the lower electrode offset frequency range can be from 0.1 MHz to 100 MHz, such as 2 MHz. For example, the time required to heat the substrate from room temperature to 400 ° C can range from 60 to 120 seconds. FIG. 10 shows a flowchart of a method for engraving a high dielectric constant dielectric layer on a substrate in a plasma processing system according to an embodiment of the present invention. The method 2 starts from 5 1 0, and first raises the substrate temperature, for example, the substrate temperature may be higher than. The temperature of the substrate may preferably be between 300 and 5000. (: in the range (such as 40 (C)); the substrate may use the preheating plasma process as described with reference to FIG. 9 and above ( PPH) heating. In 520, we introduced a processing gas into the plasma processing system to etch a high dielectric constant, such as H f 〇2. In one embodiment, the sense gas contains A halogen-containing gas, such as HBr, Cl2, HC1, NF3, Br
2體C2H4Br2及匕至少其中之一;在另一實施例中,該處理氣 、,包含一還原氣體,如H2、匕扎、、CH4、、C2H 3il4 ^ ^ C3H8 ' C4H6 > C4H8 > C4H10 ^ C5H8 ^ C5H10 ^ C6H6 > C 6^Q,2Hl2至少其中之一;又在另一實施例中,該處理氣體 匕含一含氧氣體及一含氮氣體至少其中之一,如〇2、N2、At least one of 2-body C2H4Br2 and dagger; in another embodiment, the processing gas includes a reducing gas such as H2, dagger, CH4, C2H 3il4 ^ ^ C3H8 'C4H6 > C4H8 > C4H10 ^ C5H8 ^ C5H10 ^ C6H6 > at least one of C 6 ^ Q, 2Hl2; and in another embodiment, the processing gas contains at least one of an oxygen-containing gas and a nitrogen-containing gas, such as 02, N2,
第22頁 200426937 五、發明說明(18) --- N2 0、與 N 02 〇 在530中,點燃電漿;在54η由,· I ^ 數介電層有一段時間暴露於該電漿中,該電二丨$至 圖5並利用上述任一技術將其點燃。例如可透過將叮功率作 用於該上端電極與該下端電極至少其中之一而在一電衆處 理系統内點燃該電漿’如圖4所示。舉例而言,一製程參數 工間可包含1至1000 mTorr (如5 mTorr)之一室壓、範圍 介於20至1 00 0 sccm (如50 sccm )之一含^素氣體流速、 範圍介於1至500 seem (如2 seem)之一還原氣體流速、範 圍自100至2000 W (如200 W)之一上端電極RF偏量、以及 範圍自10至500 W (如50 W)之一下端電極RF偏量;又該上 端電極偏量頻率範圍可自〇 · 1 MHz至200 MHz,如60 MHz ; 此外’該下端電極偏量頻率範圍可自〇. 1 MHz至100 MHz, 如2 MHz 〇 以上雖僅詳述本發明之某些實施例,但習於此技術者 應極易明瞭:在不背離本發明之新穎意義及優勢下,實施 例中實可作諸多調整。因此,所有此類調整均當包含於本 發明之範圍内。Page 22 200426937 V. Description of the invention (18) --- N2 0 and N 02 〇 In 530, ignite the plasma; at 54η, the dielectric layer is exposed to the plasma for a period of time, The electricity is shown in Figure 5 and ignited using any of the techniques described above. For example, the plasma can be ignited in an electrical processing system by applying a biting power to at least one of the upper electrode and the lower electrode, as shown in FIG. 4. For example, a process parameter workshop may include a chamber pressure of 1 to 1000 mTorr (such as 5 mTorr), and a range of element-containing gas flow rates ranging from 20 to 100 0 sccm (such as 50 sccm). One of 1 to 500 seem (e.g. 2 seem) one of the reducing gas flow rate, one of the upper electrode RF offset ranging from 100 to 2000 W (e.g. 200 W), and one of the lower electrode ranging from 10 to 500 W (e.g. 50 W) RF offset; and the upper electrode offset frequency range can be from 0.1 MHz to 200 MHz, such as 60 MHz; In addition, 'the lower electrode offset frequency range can be from 0.1 MHz to 100 MHz, such as 2 MHz or more Although only certain embodiments of the present invention are described in detail, those skilled in the art should readily understand that many modifications can be made in the embodiments without departing from the novel meaning and advantages of the present invention. Therefore, all such adjustments should be included in the scope of the present invention.
第23頁 200426937 圖式簡單說明 五、【圖式簡單說明】 在附圖中· 圖1為根據本發明一實施例之電漿處理系統簡化示意 圖; 圖2為根據本發明另一實施例之電漿處理系統示意圖; 圖3為根據本發明另一實施例之電漿處理系統示意圖; 圖4為根據本發明另一實施例之電漿處理系統示意圖; 圖5為根據本發明另一實施例之電漿處理系統示意圖; 圖6說明基板溫度對三種不同條件之回應; 圖7說明四個不同製程參數對基板加熱功率之貢獻; 圖8說明在處理期間基板溫度對加熱及冷卻之回應; 圖9表示根據本發明一實施例之基板加熱方法;以及 圖1 0表示根據本發明另一實施例之基板加熱方法。 元件代表符號說明 1 a、1 b、1 c、1 d電漿處理系統 15基板表面附近之處理區域 2 0基板支座 25基板 26靜電夾持系統 2 7背側氣體分佈系統 3 0真空抽氣系統 40RF產生器 5 0阻抗匹配網路Page 23 200426937 Brief description of the drawings V. [Simplified description of the drawings] In the drawings · FIG. 1 is a simplified schematic diagram of a plasma processing system according to an embodiment of the present invention; Schematic diagram of a plasma processing system; Figure 3 is a schematic diagram of a plasma processing system according to another embodiment of the present invention; Figure 4 is a schematic diagram of a plasma processing system according to another embodiment of the present invention; Schematic diagram of plasma processing system; Figure 6 illustrates the substrate temperature response to three different conditions; Figure 7 illustrates the contribution of four different process parameters to substrate heating power; Figure 8 illustrates the substrate temperature response to heating and cooling during processing; Figure 9 Shows a substrate heating method according to an embodiment of the present invention; and FIG. 10 shows a substrate heating method according to another embodiment of the present invention. Description of component representative symbols 1 a, 1 b, 1 c, 1 d Plasma processing system 15 Processing area near the substrate surface 2 0 Substrate support 25 Substrate 26 Electrostatic clamping system 2 7 Backside gas distribution system 3 0 Vacuum extraction System 40RF generator 50 impedance matching network
第24頁 200426937 圖式簡單說明 6 0磁場系統 70上端電極 72RF產生器72 74阻抗匹配網路 8 0感應線圈 82RF產生器 8 4阻抗匹配網路 •Page 24 200426937 Simple description of the diagram 6 0 Magnetic field system 70 Upper electrode 72RF generator 72 74 Impedance matching network 8 0 Induction coil 82RF generator 8 4 Impedance matching network •
第25頁Page 25
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