TW200426559A - MEMS-based, computer systems, clock generation and oscillator circuits and LC-tank apparatus for use therein - Google Patents

Abstract

MEMS-based, compliter system, clock generation and oscillator circuits and LC-tank. Apparatus for use therein are provided and which are fabricated using a CMOS-compatible process. A micromachined inductor (L) and a pair of varactors (C) are developed in metal layers on a silicon substrate to realize the high quality factor LC-tank apparatus. This micromachined LC-tank apparatus is incorporated with CMOS transistor circuitry in order to realize a digital, tunable, low phase jitter, and low power clock, or time base, for synchronous integrated circuits. The synthesized clock signal can be divided down with digital circuitry from several GHz to tens of MHz-a systemic approach that substantially improves stability as compared to the state of the art. Advanced circuit design techniques have been utilized to minimize power consumption and mitigate transistor flicker noise upconversion, thus enhancing clock stability.

Description

200426559 发明 Description of the invention: C Technical field of the invention j Field of the invention The invention relates to a micro-electro-mechanical system-type computer system, a clock generator and an oscillator circuit, and an LC energy storage device used therein. I: Prior Art 3 Background of the Invention In electronic systems and integrated circuits, oscillators are used for a variety of purposes. For example, in a radio frequency (RF) system, an oscillator is typically used for frequency conversion between low frequencies, between the basic frequency band and the passband, and through frequency mixing. In a mixed-signal circuit such as a switched capacitor circuit, a clock is required to turn the switch on and off for a specific period of time. In a microcontroller, the oscillator sets the time base or clock for this system, which sets the speed at which instructions are executed in the core. 15 At the present time, the clock and other periodic signals are integrated with the electronic devices they support, either off-chip or separate components. Current examples of this periodic signal synthesis include: a quartz crystal reference for an on-chip oscillator, which drives a phase-locked loop (PLL) and a delay-locked loop (llll), and such loops are used to generate this application Required—or multiple frequencies. They are used because they provide a high degree of stability for frequency synthesis. In autumn, this technology is not compatible with Shi Xi's integrated circuit technology. The clock synthesis can be implemented on a chip without external components, and the cost, size, and power consumption of electronic systems and integrated circuits can be greatly reduced. In fact, for some low-performance processors, the cost of this crystal reference itself exceeds the cost of the entire 5 processors. If the reference oscillator is integrated on the processor die, downsizing can be achieved and therefore the area allocated on the printed circuit board for discrete reference can be removed. In addition, a reduction in the number of pads (Pads) on the processor chip can be achieved because the interface to the reference electronic component is no longer required. Depending on the clock frequency, power dissipation can be reduced by as much as two orders of magnitude, because receiving transmitters between interfaces that do not need power are hungry. Finally, with the use of discrete silk to measure the clock, it is produced in the requirements of pLL and DLL, which is used to generate a fixed frequency of the crystal oscillator. Although these subsystems 10 are typically integrated, they can greatly increase the overall power budget. Despite the obvious and inherent advantages of this integrated clock synthesis, the development of this technology has not gained much momentum. There are many challenges, and because of unusable or poor on-wafer reference technology, temperature instability, and drift, it is impossible to generate a stable clock signal I5 on the wafer. Stability is the most important factor restricting the use of a single clock reference everywhere, because short-term instability can cut into the processor's time budget and compromise performance. Phase Noise and Unstable Looseness This oscillator is designed to provide a stable output frequency, which ideally does not shift from a central frequency typically referred to as f0. In the frequency domain, this performance performance can be represented by the Dirac-Delta function at f0. However, due to device noise such as motion and thermal noise and electromagnetic interference, this oscillator will shift from its center frequency. Therefore, there is limited power in the frequencies around the center frequency. Minimizing this phenomenon is very desirable because it can cause various problems, such as mixing with each other in the system1 and reducing the time budget that can be used in the microcontroller. Phase noise and instability are metrics, which quantify the frequency stability of a periodic signal. Phase Fengxian defines the noise power spectrum around the kiang rate. Instability is a metric that quantifies instability in the realm of time. Ideally, the occurrences of the striker signal occur at the same time interval. In an actual circuit, the edge of this signal deviates from the ideal position in this time by some amount in each cycle. The most important contributing factor to the performance of phase noise is the quality factor of the vibrator circuit. This quality factor measures the loss in a given system and is described by the following formula (1): Q = 2 7Γ .Ws / Wd ⑴ where ws is the energy stored in resonance and Wd is the energy consumed per cycle Scattered energy. The more common expression used for circuit quality factors is the following formula: < Q = f〇 / BW.3dB (2) where fO is the frequency of the resonator, and BW-3Db is the 3Db bandwidth of the quantity response. The relationship between this figure of merit and phase noise is binomial, as shown in (3): (Np / C) fm = FkT / C (l / 8Q2) (f〇 / fm) 2 (3 ) Where Np / C is the phase noise density at fm deviating from fO, p is the noise factor of the circuit, k is the Boltzmann constant, T is the temperature, and C is the output power, 200426559

, And f0 are the readout frequencies. Obviously, the phase noise performance can be enhanced by developing a vibrator with a high factor. In addition, there is a trade-off between power dissipation and Q ^ to meet high stability and low power exhaustion specifications. This phase is mixed. Fan's ideas can be explained mathematically. Please consider the ideal output of the oscillator circuit, which can be represented mathematically by the following formula: V〇 (t) = V〇sin (2 7Γ f〇t) (4) where V〇 is the signal amplitude and {is In time, the Fourier transform of this function translates into a pulse or 10 Dirac delta function in the frequency domain of frequency f0 as previously explained. Now consider introducing phase noise. The output signal in this time domain is described by the following formula: ^ 〇 (t) = V〇 sin (2 π f〇t + Φ (t)) (5) where 0 (t) represents the random process of phase noise. The process of converting any injected noise into phase noise can be understood by checking Hajimirii, time-varying phase noise model. First, consider the ideal LC network. Since the network is lossless, any noise introduced into this circuit will be maintained indefinitely. Now, consider the pulse current injected into this circuit at a certain time r. Obviously, if this pulse occurs at an oscillation spike, this signal becomes amplitude modulation. Therefore, its output does not deviate from the initial center frequency by 20, but its amplitude changes indefinitely. However, if the pulse is generated at a certain time between spikes, the phase of this exhaustion is obviously disturbed. Therefore, when this output is in this part of the cycle, the imported noise will make a significant contribution to the phase noise; and the noise introduced at this oscillation spike will not contribute to the phase noise at all. Can be set for a given oscillator structure, 8 Pulse Sensitivity Function (ISF). This function shows that the time domain area where the exhaustor is most sensitive to noise injection, and for this reason causes phase noise. Typical ... reciprocators are most sensitive to noise at the intersection with zero, and least sensitive to noise at spikes. The corresponding ISFP (0t) represents this concept. This rather straightforward theory can be used to explain the phase miscellaneous energy performance of various striker structures. For example, ring oscillators are very common in low-performance digital systems. These oscillators use an odd number of inverting states in the chain. This ISF 疋 is maximized at the zero parent and is minimized when the output is flat. When examining this ring oscillator circuit, it is clear that when one of these devices is switched off and the other device is operating in a linear region, its output signal is flat. When these devices are in the material operating area, there is very little noise connected to the output. However, when this signal crosses zero, these devices are both on and full. The potential for noise injection is maximized here because it can be emitted from the device or the power supply line. Unfortunately this corresponds to the point at which the ISF function is maximized. Therefore, this simple analysis clearly shows the reason: why the ring oscillator shows such poor phase noise performance. Furthermore, this structure is designed, for example, to switch the device as fast as possible. Therefore, the time period when the ISF is not zero is minimized. LC oscillators do not suffer from this problem. The choice of the lc resonator structure determines the performance of the phase noise, because the energy injected into the energy storage device is highly dependent on its structure. The above discussion shows that it is very desirable to have such a structure, which injects energy when ISF is minimized, and does not inject energy when isf is maximized. Many LC structures approach this performance. For example, 'in the Colpitts structure, this active device injects current at voltage spikes' which corresponds to the point where the ISF is low. This is why this structure is so common. The performance of its phase noise is excellent. Technology There are many different technologies used for oscillators and clock generation circuits, the most popular of which is a crystal oscillator. This crystal ambiguity ^ ㈣eh #) element is used in the high-quality and therefore high-performance performance of the Lai Lai. Most of this electronic system currently uses a crystal oscillator. The disadvantages of this crystal include that it is quite expensive, large, and cannot be integrated with transistor electronics. This crystal is typically off-wafer and can take up board area and is a significant portion of the integrated circuit it supports. This intensive buried application is a considerable bottleneck towards miniaturization. In addition, the cost of these crystals can actually approach the cost of the integrated circuit itself that they support. In low performance applications, on-chip oscillators are often used because they can be manufactured cheaply 'and use the smallest silicon wafer area. However, as discussed previously, this integrated structure, such as a ring oscillator, suffers from very poor phase noise performance. Some contributing factors for this can be reduced using careful design techniques, but even in this case, high-performance performance cannot be achieved. Other integrated structures include the use of planar capacitors and inductors on a wafer to form LC energy storage devices. This lC energy storage device is typically used as a reference for more stable oscillators, but its performance is still poor due to the lack of high-quality inductors and capacitors in standard Cmqs technology. This can be largely attributed to the loss of the substrate and the series resistance in each device. For example, a POLY-POLY capacitor has a very high series resistance, and therefore the quality factor Q is greatly reduced. 200426559 MEMS can provide integration and high performance. So far, a variety of high-Q MEMS components have been shown, of which only a few include: cis-5 mechanical resonators, resonant cavities, and resonant films. For embedded microcontroller applications, crystals are typically used in phase-locked loops (pLL) 5, which double the low-frequency reference: from tens of millions of hertz to hundreds of billions of terahertz. This fref is typically generated by a low frequency crystal oscillator. The phase detector compares this phase to the phase from the vc0 signal, which is divided by a pre-converter. After filtering, the VCO is controlled by the output signal. If the PLL and the crystal oscillator can be replaced by a separate adjustable performance oscillator on the chip 10, a significant improvement in cost, size, and power consumption can be achieved. Although a dynamic clock frequency is used, power savings can be achieved by reducing the clock frequency, while low performance is implemented in the microcontroller core. The relationship between this dynamic power and frequency can be expressed by the following formula (6): 15 P = aCLV2DDf (6) where P is the dynamic power consumption, α is the positive switching frequency as a percentage, CL is the load capacitor, and vDD is the power supply voltage And f are clock frequencies. Therefore, power is directly proportional to frequency, and this ability to adjust the clock frequency is directly converted to power savings. In addition, if an error checker is implemented in the core, this system can be overclocked using a VCO. Therefore, in very high performance applications, this VCO can be adjusted to execute as fast as possible. Many researches and developments have been carried out for some time now, integrating various off-chip microelectronic components. This support for oscillator circuits 11 200426559 Holding electronic components such as crystals is one of the key areas where integration has yet to be achieved. The motivation for integration and the challenges associated with this integrated vibrator are mentioned here. Motivation for integration There are many benefits associated with high-level microelectronic integration. The first and most important are costs. A large part of the cost associated with integrated circuits is in the packaging of the circuit. Therefore, in any system, if the number of tritium components can be reduced, the cost of the entire system can be greatly reduced. Power is also important, especially as portable devices increase in importance. The power required to transmit signals across the printed circuit board is approximately two orders of magnitude greater than the power required to transmit internal signals over 1C. Therefore, considerable power savings can be achieved through integration (integration) at the IC level. Finally, size reduction has recently been the main driving force in IC technology. In many applications, size and weight are the most important. Integration has drastically reduced the size of this microelectronic system. 15 Tricks related to this integrated oscillator circuit As explained earlier, most oscillator circuits use quartz crystal technology. In order for it to be feasible, this integrated solution must provide comparable performance. This is a difficult task because most chip-on-chip oscillators exhibit very poor performance due to the lack of high-factor components on the chip. In addition, what is of interest and concern is manufacturing technology. If MEMS is truly adopted as a solution for integrated oscillators, it must be simple, cost-effective, and truly consistent with CMOS process technology. Several approaches have been purchased to integrate MEMS technology with CMOS. This includes: pre-processing 12 200426559 MEMS first method, for example, Sandia's iMEMS process and UC-Berkeley's MICS process, mixed MEMS process and circuit technology, and post-processing, MEMS final method. However, most commercial manufacturing facilities are unable to accept pre-processed wafers due to concerns over equipment contamination. 5 Significant differences between SOI technology in bulk silicon nTFT devices and SOI nTFT devices include the existence of BOX and oxides around SOI devices, which provide better isolation between devices when compared to monolithic Shi Xi . Moreover, the junction capacitance of the SOC device is an order of magnitude smaller than that of the monolithic device, which can be directly converted into higher speed and lower power. Other advantages of this SOI technology include: • Reduced short path effects due to the shallow electrodeless and source regions of the device. In addition, SOI devices show better subcritical slopes, lack of body effect, improved package density, and freedom from locking. The S01 device can be fully depleted (FD: fully depleted) or partially deficient (PD: PartiaUy depleted). When the FD device is on, the body under the gate is completely lacking in charge. However, the critical voltage of this device is a strong function of the thickness of the Shi Xi layer and is therefore difficult to control. However, the junction between the source and the electrode is very shallow, and therefore the resistance between the source and the electrode is high, which is not desirable. So far, most of the work of SOI is to empty only a part of the body (b〇dy) below the gate of the PDS0I 20 ′. This technique overcomes the problems associated with FDS0I, but introduces the effect known as floating bodies (like a heart kiss). This effect can be attributed to the fact that when the device is turned on, the body of the device is not completely empty. Therefore, these devices show a shift in the threshold voltage, and a time pattern of hysteresis 13 200426559 due to the charge from the body produced by the impact ionization. However, PD SOI showed an improvement of 20-35% over the performance of Rectification + & & Basket Silicon. And so recently, most of them are concentrated in PD SOI. CMOS Integration Opportunity 5 10 This is an ideal substrate for integrating multiple technologies. First of all, the BOX and the insulating oxide greatly reduce the face-to-face ratio in the device, and the digital and RF components are integrated in a single device. Therefore, it is possible to mount a chip-like chip—the whole challenge. In addition, its display can be made in bulk CMOS due to poor insulation as a high-performance and low-cost MEMS device in soi. Finally, the speed and power performance gains achieved in SOC [make it the substrate of choice for SOC and microsystem solutions. Despite the original benefits of SOI technology, most integrated circuits are currently manufactured in monolithic CMOS. Hyundai's holistic process provides the opportunity to integrate multiple technologies into early films. E.g'. Taiwan Semiconductor 15 Manufacturing Company's mixed-mode process support: multiple metal layers for a wide range of circuits, MIM capacitors for analog and RF circuits, and thick top metal layers for RF devices such as inductors.

Many previous works on MEMS in MOS show this MEMS technology, and it is claimed that this MEMS 20 device is compatible with CMOS technology. However, these reported devices all require special process steps that are quite different from standard CMOS manufacturing. These previous work did not actually show: MEMS devices in a truly standard CMOS process, and active transistor electronics in the same process. MEMS devices have recently become very interesting words in SOI 14 200426559. The entire structure of this substrate provides many opportunities to manufacture MEMS devices with low process complexity. For example, a device layer of a wafer can be used as a structural material for a MEMS device. This material is monocrystalline, and therefore its material characteristics are superior to those of polycrystalline silicon. In addition, the box can be used as a built-in release layer for these structures. In fact, this technique can be used to make a suspended monocrystalline silicon device with a mask. In addition, a BOX can be used as the rear end or front end | This is useful for applications where the substrate area is removed from around the device in order to minimize light-on losses. 0 iiiiifi and Weak Inversion Lightning Weak Inversion is the operating structure of the device, where]] ^ 〇; 5 The device has not been completely inverted. When the gate voltage of this device exceeds the threshold voltage and causes a complete reversal in the path between the source and the > and the electrodes. In a voltage range where this surface inversion occurs but is less than the critical voltage, the device is said to be in weak inversion. Its 5 operating areas have many interesting characteristics, the most notable of which is the enhanced conductivity of this device. The conductivity in this structure is given by ...

Sm = I〇 / V τ (7) where ’ID is the drain current and Vr is the thermal voltage. This formula can be compared with the following formula for devices in strong inversion: 20 1/9 gm = (2 // Cax (W / L) ID) 1/2 (8) where # is the drift rate and Cax is the MOS capacitor , And W and L are each the width and length of the device. Obviously 'the conductivity of this device is proportional to the square root of Id in strong inversion' and proportional to ID in weak inversion. Therefore, this weak reversal is very attractive because the current can be driven with minimal current: and therefore the gain of the device is maximized. Therefore, power consumption can be minimized. In oscillator applications, this method is very suitable ... because a minimum loop gain is required to start the oscillator. By using this weak inversion technology, the starting power can be as low as 50%. One of the lowest power VCOs using weak inversion technology is currently shown. MEMSLC element The most common design used for high performance VCOs is the LC energy storage device. This is mainly because the LC energy storage device can be easily integrated with CMOS technology, and the performance of this LC energy storage device is better than that of the integrated ring oscillator. The best characteristic of the performance of this LC energy storage device is its figure of merit. This LC energy storage device with a high Q factor will provide a narrow response and is therefore suitable for stable performance. Therefore, maximizing the quality of Lc energy storage is a topic of much research. Much work has been done so far in the field of micromechanical variable capacitor diodes (Varact 00 domain 15). The simplest design for this device is shown in Figures 1 and 2. Young and Boster revealed A type of removable metal top plate, which is typically pure, suspended from a fixed bottom plate and supported by a mechanical network of arms, as shown in Figure i. By applying a voltage vDC across this device, this can be The movable top plate can be offset by some distance X, and therefore the capacitance of this device can be adjusted. This variable capacitance diode can be used as a variable device for adjusting the VCO. The reminiscent capacitance is given by: C = ε A / xa (9) and ε is the electrical conductivity of air, A is the overlapping area of the plates, and & is the rated distance between plates 16 200426559. Therefore, for the variable resistance this formula becomes: C = ε A / (xa-x) (10) X is the displacement forced by the adjusted voltage. The electrostatic force generated by the voltage between the plates is given by: 5 Fe = l / 2 (dC / dx) V2DC = 1/2 CV2DC / (Xa-x) 2 (11) This effective electrical spring constant is shown by the following formula Q2):

Ke = 丨 dFe / dx 丨 = CV2Dc / (xa-x) 2 (X2)

This mechanical elastic constant km is related to the ceiling suspension, and the restoring force F is generated by this suspension. And] ^ with? The relationship between 111 is shown by Hook's Law 10:

Fm = kmx (13) The magnitude of this Fm and km is equal when balanced kmX = 1/2 CV2DC / (xa.x) 2 = 1/2 ke (Xa-x) (14) Finally, this is expressed in km The formula can be as follows: kex = 2kmx / (xa-x) (15) When X = xa / 3, the two spring constants are equal. Beyond this point, the power exceeds the maximum mechanical restoring force and the two plates are pulled together. Therefore, the adjustment voltage related to this offset x = xa / 3 is called the pull-in voltage. It will be easy to show that the theoretical adjustment range of this device is less than 50%. In Figure 2, ° γρ and CBP represent parasitic capacitances to the substrate. These parasitic capacitors degrade the adjustment range, as shown in the study of ¥ 〇11] and 805. In typical oscillator applications. It is negligible because both the base plate and the base plate are grounded. However, Ctp appears to be in parallel with the adjustable capacitor. In addition, there is a considerable adjustment voltage across it. Therefore, this device has no 17 to achieve its theoretical conversion range, because CTP limits the amount of total capacitance that can be adjusted by this top plate deflection. This study was continued by Zou et al. And reached an adjustment range of 69.8%. The corrections disclosed in FIG. 3 are illustrated. Here the control voltage is applied across a large gap and the adjustable part of the variable capacitor diode is across a small gap. Although this clever technology can greatly enhance its adjustment range, it is not compatible with CMOS.

Yao et al. Used a lateral comb structure to show an adjustment range of 300%. This structure was made in SOI using deep reactive ion etching (DRIE) technology. However, this device can cause integration problems with standard CMOS processing and is therefore not suitable for monolithic applications. Table 1 summarizes previous studies in this area. Table 1 Summary of previous MEMS variable capacitor diode research Reference device adjustment range Rated capacitance Q Frequency Annual Yoon and Nguyen Parallel plate 7.7% 1.14pF 291 1GHz 2000 Zou et al. Modified parallel plate 69.8% 58pF NA NA 2000 Yao et al. Comb 300% l-5pF 100 400MHz 1998 Fan et al. Hanging parallel plate NA 500pF NA NA 1998 Young and Boser Parallel plate 16% 2pF 60 1GHz 1997 Recently, micro-mechanical technology was used to reveal a variety of high performance integrated inductors. Many of these devices are designed to achieve high figures of merit. For example: Yeh et al. Disclose a copper encapsulation technique that produces an inductor with a factor of more than 30 at 5 < 319 [2. Yoon et al. Used a coil structure in electroplated copper to make an inductor with a Q-factor of 16.7 at 20.4 GHz. 18 200426559 The key factor in the performance of the inductor Q is the loss of the substrate for the following reasons: the turbine current and the series resistance in the device material. For this reason, these suspended inductors and copper inductors have been the subject of considerable research. For example, Fan et al. Revealed a high-performance performance suspension inductor, 5 which uses a micromechanical hinge to lift this inductor onto a substrate at 250 // m. A summary of this previous work is shown in Table 2. Table 2 summarizes the previous research on integrated inductors. Reference device Rated capacitance Q Frequency Annual Roger et al. Copper plating 2.6nH 17 2.5GHz 2001 Yeh et al. Copper package 2.12nH 30 5GHz 2000 Yoon et al. Copper-plated coil 2.67ηΗ 16.7 2.4GHz 1999 Ribas et al. Suspended 4.8η 16 16 16GHz 1998 Fan et al. Suspended 24ηΗ ΝΑ 6.6GHz 1998 Young et al. 3D copper coil 4.8ηΗ 30 1GHz 1997 Hisamoto et al. Suspended in SOI 7.7ηΗ 11 19.6GHz 1996

Many of these devices face significant challenges in integrating with CMOS technology. In fact, some are not compatible with CMOS at all. Various integrated oscillators are reported. In addition, many different technologies can be developed to achieve a fully integrated oscillator. Important advantages for these devices include: power and phase noise performance for each oscillator. Table 3 summarizes recent research in this area. 19 200426559 Table 3 Summary of recent VCO studies Reference technology Phase noise density Power frequency Annual Roger et al. Copper inductor bipolar 106dBc / Hz @ 100kHz 18mW 2GHz 2001 Samori et al. Bipolar-104dBc / Hz @ 100kHz 14mW 2.6GHz 2001 Demeui • et al. Flat 1C inductor BiCMOS -125dBc / Hz @ 600kHz 34.2mW 2GHz 2000 Dec and Suyama MEMS variable capacitor diode wiring inductor CMOS -126dBc / Hz @ 600kHz 15mW 1.9GHz 2000 Dec and Suyama MEMS variable capacitor II Polar Body Inductor CMOS -122dBc / Hz @lMHz 13.5mW 2.4GHz 2000 Klesper and Ducera Integrated Inductor Variable Capacitance Diode Diode BiCMOS • 129dBc / Hz @ 3MHz 18mW 2.4GHz 2000 Zannoth et al. Flat 1C Inductor Bipolar -139dBc / Hz @ 4.7MHz 29.7mW 1.8GHz 2000 Harada et al. Flat 1C Inductor CMOS / SIMOX -110dBc / Hz @lMHz NA 2GHz 2000 Hung and Kenneth Flat 1C and Wiring Inductor CMOS -126dBc / Hz @ 600kHz 12.7mW 1.1GHz 2000 Svelto et al. MOS variable capacitor diode wiring inductor CMOS -119dBc / Hz @ 600kHz 12mW 1.3GHz 2000 Young et al. MEMS variable capacitor diode CMOS -1 05dBc / Hz @ 100kHz NA 1GHz 1999 Zohios et al. Integrated Copper Inductor Diode BiCMOS -122dBc / Hz @ 600kHz 21mW 1GHz 1999 Young et al. MEMS Variable Capacitor Diode 3D Coil Inductor CMOS -136dBc / Hz @ 3MHz 43mW 859MHz 1998 Roessig et al. MEMS resonator CMOS • 88dBcHz / Hz @ 500Hz NA 1022MHz 1998 Craninekx And Steyert planar 1C inductor CMOS -116dBc / Hz @ 600kHz 6mW 1.8GHz 1996 Craninekx And Steyert wiring inductor CMOS -115dBc / Hz @ 200kHz 28mW 1.8GHz 1995 Many single-package clock parts are obtained from shopping malls: for example, from Texas Instruments, and via electronic distributors such as Digi-Key5. This type of clock typically uses a macroscopic crystal as the time for this system. See 20 200426559. In addition, such clocks tend to consume considerable power. The simple ring oscillators used by many circuit design companies are only suitable for very low performance applications. Many technologies have been developed for radio frequency (RF) applications. Significant contributions in this area will be cited in the following 5 chapters. The focus of these studies is on the development of low-phase noise oscillators for cellular communications. Related Technology Documents MEMS Variable Capacitor Diodes: US Patent No. 6,242,989 "Article comprising a 10 Multi-Port Variable Capacitor ·" US Patent No. 5,959,516 "Tunnable-Trimmable Micro Electro Mechanical System (MEMS) Capacitor ·" US Patent No. 6,215,644 "High Frequency Tunable Capacitor." 15 D. Young et al., Micromachined-Based RF Low-Noise

Voltage Controlled Oscillator, "IEEE CUSTOM INTEGRATED CIRCUITS CONFERENCEpp, 431-434, 1997 J. Zou et ·," Development of Wide Tunning Range MEMS Tunable Capacitor for Wireless Communication 20 Systems, ", INTERNATIONAL ELECTRON DEVICES MEETING, pp403-406, 2000 · J. Yao et al "" High Timing Ratio MEMS Based Tunable Capacitors for RF Communications Applications, "SOLID-STATE SENSORS AND ACTUATORS WORKSHOP, PP. 124-127, 1998 21 200426559 J.-B. Yoon et al.? ?? A High-Q Tunable Micromechanical Capacitor with Moveable Dielectric for RF Applications, "INTERNATIONAL ELECTRON DEVICES MEETING, PP.20.4 1-20.4.4, 2000. 5 L · Fan et al, ·" Universal MEMS Platforms for Passive RF Components: Suspended Inductors and Variable Capacitors, "pp. 29-33, 1998. US Patent No. 6,232,847:" Trimmable Singleband and Tunable Multiband Integrated Oscillator Using Micro -Electromechanical 10 System (MEMS) Technology · "MEMS inductor L. Fan et al ·, ”Univeral MEMS Pl atforms for Passive RF Components: Suspended Inductors and Variable Capacitors, " pp.29-33,1998. 15 J-L. Yeh et al ·, "Copper-Encapsulated Silicon Micromachined

Structure. &Quot; IEEE JOURNAL OF MICROELECTROMECHANICAL SYSTEMS, Vol.9, No. 3 pp.281-287, Sept. 2000. J.-B Yoon et al./'Surface Micromachined Solenoid On-Si and On-Glass Inductors for RF Applications. ”IEEE 20 ECECTRON DEVICE LETTERS, Vol. 20, No. 9, pp 487-489, Sept 1999. JW Rogers et al./Tost-Processed Cu inductors with Application to a Completely Integrated 2-GHz VCO.” IEEE ELECTRON DEVICE LETTERS, VOL. 48, No. 6, ρρ. 22 200426559 1284-1287? June 2001. RPRibas et al., `` Monolithic High-Performance Three-Dimensional Coil Inductors for Wireless Communication Applications, " INTERNATIONAL ELECTRON DEVICES 5 MEETING, ρρ · 3 · 5 · 1-3 · 5 · 4 ·

D. Hisamoto et al, · ’’ Silicon RF Device Fabricated by USLI Processes Featuring 0.1- // m SOI-CMOS and Suspended Inductors, "·

SYMPOSIUM ON VLSI TECHNOLOGY DIGEST OF 10 TECHNICAL PAPERS pp, 104-105, 1996. RPRibas, et al./? Micromachined Planar Spiral Inductor in Standard GaAs HEMT MMIC Technology · ,, IEEE Electron Device Letters, Vol. 19, N0.8 , PP.285-287, Aug, 2000 · Circuit Layout and Oscillator Oscillator 15 US Patent No. 6,292,065, Differential Control Topology for

IC vco · ”JW Rogers et al /? A completely Integrated 2GHz VCO with Post Processed Cu Inductors,“ IEEE CUSTOM INTEGREATED CIRCUITS CONFERENCE. 20 PP, 575-578, 2001. C. Samori et al./?A Fully-Integrated Low-Power Low-Noise 2.6 GHz Bipolar VCO for Wireless Applications, "IEEE Micrewave AND Wireless Components LETTERS, Vol.ll3No.5? Pp 199 -201, May 2001. B · Demuer et al ·," A 2GHz Low-Phase- Noise Integrated 23 200426559 LC-VCO with Flicker-Noise Upconversion Minimzation,? ΊΕΕΕ JOURNAL OF SOLID-STATE CIRCUITS, Vol. 35 No.7? Pp? 1034 -1038, July 2000.

A. Dec et al.? '' Microwave MEMS-Based Voltage-Controlled 5 Oscillators / ΊΕΕΕ TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, ν〇1 · 48, Νο · 11, ρρ, 1943-1949, Νον · 2000 ·

I. Novof, etal, `` Fully-integrated CMOS phase-locked loop with 15 to 240 MHz locking range and +50 ps jitter. '' Solid-State Circuits Conferene, 1995. Digest of 10 Technical Papers. 42nd ISSCC, 1995 IEEE International, 15-17 Feb. 1995, pp 112-113, 347 · A. Dec et al ·, "Microwave MEMS-Based Voltage-Controlled Oscillators / ΊΕΕΕ TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, Vol. 48, No.ll, Nov. 200015 B.-U. Klepsecr et al./?A Fully Integrated SiGe Bipoar

2.4GHz Bluetooth Volatage Controlled Oscillator, " IEEE RADIO FREQUENCY INTETRATED CIRCUITS SYMPOSIUM, PP, 61-64, 2000. ML Zannoth et al. ,,, A Single-Chip Si-Bipolar 1.6GHz VCO 20 With Integrated-Bias Network, ' 'IEEE TRANSACTITONS ON MICROWAVE THEORY AND TECHNIQUES, Vol. 48, No. 2, pp.203-205, Feb. 2000. M. Harada et al ”` `2-GHz RF Front-End Circuits in CMOS / SIMOX Operating at an Extremely Low Voltage of 24 200426559 0.5V ,,, IEEE JOURNAL OF SOLID-STAATE CIRCUITS, Vol.35, No.l2, pp.2000-2004, Dec.2000. CMHung et al./?A Packaged 1.1GHz CMOS VCO With Phase Noise of -126dBc / Hz at a 600-kHz Offfset / ΊΕΕΕ Journal

5 OF SOLID-STATE CIRCUITS, Vol.35, No.l, pp.l00-103, Jan. 2000 · F. Svelto et al./?A 1.3GHz Low-Phase Noise Fully Tunable CMOS LC VCO /? IEEE Journal OF SOLID-STATE CIRCUITS, VoL35, No. 3, pp. 356-361, Mar. 2000 ·

J, Zohios et al., "A Fully Integrated 1 GHz BiCMOS 10 VCO / TROCEEDINGS OF THE 6th IEEE INTERNATIONAL CONFERENCE ON THE ELECTRONICS CIRCUITS ANS SYSTEMS, Vol.l, pp.l93-196, 1999. DJ Young etal./?A Low-Noise RF Voltage-Controlled Oscillator Using On-Chip High-Q Three-Dimensional Coil Inductor And

15 Micromachined Variable Capacior /? SOLID-STATE SENSOR AND ACTUATOR WORKSHOP, PP.128-131, 1998TA Roessig et al./?Surface-Micromachined 1MHz Oscillator With Low-Noise Piere Configuration. &Quot; SOLID-STATE SENSOR AND ACTUATOR WORKSHOP , 1998. 20 J. Craninckx et al., "A 1.8-GHz CMOS Low-Phase-Noise

Voltage-Controlled Oscillator Using Optimized Hollow Spiral Inductors / 5 IEEE JOURNAL OF SOLID-STATE CIRCUITS, Vol.32, No.5, pp.736-744, May 1997 · J. Craninckx et al ·, "A 1.8-GHz CMOS Low -Phase-Noise 25 200426559

Voltage-Controlled Oscillator With Pres calar, "IEEE JOURNAL OF SOLID-STATE CIRCUITS, Vol.30, No.l2pp. 1474-1482? Dec.l995. D. Young et al./?A Micromachined Based RF Low-Noise 5 Voltage -Controlled Oscillator / ΊΕΕΕ CUSTOM INTEGRATED CIRCUITS CONFERENCE, PP.431-434, 1997 · [Akimoto 3 Summary of the Invention The content disclosed by the present invention includes: a MEMS-type computer system, a 10-pulse generating and oscillating circuit, and a circuit used therein LC energy storage device. This circuit and device can be made on a single substrate without external components. In one embodiment, the MEMS clock generator is used to generate a highly stable digital output signal without external components. The circuit includes: a substrate and an oscillator disposed on the substrate. The oscillator includes: a high-Q 15 MEMS LC-energy storage device for generating high-frequency periodic signals. The circuit also includes: made on a substrate The first circuit is used to convert this period signal into a high-frequency digital output signal. This period number can be a sine wave and has the original frequency. This output is numbered as a square wave The frequency is half of the original frequency. 20 The clock generation circuit may further include a second circuit also made on the substrate for dividing the frequency of this digital output signal into at least one lower desired application Frequency, and therefore reduce the phase noise of this signal, thereby increasing its stability. CMOS-compatible processes can be used to make this _ and 26 200426559 circuits and oscillators on the substrate. This CMOS-compatible process It can be a monolithic process or a SOI CMOS process. The periodic signal can be a sinusoidal differential signal, and the first circuit can convert the differential signal into a single terminal signal. The first circuit can also convert the single terminal signal into : High-frequency square-wave digital output signal. This second circuit may include a flip-flop connected to the first circuit: used to divide the frequency of this square-wave digital output signal into at least one lower desired 10 application frequency. The substrate can be a monolithic or SOI substrate. In another embodiment, a MEMS-type oscillation circuit is provided for generating a low-noise high-frequency periodic signal. The oscillation circuit includes: Board, and a high-Q MEMS LC energy storage device made on a substrate using a CMOS compatible process. This 15 circuit also includes another circuit that is made on the substrate using a CMOS compatible process and connected to the LC storage The device can be configured to generate a periodic signal. This frequency is variable to adjust the oscillating circuit in response to a control input. This CMOS-compatible process can be a monolithic process or a SOI CMOS process. 20 This oscillating circuit can be a double-balanced oscillating circuit to reduce the up conversion of unstable noise. The LC energy storage device may include at least one micro-electromechanical variable capacitor diode, and its capacitance is changed in response to a control input. The at least one variable capacitor diode may include a top plate, and the circuit may include a bypass capacitor to block control inputs from the rest of the circuit to the top plate. This oscillator circuit can be a double-balanced cross-coupled oscillator circuit to reduce the up conversion of unstable noise. 5 In another embodiment, a MEMS-type LC energy storage device is provided which has a high quality factor. The device has a substrate and at least one micro-electromechanical variable capacitor diode fabricated on the substrate in a CMOS-compatible process. The device also includes a micro-electro-mechanical inductor connected to at least one variable capacitor diode and fabricated on a substrate in a CMOS-compatible process. 10 The at least one variable-capacitance diode may have a variable capacitance to provide a range of adjustment of the device. This capacitor can be suspended from the substrate and released during or upon completion of this CMOS compatible process. The inductor may be hollow and suspended on the substrate by a fixing member 15, which is defined by a CMOS-compatible process. The at least one variable capacitor diode may have a fixed bottom plate and a movable top plate suspended on the fixed bottom plate, and is released during or upon completion of the CMOS-compatible process. The top plate can be deflected according to the control input to adjust the capacitance of at least one variable 20 capacitor diode. This top plate can be suspended from the bottom plate by a mechanical suspension network 'defined by a CMOS compatible process. The at least one variable-capacitance diode and the inductor may be defined by a conductive layer in a CMOS-compatible process. 28 200426559 This conductive layer can be a metal layer. This CMOS-compatible process can be a monolithic or sol SMOS process. The top plate may have multiple etched holes to facilitate the release of the top plate during this process or upon completion. 5 This substrate can be a monolithic or SOI substrate. The at least one variable-capacitance diode and the capacitor may be defined by a MiM layer or two quasi-metallic circuit layers. In other embodiments, the MEMS-type clock generating circuit is provided for generating a stable digital output. signal. This circuit includes: a vibrator made on a 10 苐 substrate, and includes: Nan-Q MEMS LC energy storage device for generating periodic signals. The circuit further includes a first circuit formed on the second substrate for converting the periodic signal into a high-frequency digital output signal. The first and second substrates may be different, or may be the same, so that the clock generation circuit may be a single circuit. 15 In yet another embodiment, a computer system is provided. The computer system includes: a data bus, a central processing unit bidirectionally connected to the data bus, a temporary memory bidirectionally connected to the data bus, and a persistent memory bidirectionally connected to the lean bus. The computer system further includes: a MEMS-type clock generating circuit for generating a highly stable digital output 20 signal, which is suitable for use in a computer system. The clock generation circuit includes: an oscillator made on the first substrate, and includes: a high qmemslc storage device for generating a periodic signal. A first circuit made on the second substrate is used to convert this periodic signal into a high-frequency digital output signal. The features and advantages of the present invention will be apparent from the following detailed description of the best mode for carrying out the present invention with reference to the accompanying drawings. Brief description of the drawing. Figure 1 is a schematic top view of a conventional micro-electromechanical variable capacitor diode. 5 Figure 2 is a conventional variable capacitor diode in the first figure along line 2-2. Fig. 3 is a schematic side view of another variable capacitor diode of the conventional technology; Fig. 4a is a perspective sectional view of a variable capacitor diode constructed according to the first embodiment of the present invention; 10 Fig. 4b is a schematic perspective view of a variable capacitor diode constructed according to the second embodiment of the present invention; Fig. 4c is a part along the line 4c-4c of the second embodiment of the conventional technology in Fig. 4b A side sectional view; Figure 5a is a perspective sectional view of the variable inductor 15 constructed according to the first embodiment of the present invention; Figure 5b is a variable inductor constructed according to the second embodiment of the present invention_ Perspective view of the device; Figure 6 is a schematic circuit diagram of the energy storage device of the present invention; Figure 7a is a schematic circuit diagram 20 of the oscillator core of the first embodiment of the present invention; Figure 7b is a second embodiment of the present invention. The schematic circuit diagram of the vibrator core; FIG. 7c is the schematic circuit diagram of the oscillator core of the third embodiment of the present invention 30 200426559 Fig. 8a is a schematic circuit diagram of a vibrator structure in the first embodiment of the present invention; Fig. 8b is a schematic circuit diagram of a unitary CMOS-MEMs clock reference circuit in the second embodiment of the present invention; 9 core 9 (1 is a perspective overview diagram collectively provided in a simplified manufacturing flowchart of a standard monolithic or SOI CMOS process used in the present invention; and FIG. 10 is a synchronous semiconductor device on a single substrate of the present invention A schematic perspective view of the device, which includes a plurality of electronic subsystems and seals for the device. 10 [Embodiment] Detailed description of the preferred embodiment Now please refer to FIG. 4a, whose description is usually made on an SOI substrate. The first embodiment of the variable capacitor diode in 40 is aimed at the most important disadvantages related to the previous research of MEMS variable capacitor diodes. First, I5 this process is CMOS compatible in order to achieve a single Second, this adjustment range is quite wide. Third, its quality factor is high. All these issues for variable capacitor diodes are discussed below. First, the capacitive diode is made into a parallel plate as part of a standard CMOS process, which uses a metal insulator (metal) layer 20 or a suitable metal wiring layer. The swing arm 45 supports the top plate 42 on the bottom plate 44. These support arms 45 can be designed in any shape so as to appropriately suspend the top plate 42. No further processing steps are required to define this structure. However, the plates 42 and 44 are released by using an unshielded post treatment by removing the insulating material between the plates 42 and the material. This release is conveniently achieved by using standard 31 200426559 CMOS process steps, which define this wiring pad hole. By providing a wiring pad window around the MEMS variable capacitor diode structure, the device can be exposed if it cannot be adapted. Additional etch may be required to release the structure, but this etch can be achieved without using other mask 5 steps, because this wiring pad etch has defined a mask window for further etching. The top plate 42 includes etched holes 43 to facilitate the release of the top plate 42. Secondly, 'removing the substrate 46 under the variable capacitor diode 40 through the back side of the backside' can minimize parasitic losses, and therefore strengthen the adjustment of this range to approach the theoretical limit of 50% for a given design . If the substrate 46 10 is not removed, there is a large parasitic capacitance in parallel with the variable capacitance diode 40, and this adjustment range is severely degraded, as observed in previous studies. This step can be removed with the use of a high-sensitivity SOI substrate 48 because the parasitic capacitance is not severe. The use of the SOI substrate 48 is important for these manufacturing options. This intrinsically buried oxide (ie, BOX 50) is used as a silicon (si) backside etching 15 etch stopper, or as an insulator for a highly sensitive substrate 48. This technology cannot be implemented with a standard monolithic silicon substrate because there is no BOX 50. Finally, the variable capacitor diode 40 is designed with copper, so it has a much lower sheet resistance than the sheet with an inscribed sheet, which enhances the Q-factor. Copper-based variable capacitor diodes have not been reported in the conventional technology so far. 20 The variable capacitor diode 40 exhibits a rated capacitance set by the geometry of the variable capacitor diode and the gap Xa between the plates 42 and 44. By applying a positive DC voltage VDC across the plates 42 and 44, the movable top plate 54 will be offset by some distance due to the static electricity, so this capacitance can be adjusted. Therefore, this variable capacitor is described by the following relationship: 32 200426559 C = ε A / (xa «x) where ε is the dielectric constant of air, A is the overlapping area of the plates, and xa is between plates 42 and 44 The nominal distance and χ are some displacements forced by the DC adjustment voltage Vdc. It can be shown that the maximum displacement used for this design is xa / 3. If the maximum displacement exceeds 5, the electrostatic force exceeds the maximum mechanical recovery force, and the plates 42 and 44 are pulled together. In addition, it can be shown that the theoretical adjustment range for the variable capacitor diode 52 is less than 50%. The performance of the variable capacitor diode 40 depends on the material and the geometry of the device. In particular, the mechanical elasticity constant of the mechanical suspension network 45 will determine the adjustment of the voltage response. In addition, the device geometry determines the achievable capacitance. Now, please refer to Figs. 4b and 4c, which illustrate a second embodiment of the variable capacitor diode manufactured by the overall CMOS process shown generally at 52 in the present invention. This variable capacitor diode 52 includes a movable top plate 54 and a stationary bottom plate. The 56 ° top plate 54 is supported on the bottom plate 56 by a mechanical suspension network 58 and is fixed to the base plate 60 at a fixing member 62. In particular, this micro-electromechanical variable capacitor diode 52 has a parallel plate design similar to that in conventional branches. The variable capacitor diode 54 is constructed by mechanically suspending a metal top plate 54 in the air on a fixed metal bottom plate 65. This mechanical suspension network 58 provides support for the top plate 54 as shown. This variable capacitor diode 52 exhibits a rated capacitance, which is set by the gap xa between the structure of the variable capacitor diode and the plates 54 and 56. With the positive DC voltage (D0 voltage vDC) across the plates 54 and 56, the movable top plate 54 can adjust the capacitance due to the electrostatic force that can be offset by some distance x. Therefore, this variable capacitor is composed of 33 200426559 The following relationship is explained: C = ε A / (xa-x) where ε is the dielectric coefficient of air, A is the nuclear smash # Ao's overlapping area, xa is the rated distance between plates 5 54 and 65 'and X is some displacement forced by 0 (: adjusting voltage vdc. It can be shown that the maximum displacement for this design structure is ^ 'If this maximum displacement is exceeded, the power exceeds the maximum mechanical recovery force, and the plates 54 and 56 are pulled at Together. In addition, it can be shown that the theoretical adjustment range for the variable capacitor diode 俨 52 can be less than 50%. The performance of the variable valley-pole 52 depends on its material and the geometry of the device. In particular, the mechanical elastic constant associated with the mechanical suspension network 58 will determine the voltage response adjustment. In addition, the device geometry determines the achievable capacitance. The variable generator 52 is designed to achieve a nominal capacitance close to 0.25Pf And responds to voltages from 0 to 1.2V A summary of the design parameters of these devices is shown in Table 4. 15 Table 4 Design parameters of MEMS variable capacitor diodes Design parameter values Rated capacitance (C) 0.26pF Layout structure Parallel plate overlap area (A) 1024 " it? Distance (da) 34.5nm Relative permittivity (ε r) -1 Support beam length 8.5 β m Support beam width 3 // m Support beam height 2 μ m Device material ΑΪ Adjustment voltage 0-1.2V Adjustment range (theory) 50% estimated figure of merit (at 2GHz) 60 34 200426559 As can be understood, the above parameters only describe one very specific embodiment. However, those familiar with this technology understand: how to adjust these parameters to affect the circuit 'and to The instructions of the present invention make it easy to design other circuits such as those described herein. 5 Please refer to FIG. 5a for a description which is in accordance with the previous description and the manufacturing process of the variable capacitor diodes 40 and 52. ^-SOI CMOS The first embodiment of the suspension inductor 64 manufactured in the manufacturing process. In particular, the inductor 64 and its supporting fixtures are defined by the standard SOI CMOS manufacturing process. The inductor coil 64 is circular and hollow. This means that the coil of the spiral 10 suspect line does not completely enter the center of the circle, because it is known that the hollow inductor exhibits a better quality factor Q, and the internal coil contributes little to the overall inductance. It can be square or octagonal to meet the requirements of the CMOS process. The inductor coil 64 can be suspended in a metal layer, and in addition, as shown at 66, the substrate under the inductor can be removed. 15 Therefore, due to the eddy current The parasitic loss to the substrate 68 caused by the (eddy current) is minimized, the sheet resistance of this device is low, and a high Q · factor can be obtained. As in the case of the variable capacitor diodes 40 and 52, if a high-resistance SOI substrate including the BOX 70 is used, the backside etching step can be omitted. Referring now to FIG. 5b, this second embodiment illustrates a suspension inductor manufactured in a monolithic CMOS 20 process, which is typically shown as 72. The inductor 72 can be square, round, or octagonal to meet the requirements of the CMOS process. The inductor 72 and its fixture 74 are defined by a standard monolithic CMOS process, and its definition does not require additional manufacturing steps. The inductor 72 is connected to the MEMS variable capacitor diode 52 shown in Figs. 4b and 4c. 35 200426559 is connected. The inductor 72 is also made by a standard CMOS process, and a fixing member 74 defined by the standard process is suspended on the substrate. The 'I' electrical material is removed around the inductor to increase the figure of merit. Removing this dielectric can reduce the capacitive coupling between the inductor 72 and the substrate 76, and thus can reduce the energy loss caused by the eddy current induced in the substrate 76. The inductor 72 is finally made in a durable and thick metal layer to avoid losses due to series resistance. This inductor 72 may also include a patterned ground shield 'to reduce losses due to eddy currents. This ground shield can also be defined by a standard CMOS process. 10 The geometry of this device determines its performance. With simple mode, the inductance can be estimated from the following relationship: L = 37.5 // nV / (22r-14a) where a is the average radius of the spiral and ^ is the spiral coil The number of turns, # is the permeability of the core, and r is the radius of the spiral coil. 15 This inductor 72 is designed to maximize the Q-factor and achieve a nominal inductance close to 10nH. A summary of the inductor design parameters is shown in Table 4: Table 5 ... MEMS inductor design parameters_design parameter values ...-- j fixed inductance (C) 10nH __layout structure square hollow core — interesting for magnetic permeability (A) -1 to one revolution (η) 6 average radius (a) 92.5 β m. __Radius ⑴ 125 β m --- core core radius 76.25 β m ---- height 2 // m width 8 # m. ..........__ Coil space 1.5 β m ...__ Device material Al ..... Estimation _ Speech 1 ^ Prime factor (at 2GHz) 20 36 200426559 Now refer to Figure 6 It shows that the MEMS variable capacitor diode and the inductor are arranged in parallel to form an adjustable LC energy storage device or reference for the oscillator. So far, no previous research has shown that in a single-capacity process, a single MEMS variable capacitor and inductor are connected together to achieve a high-Q energy storage device. This energy storage device is mainly an inductor and a capacitor in parallel with a parasitic loss element represented by a resistor r. This energy storage device shows high-Q performance compared to low-〇 performance. The connected energy storage device provides a response that surrounds the center around a resonance frequency called the energy storage device. When this oscillator is constructed, this form of performance is desirable because it seeks a stable frequency output. The circuit design layout of this first embodiment has two main components. The first is: the illustrated low-noise and low-power oscillator cores are as described in Figure 7a; the second is: the support circuit which implements the square wave digital clock output, as shown in Figure 8a. 15 The layout of the oscillator core design shown in Figure 9 has the following characteristics. First of all, this design layout is well known to provide a reduction of unstable noise in the residual noise of CMOS devices. It is the main source of phase noise due to its upward conversion around the frequency. This is achieved as shown by the nature of this double average structure. This structure is symmetrical up and down and left and right. This tail current source 20 is the main source of unstable noise. Therefore, this circuit is implemented as a series current source, which minimizes the noise injected from the common mode point by increasing the common mode rejection ratio. It has been shown in previous studies that the rejection of unstable noise can be reduced by using a common mode capacitor section. In addition, this tail current is sourced by the Pmos device via 37 200426559, which is known in typical CMOS technology to show considerably less unstable noise than the same nMOS device. Moreover, for example, the conductivity of such a complementary structure is twice that of a complete * nMOS or a full pMOS structure. This higher conductivity allows to start at lower power. Finally, this structure 5 is compatible with the previously described MEMS LC energy storage device. Some key features of this LC energy storage device that belong to this design layout are: the use of bypass capacitors 80 and MOS resistors 82, through which the input voltage can be adjusted and controlled. This bypass capacitor 80 blocks the DC adjustment voltage on the top plate 42 of a pair of parallel variable capacitor diodes 40. This MOS resistor 10-82 is a high-impedance device that allows an adjustment voltage to be applied to the variable-capacitance diode 40. Without this device, the inductor 64 would resonate with the bypass capacitor 80. Finally, the cross-connect device is biased at or near the weak inversion structure to maximize gain and minimize power consumption and noise contribution from the active device. The following is a summary of the characteristics of the combination of bureaus and departments used in this design: I5 • Double-balanced structure for symmetry, reduction of unstable hybrids, and low power initiation; • Series tail current for unstable noise rejection; Common mode capacitor 84 for unstable noise rejection; • pMOS tail current to minimize unstable noise rejection; 2 • Compatible with MEMS LC-energy storage devices; and • Weak inversion at or near The active device is used to minimize power and noise.

FIG. 7b illustrates a double-balanced cross-connected negative resistance CMOS MEMS LC oscillator having unstable noise reduction in the second embodiment of the present invention. The design of Figure 25 7b provides a negative resistance of -2 / gm to the previously described second embodiment of the 2004 2004559 energy storage device circuit, and therefore removes losses in the energy storage device. The resonator includes a pair of variable capacitor diodes 52, an inductor 72, a MOS resistor 88, and a common mode capacitor 84, much like the embodiment of Figure 7a. This bypass capacitor 86 isolates the variable capacitor diode adjustment voltage from the rest of the circuit. This design is completed to achieve a circuit gain of at least 5 'with a phase shift of zero degrees' in order to meet the Barkhaussen start criteria with sufficient margin. As can be appreciated, the circuit of Figure 7b can be built with a variety of different parameters. As discussed earlier, this phase noise density can be reduced not only by an increase in Q of 10, but also by a decrease in circuit noise factor F. The most important contribution to phase noise and instability in CMOS electronic devices is device instability noise. In particular, the low-frequency device from the bias current source is unstable and modulated, and it is up-converted around the fundamental frequency of the oscillator. This improved technique reduces the up-conversion of unstable noise from this source and effectively improves the noise factor of the striker. Especially consider this design layout and bias point in order to reduce the noise factor of this circuit. The factors to be considered include the following: • Symmetrical design layout 20 Select a double-balanced structure to increase the waveform symmetry in the output signal, so reducing the possibility that the leading edge and the trailing edge are not the same : Unstable signal from the tail current source is up-converted and attenuated. • Stabilized common mode point design and layout The stability of the T common mode point can reduce the mismatch of the injection error energy device. The bypass capacitor 86 is connected across the tail current device to stabilize the total 39 200426559 same mode point. • Optimal Bias Set the quiescent current to allow this energy storage device to maintain voltage on the edges of the current limiting structure. Different from the voltage limiting structure in this structure, it can reduce the up conversion of unstable noise. • PMOS bias PMOS devices typically show unstable noise density, which is 10dB less than NMOS devices of the same size. This can be attributed to the buried via operation of PMOS devices in a typical CMOS process. 10 • Weak inversion Previous studies have shown that unstable noise is reduced in weak inversion. By biasing the tail current source in weak inversion, this effect can improve the performance of phase noise. Fig. 7c illustrates a third embodiment of the present invention. The barrier capacitor of the embodiment of Figs. 7a and 15b is not needed here because the adjustment voltage for the MEMS variable capacitor diode (ie, 52 ') is applied to a common node, which is variable by the MEMS The capacitor diode structure itself is isolated from the sustain circuit. The oscillator includes an inductor 72 'and a common mode capacitor 87'. As shown by the '(pdme) symbol: variable capacitor diode 52', inductor 72 ', and 20 capacitor 87', and variable capacitor diode 52, inductor 72, and The capacitors 87 have the same or similar structure. The oscillator core of Fig. 8a generates a differential sine signal, which is accessed across this energy storage device. In order to convert this signal into a clock or square wave digital signal, this micro 40 200426559 sub-signal is converted into a single terminal signal, as shown in Figure 8a. Then, the D-flip-flop is controlled by this signal clock, which connects its complementary output back to the D input. From here, the clock can be arbitrarily divided to achieve any output frequency. This is a benefit related to the present invention, since the division of the clock improves the performance of the phase noise 5. In order to clarify its significance, this high-performance performance oscillator is designed at a relatively high frequency, and each time its frequency is divided, its phase noise performance is improved. This is the exact opposite of the recent drive in this field, where the South Performance Clock is generated at a very low frequency and the phase noise performance is degraded by doubling its frequency to the operating frequency. Regarding the frequency stabilization in the previous method 10, there is a substantial system advantage. Phase and frequency are related by a linear operator, and in particular the frequency is the time differential of the phase shown by the following formula: ω = d 0 / dt

And ω is the strong resonance frequency, (^ is the phase and [is the time. Consider the ideal voltage output of the independent 15 oscillator v0 (t) as a function of time. This signal can be mathematically shown as follows: V〇COS (cjt) where ω is the basic strong frequency and VG is the rated voltage amplitude. The output of this same oscillator under the influence of noise sources can be described by the following formula: 20 v〇 (t) = v〇c〇 s where ⑴ must be a zero-average random process. 0 (t) represents the phase noise of the oscillator. If this signal is divided by its integer N, this signal becomes: V〇 (T) =: V〇c〇S (wt / N + (/) (t) / N) where the narrowband FM approximation is used 'this phase noise power is reduced by N2 41 200426559 times. Conversely, if the output of the oscillator is multiplied by the integer N, this output The signal is represented by the following formula: V〇 (T) = V〇cos (N ω t + N 0 (t)) and this phase noise power is increased by N2. Obviously, the method of the present invention provides in 5 cumulative phase noise Substantially reduced, so the stability of the frequency is enhanced. Finally, the Q output of the flip-flop is buffered, and at this time the pulse drives any load. Figure 8b illustrates the complete clock reference circuit of the second embodiment. At this time, the pulse oscillator provides a differential output signal that drives a single-to-differential conversion amplifier with a gain of 1. Then, a series of flip-flops convert the signal Divided into appropriate 10 frequencies. Table 6 provides a summary of the performance parameters for the circuit of Figure 8b. Table 6 Summary of performance parameters for the low-stability monolithic CM0S-MEMS clock reference CM0S-MEMS clock reference Design parameter value processing technology TSMC0.18 // m mixed mode power line (Idd) 1.8V power dissipation (Min / Max) 3.8mW / 4.1mW voltage output level (high / low) 1.8V / 0V -90% voltage Rise / fall time 69ps / 48ps Duty cycle (high / low) 44/56 Cycle beat (1GHz) 8.5fs Density (at 600kS ^ " Fif -130dBc / Hz Full range (2 times) 125MHz-lGhz Full range 0.15% 42 200426559 The micro-electromechanical LC element of this second embodiment needs to be modified with standard MiM capacitors and inductors. This variable capacitor diode 52 needs to be added: a mechanical support network 58 and a worm hole in the top plate 54 to Convenient release of this structure. Made of passivation cutting. This manufacturing technology allows for a maskless 5 post-process which completely releases the structure by simple wet chemical etching if necessary. However, this structure is almost completely cut by purification Released as part of the standard CMOS process. This developed manufacturing technology may include the following steps, as explained with reference to Figures 9a-9d. In each of Figures 9a-9d, the phantom dielectric layers 91, 9210, 93, and 94 are illustrated. Also illustrated are the metal layers 95, 96, and 97. For example, the through holes of the through holes 98 connect the metal layers 95, 96, and 97. Also shown are: a suspension portion 100 and a fixing portion 99 of the MEMS device formed on the substrate 90. An active CMOS device 102 is also formed on the substrate 90.

First, the MEMS variable capacitor diode (40 or 15 52 in Figures 4a and 4b) and the MEMS inductor (64 or 72 in Figures 5a and 5b) are in a standard CMOS process by the MiM layer , Or two flat metal wiring layers, and vias connecting these layers. In Fig. 9a, the process for three metal connection layers 95, 96 and 97 is shown in its entirety. Therefore, no additional mask is required to define this structure.

20 As shown in Figure 9b, this MEMS device is exposed by cutting through a standard CMOS pad. The first and selective mask (which is selective: if a high-resistance SOI substrate is used as previously described, or if the substrate is a monolithic substrate) is used to etch the silicon substrate from the back side (Figures 4a and 5a) 48 or 68), and stop at the box (50 or 70 in Figures 4a and 5a) 43 200426559 around each device. The removed substrate is shown in Figure 9c. Finally, if this wiring pad is cut without releasing these clothes, the variable capacitor diode (40 or 52 in Figures 4a and 4b) and the inductor (64 or 64 in Figures 5a and 5b) 72) Removal of surrounding dielectric material. This step illustrated in Figure 9d releases the variable capacitor diode plate (42 and 44 in Figure 4a or 54 and 56 in Figure 4c) and the inductor (Figures 5a and 5b) 64 or 72) of the suspension.

The following summarizes the main concepts mentioned in the manufacturing process: • Structural metals as defined in the standard monolithic or SOCICMOS process; • Post-treatment with release etching; and • Post-treatment with selective back engraving . A reduced manufacturing flow chart is shown in Figures 9a-9d, referring to the chemical etch shown in Table 7.

Illustrated steps Figure 9a Figure 9b Layer Process Mask

MiM or wiring Dielectric deposition Etching

Details Standard CMOS Standard CMOS

Figure 9c Figure 9d Not shown

Si-Ilandle Dielectric Insect Carved Dry I Insect Carved H1

SF6, C4F8, DRIE HF / H2S04, H202, H2o wet strength C02 44 200426559 The clock generator circuit produced by this unit provides time basis, which has low phase noise and consumes low power and can be adjusted , And provide digital clock output. It is suitable for a variety of applications, including but not limited to: clocks for embedded microcontrollers and microprocessors. In summary, the present invention provides a number of unique benefits, including but not limited to the following: • Highly stable monolithic CMOS clock generation circuit, which does not require external components and is implemented with a high QMEMSLC energy storage device; 0. By Use standard CMOS processing layer and unmasked post-processing to achieve standard commercial CMOS-compatible MEMSLC energy storage devices; Top-down frequency generation, which provides stability comparable to bottom-to-5 frequency generation of bottom-up; • The cost for clock generation is greatly reduced; • The The power generated by the clock is greatly reduced; • The number of pins is reduced and therefore the packaging cost for microcontrollers and micro-processing benefits; ○ • Since the Risen pulses are discrete components on the chip rather than in individual packages 'And can greatly reduce the overall size of this embedded system; • Increased reliability due to single-piece integration rather than circuit board level integration; and • Wide adjustment range (continuous Discrete). 45 2〇〇 ^ 26559 According to the present invention, a clock generating circuit or a time base can be integrated on a chip. This signal is required in all synchronous integrated circuit applications. Figure 10 illustrates the application of the present invention to integrated circuits. The clock generator 104 is formed as part of an integrated circuit, such as a microprocessor, microcontroller, or other synchronization device 106. A synchronous semiconductor device 106 is formed on a substrate and includes various electronic subsystems. A package 10S for a semiconductor device 10 is provided. In other words, the clock generation circuit can be a single-piece component of a complete integrated circuit, and can be manufactured together with the electronic components it supports on a common substrate. Although the embodiments of the present invention have been described above, it is not intended to describe and illustrate all possible forms of the present invention. Rather, the words used in the description are intended to be illustrative, and not restrictive, and various changes may be made without departing from the spirit and scope of the invention. 15 For example, the above discussion discusses the point of view of the present invention, but those familiar with the present invention can easily understand the present invention. 3 The MEMS device can be implemented in a standard CMOS process. The invention is a single type. Many advantages, such as: [Structure without having to make this drawing simple] In addition, the present invention has a variety of uses in specific applications, such as PDA, cellular phone, portable computer, desktop computer and so on. Top view of the outline of the diode. Figure 1 is a conventional micro-electromechanical variable capacitor.

Side view; 46 200426559 Figure 3 is a schematic side view of another variable capacitor diode of conventional technology; Figure 4a is a perspective section of a variable capacitor diode constructed according to the first embodiment of the present invention Fig. 4b is a schematic perspective view of a variable capacitor two 5-pole body constructed according to the second embodiment of the present invention; Fig. 4c is a line 4c-4c of the second embodiment of the conventional technology along the line 4c in Fig. 4b Partial side sectional view of the line; Figure 5a is a perspective sectional view of a variable inductor constructed according to the first embodiment of the present invention; 10 Figure 5b is a variable constructed according to the second embodiment of the present invention A perspective sectional view of an inductor; FIG. 6 is a schematic circuit diagram of an energy storage device according to the present invention; FIG. 7a is a schematic circuit diagram of an oscillator core according to the first embodiment of the present invention; Figure 7c is a schematic circuit diagram of the oscillator core of the third embodiment of the present invention; Figure 8a is a schematic circuit diagram of the oscillator structure of the first embodiment of the present invention; Figure 8b is the present invention Overview of the single sCMOS-MEMS clock reference circuit of the second embodiment The circuit diagrams are shown in Figure 1. Figure 1 is a schematic perspective view, a simplified manufacturing flowchart collectively provided in a standard monolithic or SOICMOS process used in the present invention; and Figure 10 is a single substrate of the present invention. A perspective view of a synchronous semiconductor device 'This device includes multiple electronic subsystems and a package for the device. 47 200426559 [Representative symbols for the main components of the formula] 40… variable capacitor diode 80 " capacitor 42 ... parallel plate 82 " resistor 43 ··· etched hole 84 " capacitor 44 ... parallel plate 86 " bypass capacitor 45 ... support arm 87 " capacitor 46 ... substrate 87, · • capacitor 48 ... substrate 88 " resistor 50 ... embedded oxide 90 " substrate 52 ... variable capacitor diode 91 " phantom dielectric layer 52 '·· 可Variable capacitor diode 92 " phantom dielectric layer 54 ... top plate 93 " phantom dielectric layer 56 ... bottom plate 94 " phantom dielectric layer 58 ... mechanical suspension network 95. metal layer 60 ... substrate 96 " metal layer 62 ... fixed 97 " metal layer 64 ... inductor 98 " through-hole 66 ... substrate 99 ·· fixed part 68 ... substrate 100 •• suspension part 70… buried oxide 102 •• active CMOS device 72… inductor 104 •• Clock generator 72 '... Inductor 106 • Semiconductor device 74… Fixture 108 • Package 76… Substrate 48

Claims (1)

200426559 Patent application scope: 1. A MEMS clock generator circuit is used to generate a highly stable digital output signal without external components. This circuit includes: a substrate; 5 an oscillator on a substrate and includes a high-Q MEMS LC The energy storage device is used to generate a periodic signal; and a first circuit also made on the substrate is used to convert the periodic signal into a high-frequency digital output signal. 2. For example, the MEMS-type clock generation circuit of the first patent application range, where 10 the periodic signal is a sine wave and has the original frequency, and wherein the output signal is a square wave signal whose frequency is one and a half of the original frequency, and where This circuit also includes a second circuit also made on the substrate, which is used to divide the frequency of this square wave digital output signal into at least one desired lower application frequency, thus reducing the phase noise of this signal and enhancing it. Stable 15 sex. 3. For example, the MEMS-type clock generating circuit of the second patent application range, wherein the first and second circuits and the oscillator are manufactured on the substrate by a CMOS compatible process. 4. For example, the MEMS-type clock generation circuit of the first patent application range, in which 20 the oscillator and the first circuit are made on the substrate by a CMOS compatible process. 5. For example, the MEMS-type clock generation circuit in the patent application No. 4 wherein the CMOS compatible process is a monolithic or SOI CMOS process. 6. For example, the MEMS-type clock generation circuit in the second item of the patent application, where 20042004559 the sinusoidal periodic signal is a differential signal, and the circuit of Dan Yi converts this sinusoidal differential signal into a sinusoidal single-ended signal. 7. If the MEMS-type clock generation circuit in the sixth item of the patent application, the first circuit in the basin converts a red-string single-ended chirp into a square-wave digital output signal whose frequency is half of the original frequency. 8. The MEMS-type clock generating circuit according to item 2 of the patent application scope, wherein the second circuit includes at least one positive and negative cry connected to the _ circuit for dividing the frequency of the square wave digital output signal into at least Think ^ lower application frequency. "10 9. As described in the scope of patent application, the simplified clock generator circuit, where the substrate is a monolithic or SOI substrate. 10. A MEMS-type oscillator circuit is used to generate low-noise high-frequency periodic signals This oscillator circuit includes a substrate; 15 aCM_ high-Q MEMS LC energy storage device made on the substrate; and a circuit made on the substrate in a CMOS-compatible process and connected to the LC storage. It can be installed to generate a periodic signal. 11. The oscillator circuit of item 10 in the scope of patent application, in which the frequency is variable in response to the control input to adjust the oscillator circuit. Oscillator circuit, where the CMOS compatible process is a monolithic or soICM0s process. 13. If the oscillator circuit of the patent application item 10, wherein the oscillator circuit is a double-balanced oscillator circuit Reduce the up-conversion of unstable 50 noise. See the patent application scope of the __ oscillator circuit, where the LC energy storage device includes at least one micro-electromechanical variable capacitor diode, which has a change in response to control input Electricity B. If the oscillator circuit according to item 14 of the patent application scope, wherein the at least one variable capacitor diode includes a top plate, and wherein the electric circuit includes a bypass capacitor to block the control input from the rest of the circuit The share t is transmitted to the top plate. 77 From the exhaustion circuit of the patent application scope item 14, among which § This oscillation circuit is a double-balanced crossover oscillator circuit to reduce the up-conversion of unstable noise. 17 · —kind 2MemsslC energy storage device with high quality factor, the device includes: a substrate; at least one micro-electromechanical variable capacitor diode made on the substrate by a CMOS compatible process; and connected to at least one variable capacitor diode MEMS inductors are also fabricated on the substrate using a CMOS-compatible process. 18. For example, a MEMS-type LC energy storage device with a scope of patent application of item 17, wherein the at least one variable capacitor diode has a variable capacitor. In order to provide the adjustment range for this device. 19 · If the patent application scope of the 17th mEmS type LC energy storage device, where the inductor is suspended on the substrate, and in this CMOS compatible system Released during or upon completion. 51 200426559 20 · If the MEMS-type LC energy storage device under the scope of the patent application No. 17 in which the inductor is hollow. 21 · If the MEMS-type LC energy storage device under the scope of the patent application No. 17, The inductor 5 is suspended on the substrate by the fixing member defined by the CMOS compatible manufacturing process. 22. The MEMS-type LC energy storage device according to item 17 of the patent application scope, wherein the at least one variable capacitor diode It has a fixed bottom plate and a movable top plate suspended from the bottom plate, and is released during or upon completion of this CMOS compatible process. 10 23 · The MEMS-type LC energy storage device according to item 22 of the patent application scope, wherein the top plate is shifted according to the control input to adjust the capacitance of the at least one variable capacitance diode. 24. For example, the MEMS-type LC energy storage device under the scope of application for patent No. 22, wherein the top plate is suspended on the bottom plate by a mechanical suspension network defined by a CMOS-compatible manufacturing process. 25. The MEMS-type LC energy storage device according to item 17 of the application, wherein the at least one variable capacitance diode and the capacitor are defined by a conductive layer in the CMOS-compatible process. 26. The MEMS-type LC energy storage device according to item 25 of the application, wherein 20 of which the conductive layer is a metal layer. 27. The MEMS-type LC energy storage device according to item 17 of the patent application scope, wherein the CMOS compatible process is a monolithic or SOI CMOS process. 28. For example, the MEMS-type LC energy storage device under the scope of application for patent No. 22, wherein the top plate has a plurality of etched holes to facilitate the release of the top plate during or upon completion of the CMOS-compatible manufacturing process. 29. The MEMS-type LC energy storage device according to item 17 of the application, wherein the substrate is a monolithic substrate or an SOI substrate. 30. The MEMS-type LC energy storage device according to item 17 of the patent application scope, of which 5 this device has a resonance frequency. 31. The MEMS-type LC energy storage device according to item 17 of the application, wherein the at least one variable capacitance diode and capacitor are defined by a MiM layer or two horizontal metal wiring layers. 32 · MEMS type clock 10 generating circuit for generating a highly stable digital output signal, the circuit includes: an oscillator made on a first substrate and including a high-Q MEMS LC energy storage device for generating periodicity Signals; and a first circuit also formed on the second substrate for converting a periodic signal into a high-frequency digital output signal. 15% · The MEMS-type clock generation circuit according to item 32 of the patent application, wherein the first and second substrates are different. 34. The MEMS-type clock generating circuit according to item 32 of the application, wherein the first and second substrates are the same, so that the clock generating circuit is a monolithic circuit. 2035 · —A computer system including: a data bus; a central processing unit bidirectionally connected to the data bus; a temporary memory bidirectionally connected to the data bus; a persistent memory bidirectionally connected to the data bus; and 53 r200426559 MEMS-type clock generation circuit is used to generate highly stable digital output signals suitable for use in this computer system. The clock generation circuit includes: an oscillator fabricated on the first substrate and includes a high-Q MEMS LC 5 The energy storage device is used to generate a periodic signal; and a first circuit also made on the second substrate is used to convert the periodic signal into a high-frequency digital output signal. 54