TW200425607A - Multi-phase buck converter with programmable phase selection - Google Patents

Abstract

A buck converter is provided for providing an output voltage to a load, the output voltage being produced from an input voltage in accordance with a desired voltage. The buck converter includes an output capacitor, the output voltage being provided by the output capacitor; a plurality of output switch arrangements having respective output inductors coupled to the output capacitor, the switch arrangements being controllable to provide respective phase output currents to the output capacitor through the respective output inductors; a plurality of phase output arrangements respectively coupled to the output switch arrangements, the phase output arrangements being controllable to set the respective phase output currents supplied by the output switch arrangements, each of the phase output arrangements being operable to shutdown the respective output switch arrangement if a signal representing an output current of the buck converter falls below a respective programmable threshold signal; and a phase control arrangement configured to control the phase output arrangements to set the respective phase output currents supplied by the output switch arrangements so that the output voltage approximates the desired voltage.

Description

说明 Description of the invention: [Technical field to which the invention belongs] Related applications This application is based on the application of US Patent Application No. 5/60/443210 filed on January 28, 2003, and the title is Multi-Phase with Programmable Phase Selection Converter, the entire contents of which are incorporated herein by reference. FIELD OF THE INVENTION The present invention relates to buck converters, such as multi-phase buck converters used in low voltage / high current applications. [Background of the Invention] Various applications may provide a conventional DC-to-DC buck converter that accepts a DC input voltage and generates a lower DC output voltage to drive at least one set of circuit components. Buck converters are typically used in low voltage applications that require a high amount of load 15 currents (for example, 30 amps or more). Generally, as shown in FIG. 19, a set of single-phase step-down converters 1900 includes a set of high-side switches 1905, a set of low-side switches 1910 connected to the high-side switch at a switching node 1915, and a set of An output inductor 1920 connected to the switching node 1915 and a set of output capacitors 1925 connected to the output inductor 1920. In operation, the high-side and low-side switches 1905, 1910 are controlled by a control circuit 1930 to generate the output voltage required to cross the load 1935. For this purpose, the high-side switch 1905 is initially turned on, while the low-side switch 1910 remains powered off. This results in a set of voltage drops of approximately (V1N-VOUT) across the output inductor 1920, which causes a set of currents to build up in the output inductor. At a subsequent time 5 200425607, the high-side switch 1905 is turned off, and the low-side switch 19m is turned on. Because the current obtained through the switch 1910 within the inductor 1920 cannot be changed immediately, the current continues to flow through the output inductor 1920, thus charging the output capacitor 1925 and causing 5 liters across the voltage (νουτ) across the output capacitor 1925. In this way, the high-side and low-side switches 1905, 1910 can be appropriately switched at the appropriate time until the voltage (V0UT) across the output capacitor i 925 is at the desired output voltage, which is generally lower than the input voltage . Once the required output voltage is reached, the high-side and low-side switches 1905, 1910 can be controlled on a periodic basis, so the output inductor 1920 provides an amount of current equal to the current demand of the load 1935 connected across the output capacitor 1925. By providing a current demand of no more and no less than the load 1935, the voltage (Vout) across the output capacitor 1925 remains at least approximately fixed at the desired output voltage. It is also conventional to provide a set of multi-phase DC-to-DC buck converters 15 2000, which include a plurality of interleaved output phases 2005a, 2005b, 2005c ..... 2005n, as shown in FIG. 20. As shown in Figure 20, each output phase 2005a, 2005b, 2005c ..... 2005η is assigned a separate switching configuration, which includes a set of high-side switches, a set of low-side switches, and a set of output inductors. In operation, the control circuit 2010 periodically operates the output phases 2005a, 2005b, 2005c, ..., 2005n in a time delay sequence. By operating the output phases 2005a, 2005b, 2005c, ..., 2005η with a phase delay sequence, the conventional multi-phase buck converter 2000 allocates a plurality of output phases 2005a, 2005b, 2005c, ..., 2005η The current output 'thus distributes heat generation and reduces the need for the output capacitor 1925 200425607, so that a smaller output capacitor 125 can be used. However, because the conventional multi-phase buck converter requires a fixed number of point-to-point connections between the control circuit 2010 and the output phases 2005a, 2005b, 2005c, ..., 2005η, the conventional multi-phase buck converter does not provide A robust structure that can easily expand capabilities to include any number of phases required. Furthermore, conventional multi-phase buck converters cannot respond to the requirement to reduce the required output voltage or the requirement to reduce the load's 1935 current to optimally control the output voltage. Because the output voltage cannot be optimally controlled, the conventional multi-phase buck converter may generate unwanted voltage surges, which may damage the circuit connected to the output of the buck converter. Summary of the invention; 1 Summary of the invention • and a set of phase control configuration communication One object of the present invention is to provide a multi-phase buck converter which overcomes the disadvantages of the aforementioned prior art buck converter. To achieve this, the present invention 15 provides a multi-phase buck converter for generating a set of output voltages to a load. The output voltage is generated from an input voltage according to a required voltage. The converter includes a set of output capacitors. The output voltage is provided by the output capacitor; most output switch configurations have separate output inductors coupled to the output capacitors, and these switch configurations are controllable to provide output to the output via 20 separate output inductors. The respective phase output currents of the capacitors; a plurality of phase output configurations are respectively coupled to the output switch configurations, and the phase output configurations are controllable to set the phase output currents respectively supplied using the output switch configurations, one The group phase control bus communication ground is coupled to each phase output configuration 7 2204256, and is coupled to the phase control bus. The phase control configuration is configured to control the phase output configuration and set to use the output switch configuration respectively. The supplied phase output current, so the output voltage is close to or adjusted to the required Pressure, wherein the phase control arrangement and the phase output configuration is provided as a separate integrated circuits 5, and the phase control arrangement is configured to control via the phase control bus and the phase output configuration. Utilizing the functions of separate phase control configuration and phase output configuration, the multi-phase buck converter example according to the present invention does not contain unused or redundant silicon because the buck converter can only contain those phase 10 outputs required for a specific application Number of configurations. Therefore, if a design engineer requires, for example, a set of three-phase step-down converters for a specific application, the engineer can design a multi-phase step-down converter to include only three sets of phase output configurations, each of which is assigned to a separate set of three phase outputs A group that. Furthermore, the phase control bus (e.g., a set of 5-wire analog buses) allows the multi-phase buck converter of the present invention to communicate with a possible unlimited number of phase output configurations without the need for Point-to-point electrical connection between phase output configurations. In this way, the multi-phase buck converter allows effective and easy adjustment of the scaled phase structure. According to another implementation example of the present invention, a multi-phase buck converter has a set of phase error detection configurations. If a phase-out configuration cannot provide a set of phase output currents to match the average inductor current of the phase output configuration, it is State to generate a set of phase error signals. In this way, the phase control configuration is provided with a set of signals for detecting a defective phase and, if Kumida of Shida does not activate the defective phase and / or activate a backup phase output configuration. 8 200425607 According to another example of the present invention, each output phase configuration responds to a lower required output requirement (vDES) or a requirement to reduce load current, which operates to cut off the high-side and low-side switches. In this way, the twist rate of the inductor is increased 'which increases the response time of the multi-phase buck converter of the present invention and prevents 5 negative negative currents from flowing through the output inductor and may damage the power supply. According to another embodiment of the present invention, each output phase configuration includes a set of current sense amplifiers, a set of resistors Ecs electrically connected between the positive input of the current sense amplifier and an output inductor node, and a set of current sense amplifiers. A capacitor 10 Ccs which is electrically connected between the positive and negative inputs of the amplifier. The output inductor is also connected to the negative input of the current sense amplifier. 0 The resistor Rcs and the capacitor Ccs are connected across the output inductor node and flow through The current of the output inductor 220 can use the selection resistor Rcs * capacitor Ccs, so that the time constant of the resistor Rcs and the capacitor Ccs is equal to 15 the output inductor 220 and its DC resistance (ie, the sensing coefficient L / inductor DCR, where DCR is the time constant of the inductor's DC resistance) and the voltage across the capacitor is sensed. In this way, this embodiment of the invention allows each output phase configuration to sense the current provided to the load in a non-destructive manner (i.e., without disturbing the current provided to the load). 20 According to another example of the present invention, the phase control configuration includes a drop circuit configured to reduce the output voltage in proportion to the load current demand. In this way, this embodiment example allows an efficient and really simple way to adaptively modify the output voltage via adaptive voltage localization. According to another embodiment of the present invention, the phase output of each multi-phase buck converter 9 200425607 configuration can be programmed to turn off the high-side and Low-side switch. In this regard, the number of phase output configurations selected for a particular design may depend on the need to meet thermal requirements and / or minimize the number of input and wheel-out capacitors at maximum output current. However, when the buck converter output current is less than the maximum output current, if fewer phase output configurations are used, the efficiency will increase. When the output current decreases, the phase output configuration is cut off. The efficiency is increased by 10 to eliminate gate charging losses, MOSFET switching losses, and high- and low-side switches and the current circulating in the output inductors of each phase output configuration. Each unique circuit design can sequentially cut off the phase output configuration at a specific output current level to achieve maximum efficiency over the entire output current range. Brief Description of the Drawings Figure 1 is a block diagram of an example of a buck converter according to the present invention. 15 Figure 2 is a block diagram of an output switch configuration according to the present invention. Figure 3 is a block diagram showing the detailed phase control configuration of Figure 1. Fig. 4 is a reaction diagram showing an example of a step-down converter according to the present invention in response to a reduction in the load stage. Figure 5 is a block diagram showing the detailed phase timing configuration of Figure 3. 20 Figure 6 is a block diagram showing the detailed PWM configuration of Figure 3. Fig. 7 is a block diagram showing a variation of the PWM configuration example of Fig. 6, which is configured to reduce the output voltage in proportion to the increase in load current. Fig. 8 is a block diagram showing another example of a phase control configuration according to the present invention. 10 200425607 Figure 9a is a graph showing a continuous charging cycle example for an output switch configuration. Figure 9b is a graph showing output switch configuration control in response to lower required output requirements. 5 FIG. 10 is a block diagram of a phase output configuration example according to the present invention. FIG. 11 is a block diagram of a start time configuration example according to the present invention. Fig. 12a is a graph showing an example of a phase timing signal according to the present invention. Fig. 12b is a graph showing the phase timing signal of Fig. 12a shifted by the setpoint voltage value. 10 Figure 12c is a graph showing the output of a phase time comparator. Figure 12d is a phase timing graph showing eight sets of phases for a set of triangular phase timing signals. Fig. 12e is a block diagram showing another example of start time configuration according to the present invention. 15 FIG. 13 is a block diagram showing an example of continuous charging configuration according to the present invention. Fig. 14 is a block diagram showing an example of a ramp wave generator according to the present invention. FIG. 15 is a block diagram showing an example of a current sensing configuration according to the present invention. Fig. 16 is a block diagram showing an example of a phase output configuration made as a discrete integrated circuit according to the present invention. 20 Figure 17 is a block diagram showing the connections between a set of phase control arrangements and a plurality of phase output arrangements according to the present invention. Fig. 18 is a block diagram showing an example of an over-temperature detection circuit according to the present invention. Figure 19 is a block diagram showing the 11 200425607 of a single phase buck converter according to the prior art. Figure 2020 shows a block diagram of a multi-phase buck converter according to the prior art. Figure 21 is a block diagram of a phase output configuration using a phase shutdown circuit according to the present invention. Fig. 22 is a block diagram of an example of a converter output current detection configuration according to the present invention. [Implementing the cold type] Detailed description of the preferred embodiment 10 Next, referring to FIG. 1, a first example of the multi-phase buck converter 100 according to the present invention can be seen. The step-down converter 100 includes a phase control configuration 105 electrically and communicatively coupled to the input bus 130, and electrically and communicatively coupled to the phase control via a phase control bus 115 (e.g., a 5 wire analog bus). The phase output configurations 110a, ii〇b, ii〇e, ... 15 of the configuration 105 are electrically and communicatively coupled to the input voltage (vIN) output switch configurations 120a, 120b, 120c, ..., 120η and phase Output configurations ii〇a, 110b, 110c ..... ll〇n, a set of output capacitors 125 are electrically coupled to the output switch configurations 120a, 120b, 120c ..... 120η for generating an output voltage (V 〇ut) 'and a set of loads 135 are electrically connected between the output voltage 20V (ground) and ground. The multiphase buck converter 100 shown in the example in Figure 1 can be used, for example, in applications that require small size, design flexibility, various low voltage outputs, high currents, and rapid transient response, and the buck converter 1 〇〇 can include one or more sets of output phases, for example, three sets of phases, each of which can use phase input 12 200425607 output configuration 110a, 1 l0b, 1 loc, ..., no Was made. The control configuration 105 includes a circuit that is configured to control the phase output configurations 110a, 110b, 110e ..... ll〇n by communicating a phase control signal via the phase control bus 115, and therefore the phase output configurations 110a, ii Ob, 110c 5 ..... 110n generate an output voltage (v0UT) according to a set of required output voltage variables (VDES), which can be provided to the control configuration 105 via the input bus 130. Each phase output configuration 11 〇a, 11 〇b, 11 〇c, ..., 11 On contains circuits' which are configured in response to the use of a control configuration 105 to control the phase control signals communicated through the phase control bus 10 rows 115 115 respectively The output switch configuration is 120a, 120b, 120c ..... 120η. For this purpose, the phase output configurations 110a, 110b, 110c, ..., 110n operate to control the respective switch configurations 120a, 120b, 120c, ..., 120η and generate the output according to the required output voltage variable (VDES) Voltage (V0UT). 15 Referring next to Figure 2, an example of an output switch configuration 120η according to the present invention can be seen. The output switch configuration 120n includes a set of high-side switches 205 and a set of low-side switches 210 (e.g., transistor switches, FET switches, FET rectifiers, etc.) electrically connected to each other via an inductor node 215. The input voltage (VIN) is electrically connected to the high-side switch 205 and the ground voltage is electrically connected 20 to the low-side switch 21o. An output voltage (νουτ) is generated on the output node side 220a of the output inductor 220, which is also electrically connected to the switching node 215 at the same time. In operation, the high-side and low-side switches 205, 210 of the switch configuration 120η are controlled by the phase output configuration 110η to generate the required output voltage (νουτ) on the output node side 220a of the output inductor 22o. For this purpose, the high-side switch 205 13 200425607 is initially turned on, while the low-side switch 210 remains powered off. This results in a set of approximately (Vin-Vout) voltage drops' across the output inductor 220, which results in a set of currents built into the output inductor. At a sequential time, the high-side switch 205 is turned off, and the low-side switch 210 is turned on. Because the current in the inductor 220 cannot be changed immediately, the current continues to flow through the output inductor 220, thereby charging the output capacitor 125 and causing the voltage drop across the output capacitor 125 to rise. In this way, the high-side and low-side switches 205, 210 can be appropriately controlled and switched at appropriate times until the voltage 10 drop across the output capacitor 125 is equal to the required output voltage (VDES). Once the required output voltage (VDES) is reached, the high-side and low-side switches 205, 2 can be controlled periodically. Thus the output inductor 220 provides a load equal to the load 135 connected across the output capacitor 125 The amount of current required by the current. With a current requirement that provides no more and no less than the load 135, the voltage drop (v⑼) 15 across the output capacitor 125 remains approximately fixed at the desired output voltage (VDES). According to the above embodiment example of the present invention, the output phase configuration 11n controls the high-side and low-side switches 205 and 21 when a periodic charging cycle is continued. The cycle duration may be characterized by a specified phase delay, period Sexual start time and charging continue. Referring next to the known figure, it can be seen that one of the output switch configurations 20 to 120n has a periodic charging cycle lasting 900, which includes a phase L delayed of 905, a periodic start time 91 (), and a charging continual offense. As shown in Fig.%, The w-side switch 205 is turned on at the periodic start time 91 °, and remains on when the charging continues for 915, and is turned off when the charging continues to end. After the charging continues for 915, the high side The switch keeps the power off for the rest of the periodic charge 14 ^ 9 for 9GG. In normal operation, the low-side switch is trained so that the low-side switch 210 is turned on when the 咼 -side switch is turned off, and vice versa. In this way, the output inductor 22 establishes a current when charging continues for 915 and releases at least a portion of the current after the charging continues for 915 and for the remaining periodic charging 5 cycles for 900. By controlling the high-side and low-side switches 205 and 21 in the manner described above, the amount of current established in the output inductor 220 can be controlled by changing the charging duration 915 with respect to the periodic charging cycle duration 900. For example, if the charging duration of 915 is equal to the periodic charging cycle lasting half of 900 (that is, 50% duty cycle), then the switch configuration 120η will provide the output with half of the 100 maximum current of the buck converter Capacitor 125. Or, for example, if the charging duration 915 is equal to the periodic charging cycle lasting 900 (ie, 100% duty cycle) 'then the switch configuration 12 0 η will provide the maximum current of the buck converter 1000 Output capacitor 125. 15 During normal operation, the low-side switch 210 and the high-side switch 205 are controlled in a dichotomy. Also, when the high-side switch 205 is turned on, the low-side switch 210 is powered off, and vice versa. In this way, one of the high-side and low-side switches 205, 210 is turned on at all times. However, in response to certain operating conditions, the two sets of switches 205, 210 may be turned off. 20 Therefore, according to another exemplary embodiment of the present invention, in response to the occurrence of one of the two sets of unique operating conditions, the output phase is configured with 11 On operation to cut off both the high-side and low-side switches 205, 210. : Lower required output (VDES) requirement or reduced current demand of load 135 (ie, reduced load level). 15 200425607 The lower required output requirement (vDES) may cause the negative inductor current to flow through the output inductor 220. The negative current converts the buck converter 100 into a boost converter by transferring energy from the output capacitor 125 to the input voltage (Vrn). This energy can damage the power supply (not shown) and / or other components, can cause the voltage control loop to become unstable, and can result in wasted energy. As shown in Figure 9b, in response to the requirement to reduce the required output voltage (VDES), to prevent negative inductor current generation, both the high-side and low-side switches 205, 210 are turned off. In this manner, the 10 current established in the output inductor 220 is discharged through the load 135 instead of being supplied through the power source. When a current is discharged through the load 135, the output voltage (VOUT) across the output capacitor 125 decreases. Once the output voltage (VOUT) drops to approximately the lower required output voltage (VDES), negative current is no longer important, and the high-side and low-side switches 205, 210 can be operated in a normal manner. 15 When the current demand of the load 135 decreases (ie, the load stage decreases), the high-side and low-side switches 205, 210 should be controlled to reduce the current supplied to the output capacitor 125 by the output inductor 220. However, in the conventional buck converter, the minimum time required to reduce the current (ie, a set of current transients) in the output inductor 220 in response to a decrease in the load stage is processed according to the following equation: 20 ⑴ Tslew = [LX (Imax-Imin)] / V〇ut ^ where the high-side and low-side switches 205, 210 are made as FET rectifiers. Therefore, when the load current demand is reduced, the current transient of the inductor 25 of the buck converter output 25 (ie, the built-in current between the output inductor 16 and 200425607 when the load stage is reduced) will cause the output capacitor 125 voltage rise. Although the current demand of the load 135 will eventually discharge the excess charge of the output capacitor 125, a short continuous voltage surge on the output voltage (VOUT) may damage the sensitive circuit connected to the buck converter 100. 10 But according to the example of the embodiment of the present invention, the output phase configuration 110n reduces the current demand of the load 135 (ie, a load stage decreases), and it operates to cut off both the high-side and low-side switches 205 and 210 (That is, individual power failure). In this way, the twist rate of the output inductor 220 (i.e., the rate at which the current can be reduced) can be significantly increased, with the high-side and low-side switches 210 being made as FET rectifiers. By cutting off the high-side and low-side switches 205, 210, the switching node voltage is forced to decrease until the individual diodes of the FET rectifier are turned on. This increases the voltage across the inductor from vOUT to νουτ + the voltage across the individual poles (ie, VbodY DIODE). Therefore, the twist rate of the output inductor 220 is reduced according to the following equation: 15 ⑺

Tslew [LX (Imax-Imin)] / (V〇ut + Vb〇DY DIODE) Therefore, according to this example of the present invention, when compared to the prior art, it is built into the output inductor 220 when the load level is reduced. The current transient 20 < is discharged more quickly, resulting in fewer claimed voltage surges, as shown in FIG. 4. In fact, because the voltage drop across an individual diode can be higher than the output voltage νουΊΓ, the inductor current twist rate can be increased by two or more. Referring next to Fig. 10, it is shown that the high 17 side and low side switches 105, 110 of the output switch configuration 120η are controlled in the manner described above in accordance with the example of the phase output configuration 25 110η of the present invention. The phase output configuration Hon includes a start time configuration 1005, a charging continuous configuration 1010, a current sensing configuration 1015 electrically coupled to the charging continuous configuration 1010, an SR lock electrically coupled to the starting time configuration 1005, and a charging continuous configuration 1010. Device 1020, and electrically connected to the SR lock 1020 and the charging continuous configuration 1010 and the brake 1025. The start time configuration 1005 includes circuitry configured to determine the periodic start time 910 and phase delay 905 shown in Figure 9a. For this purpose, the start time configuration 1005 powers down the low-side switch 21o at the beginning of receiving the phase timing signal 1030 from the phase control configuration 105. Phase Date Order # 1030 may contain, for example, a periodic analog signal having a period equal to a periodic charging period lasting 900 (eg, a periodic sawtooth waveform, a periodic sine curve waveform, a periodic triangle waveform, etc.) . Using the periodic analog signal 1030, the start time configuration 105 can determine the periodic start time 910 and the phase delay 905, and generate a set of periodic clock waves 1035 at the periodic start 15 time 910. The clock pulse wave 1035 sets sR to lock it, causing the high-side ON_5 to turn on and the charging continues to 915. The charging continues to be configured 1 〇1 〇 Contains the circuit continued 9 1 5 'and in the mine-free animal chain Q 1 ς' its group State to determine charge holding

The PWM control signal 104 may include, a transition (PWM) control signal 1040. For example, a set of analog signals has a value that is proportional to the difference between the required output voltage (VDES) and the actual output voltage (V0UT). Using the PWM control signal 1040, the charging continuous configuration 1010 appropriately determines the charging duration 915 for the high-side and low-side switches 205, 210. Furthermore, the charging duration configuration 1010 is configured to modify the charging duration 915 according to the amount of current supplied from the output 5 inductor 22 to the output capacitor 125. For this purpose, the charging continuous configuration 1010 receives a set of current difference signals 1050 from the current sensing configuration 1015, which is characterized by the current supplied by the output inductor 220 relative to the current supplied by all output switches Configurations 120a, 120b, 120c, ..., 120η provide 10 quantities of average current 1045, so if the output inductor 220 is used to supply a smaller amount of current than all output switch configurations 120a, 120b, 120c, ... , 120η is provided with an average current of 1045, then the charging continuous configuration 1010 can increase the charging duration 915. By increasing the charging duration 915, the output inductor 220 supplies more current to the output capacitor 125. After the charging continues for 915 sessions, the charging 15 continues to configure the reset S-R locker 1020, which continues for 900 for the rest of the periodic charging cycle causing the south-side switch 205 to be turned off and the low-side switch 21 to be turned on. In response to a reduced required output (VDES) or reduced load current demand (ie, reduced load level), it can be determined from the PWM control signal 1040 communicated using the phase-controlled 20-configuration 105 The 1010 operation is continuously configured to turn off the high-side and low-side switches 205, 210. For this purpose, the charging continues to configure 1010 to reset the S-R locker 1020 and transmit a set of logic "0" to the AND gate 1025, thus causing the high-side and low-side switches 205, 21 to be powered off. 19 200425607 The S-R locker 1020 is reset preferentially, allowing all phase output configurations 110a, 110b, 110c, ..., il0n to reach zero duty cycles within tens of nanoseconds. The continuity is gated by the clock pulse and responds to the increase in load level. The phases can overlap and reach a duty cycle of 100%. In this way, this method of controlling the phase output configuration 110a, 110b, 110c, ..., 110η provides a "single-cycle transient response" in which the output inductor 220 current changes in response to a load transient within a single switching cycle. This maximizes the effectiveness of the power train and minimizes the need for the output capacitor 125.

The current sense configuration 1015 includes a circuit configured to modify the charge based on the average current 1045 provided by all output switch configurations 120a, 120b, 120c, ..., 120η relative to 10 and the current flowing through the output inductor 220. The current difference signal of 915 is 1050.

Referring next to Fig. 11, there is shown an example of an arrangement of 15 times at the beginning 15 of the present invention for generating a clock wave 1035 based on the periodic start time 910 and the phase delay 905. The start time configuration 1005 includes a set of phase timing comparators 1105 and one of the outputs which is electrically connected to the phase timing comparator. The set of click pulse generators 1110. In this example, the phase timing signal 1030 is a periodic triangular waveform 1030, which has a period equal to a periodic charging period that lasts 900 and an amplitude that varies between 0 volts and 5 volts, as shown in Figure 20 12a. Referring next to Fig. 12b, it is a timing diagram showing the output of the phase timing comparator 1105 and the single-shot pulse generator 1110. As shown in Fig. 12b, the output of the phase timing comparator 1105 is equal to the phase timing signal 1030 offset by a fixed setpoint voltage 1115. Therefore, when the periodic charging cycle continues at a time equal to 20 of the phase delay 905, the output of the lawful comparator 1105 crosses zero in the positive direction, the voltage axis one, thus causing the click pulse generator 1110 to generate the clock pulse 1 Them 5. With a properly selected setpoint voltage of 1115 between 0 and 5 volts, clicking on the pulse wave to generate nmo can be controlled to generate a clock pulse wave at any time when the on-duty phase cycle lasts 900 hours, half 90 hours Satoshi. In order to cause the click pulse to generate $ 111Q to continuously delete the second half temple to generate the pulse 1 () 35 in this periodic phase period, the input to the phase timing ratio ㈣⑽5 can be switched so that the phase sequence is changed. The negative input is provided to the phase timing comparator 1105 and the set point voltage 1115 is provided to the phase timing ratio

10 The positive loser of the comparator 1105. In this way, the output of phase timing comparator ιι5 and single-shot pulse wave H111G is similar to the timing diagram shown in Figure 12e. Therefore, according to the present invention, each phase output configuration 11〇a, u〇b, u〇c

, ..., 110η can be assigned a unique phase delay 905 and periodic start time 91 when the periodic phase period lasts 900, without the need for phase control configuration 105 and phase output configuration 11 (^, n〇b Point-to-point electrical connections between, 11〇c ..... n〇n. Furthermore, if the phase output configuration 110a, 110b, 110c ..... 1 l0n will use separate phase products 20 body circuits are made. If both inputs of the phase timing comparator H05 are electrically connected to the input pins of the phase integration circuit, they are used for each phase output configuration 110a, 110b, 110c, ..., ιΐ〇 A particularly effective and simple designation of one of the phase delay 905 and the periodic start time 910 of η can be formed. Next, referring to FIG. 12d, it shows that there are eight phase output configurations 110a, 110b, 110c, ..., Time chart of the 100-step buck converter 100 example 21 200425607 of the single-click pulse wave generator output.

Referring next to Fig. 12e, it is shown the start time configuration 105 which is made as an example of the phase output configuration 110n of the phase 1C 1250 separately and differently. As shown in Figure 12e, phase 1C includes electrical contact pins 1255a and 1255b which are input to the phase sequence comparator 1105 when electrically connected to the phase, respectively. A set of voltage dividers is provided between the reference voltage 1270 and ground. The voltage divider contains resistors 1265a and 1265b connected to each other at node 1260. By appropriately selecting the resistors 1265a and 1265b, a predetermined set-point voltage in5 can be supplied to the phase timing comparator 1105 via the electrical contact pin 1255b. 10 Next, reference is made to FIG. 13, which shows an example of a charging continuous configuration 1010 according to the present invention. The charging continuous configuration 1010 includes a charging continuous amplifier 1305, an individual power failure detection amplifier 1315, a fractional multiplier 1320 electrically connected to the negative input of the individual power failure detection amplifier 1315, and an electrical input coupled to the negative input of the charge continuous amplifier 1305 and The fractional multiplier 1320 produces a ramp generator 1510 of the ramp wave.

At the start time, 1005 is configured to generate the clock wave 1035 to set the time before the SR lock 1020. The inverting output 1020a of the SR lock 1020 breaks the logic high level. "The ramp generator 1310 is continuously configured at 1010 during charging. Place on the line. This causes the ramp generator 1310 to generate a fixed original output voltage on the ramp output line 1325 (the fixed original voltage is also provided on the original fixed voltage output line 1330 for a long time). After the start time configuration 1005 sets the SR latch 1020, the high-side switch 205 is turned on and the inverting output 1020a of the SR latch 1020 determines a set of logic low levels "0" above the reset line of the ramp generator 1310, resulting in The voltage on the ramp output line 1325 jumps from the output voltage of the original 22 200425607. The charging continuous amplifier 1305 compares the ramp wave output line 1325 with the PWM control signal 1040. In this example of the present invention, it is proportional to the difference between the required output voltage (VDES) and the actual output voltage (v〇UT). (VDES-VOUT) A set of analog voltage signals. Once the voltage on the ramp output line 5 1325 reaches the voltage level of the PWM control signal 1040, the charging continuous amplifier 1305 causes the SR latch 1020 to reset, which causes the high-side switch 205 to be turned off and the SR latch 1020's inverted output i 〇2〇a Determine the logic high level π1 " above the reset line of the ramp generator 1310 and reset the ramp output line 1325 to the original predetermined voltage. 10 In this way, the charging duration 915 represents the time between when the start time is configured to generate a clock wave 1035 of 105 and the ramp generator 1310 ramp output line 1325 is equal to the PWM control signal 1040 voltage level. . Therefore, the larger the deviation between the actual output voltage (v0UT) and the required output voltage (Vdes), the larger the voltage level of the Beam PWM control signal 1040, and therefore the larger the charging duration 15 915. Furthermore, the charging duration configuration 1010 can modify the charging duration 915 according to the amount of current supplied from the output inductor 220 to the output capacitor 125. For this purpose, the current supplied by the ramp generator 1310 from the description output inductor 22〇 is relative to the average current 1045 provided by all output switch configurations 12a, 120b, 120c, ... 20, 120n. The current sensing configuration 1015 receives a set of current difference signals 1050. For example, the current difference signal 1050 can provide a composition ratio between the current supplied by the output inductor and the average current supplied by all output switch configurations 12a, i20b, 120c ... 120n. The difference between the voltage values. Using the current difference signal 1050, the ramp wave 23 200425607 generator 1310 can change the rate of voltage jump on the output line 1325, so when the current supplied by the output inductor and all output switches are configured 120a, 120b, 120c When the difference between the average currents supplied by ..., 120n increases, the rate of the voltage jump on the ramp output line 1325 decreases. 5 Therefore, if the amount of current supplied by the output inductor 220 is smaller than the average current 1045 provided by all output switch configurations 120a, 120b, 120c, ..., 120η, the reduced voltage jump rate at the ramp output line 1325 will be As a result, the charging duration 915 increases, which causes the output inductor 220 to supply more current to the output capacitor 125. 10 Charging continuous configuration 1010 is also configured to cut off the high-side and low-side switches in response to a lower required output requirement (VDES) or a reduction in the current demand of the load 135 (ie, 'reduction in load level') 2 〇5, 210 both. To this end, the fractional multiplier 1320 generates a ramp multiple of the original voltage of the generator 1310 (e.g., 90%), and supplies the fractional multiple of the original voltage to a 15-body power-off detection amplifier 1315. The individual power-off detection amplifier π 15 compares the original voltage of the fractional multiple with the voltage level of the PWM control signal 1040 (ie, 'proportionally the voltage level of VDES_V0UT) and if the pwM control signal 1040 voltage level drops to A signal is generated below the fractional multiple of the predetermined voltage to turn off the high-side and low-side switches 205, 210. 20 It should be understood that various conditions can cause the individual power-down detection amplifier 1315 to turn off the high-side and low-side switches 205, 210. For example, a sudden decrease in the demand current of the load 135 that can cause V0UT to increase relative to vDES can cause the voltage level of the PWM control signal 1040 to fall below the fractional multiple of the original voltage. Additionally, for example, in response to the requirement of less required output voltage (VDES) 24 200425607, the phase control configuration 105 may force the PWM control signal 1040 to be below the original multiple of this fractional multiple, as explained more fully below. Referring next to Fig. 14, an example of a ramp wave generator 1310 according to the present invention is shown. The ramp generator 1310 includes a set of clamp circuits 1405 and a set of programmable current sources 1410 electrically connected to a ramp output line 1325. The clamping circuit 1405 includes a set of operational amplifiers 1415 and a set of clamping diodes 1420. When the driving input 1415a of the operational amplifier 1415 is determined, the two operate together to force the ramp output line 1325 to a predetermined voltage. The ramp generator 1310 also contains a set of phase error detection amplifiers 10 1450, electrically connected to the phase error detection amplifier 145 and a fractional multiplier 1455 of the original voltage, and electrically connected to the phase error detection amplifier 1450 output Switch 1460, if the phase output configuration 120η cannot provide enough current to match the average current 1045 provided by the output switch configurations 120a, 120b, 120c, ..., 120η, all of them operate together to generate a group of phase error signals 1465 . Using the phase error signal 1465, the buck converter 100 may not activate the damaged phase output configuration 120η and / or activate a supporting phase output configuration 120η. At the start time, 1005 is configured to generate the clock wave 1035 to set the time before the S_R locker 1020. The inverting output 1020a of the SR locker 1020 determines the logic high level Π1Π above the reset line of the ramp generator 1310. The clamp circuit 1405 is activated, so the voltage on the ramp output line 1325 is clamped to the original voltage. After the start time configuration 1005 sets the SR latch 1020, the high-side switch 205 is turned on and the inverting output 1020a of the SR latch 1020 determines that a set of logic low levels are above the reset line of the ramp generator 1310, which clamps 25 200425607 Circuit 1405 failed. When the clamp circuit i405 is not activated, the 'slope wave capacitor 1425 receives the current from the V1N via the slope resistor 1430, which causes the voltage of the slope wave generator 1310 ramp wave output line 1325 to jump. Once the voltage of the output line 1325 reaches the voltage level of the PWM control signal 1040, charging the continuous amplifier 5 1305 causes the SR latch 1020 to reset, which causes the high-side switch 205 to be turned off and the SR latch 102 to the opposite The phase output i02a determines a set of logic high levels " Γ above the reset line of the ramp generator 1310, thus causing the clamp circuit 1405 to force the output line 1325 to the original voltage. According to the output inductor 220, the current difference signal 1050 generated by the current sensing configuration 1015 is used to control the programmable current source 1410 to supply the current amount to the output capacitor 125, and the ramp wave generator 1310 ramp wave output The voltage jump time on line 1325 can be modified. For this purpose, the current source 1410 can be controlled to reduce some current from the ramp output line 1325, which is proportional to the current supplied at the output inductor 220 and all the output switches 15 are configured with 120a, 12b, 12b. c, ..., the difference between the average currents supplied by 120η. By removing (ie, drawing) the current from the ramp output line 1325, the ramp capacitor 1425 charges more slowly, thereby causing the voltage on the ramp output line 1325 to jump at a lower rate. By charging the ramp capacitor 1425 20 from VIN via the ramp resistor 1430, the ramp rate of the voltage at the ramp output line 1325 will automatically compensate for changes in the input voltage VIN, which may, for example, be due to the output voltage of the power supply (Not shown), or due to a voltage drop in a brushed circuit board (PCB) that changes relative to the load current. Furthermore, according to another exemplary embodiment of the present invention, the required output voltage 26200425607 (VDES) is used as the original voltage of the ramp generator 1310. Because the required output voltage (VDES) is a set of relatively stable voltage levels generated from the d / A converter inside the phase control configuration 105, the required output voltage (VDES) is not in a different phase output configuration ll〇a, u〇b, u〇c, ..., ιιη 5 fluctuate. In this way, the difference in the ground or input voltage of the phase output configurations 110a, ii0b, 110c, ..., 110n slightly or does not affect the ramp voltage output of the ramp generator 1310 because the output The voltage of line 1325 is referenced to the desired output voltage (VDES). If the phase output configuration 120η is damaged or inactive, the current supplied by the output 10 inductor 220 can drop to a level where the current source 1410 draws current more quickly than the ramp capacitor 1425 charges. In this case, the voltage of the ramp output signal 1325 can start to fall, which causes the phase error detection amplifier 1450 to trigger the switch 1460 and generate a phase error signal, which can be used to not cause the damaged phase output configuration 120η and / or Initiate 15-backup phase output configuration 120η. Referring next to Fig. 15, an example of a current sensing configuration 1015 according to the present invention is shown. The current sensing configuration 1015 includes a circuit configured to generate a current between the current supplied by the output inductor 220 and the average current supplied by all output switch configurations 120a, 120b, 120c ... 120n. 20 difference one group of current difference signal 1050. To this end, the current-sensing configuration 1015 includes a set of inductor current-sensing configurations 1505 that are configured to generate an inductor current signal 1510 that is proportional to the amount of current flowing through the output inductor 220. The inductor current sense configuration 1505 includes a set of current sense amplifiers 1515, a set of resistors Rcs electrically connected between the positive sense of the current sense amplifier 1515, and a 200425607 input and output inductor node 215, and electrically connected to the current A set of capacitors C cs between the positive and negative inputs of the sense amplifier 1515 and the inductor node 22 0a are also connected to the negative input of the current sense amplifier 1515. 5 Use resistors across nodes 215, 220a across the output inductor 220

Res and capacitor Ccs, the current flowing through the output inductor 220 can be sensed according to the following equation ... (3) Vc (s) = VL (s) x [1 / (1 + sRCsCcs)] 10 = iL (s) x [(Rl + sL) / (1 + sRCsCcs)] Select the resistor Res and capacitor Ccs so that the time constant of the resistor Res and capacitor Ccs is equal to the time constant of the output inductor 220 (ie, the inductance L / inductance DCR), the voltage across the capacitor Ccs is proportional to the current through the output inductor 220, and the inductor current sense configuration 1505 can be processed as if only a set of sense resistors with RL values were used. The time constant inconsistency does not affect the measurement of the DC current of the inductor, but affects the AC component of the current flowing through the output inductor 220. Sensing the current flowing through the output inductor 220 may be advantageous relative to the high side and / or low 20 side, because the actual output current delivered to the load 135 may be obtained instead of a peak or sampled value of the switching current. Therefore, the output voltage (VOUT) can be placed according to the time information to fit a load line. In this way, the current detection circuit according to the present invention can favorably support a single-cycle transient response. The 25 current sense amplifier 1515 can be designed with a variable gain that decreases with temperature 28 200425607, and a set of nominal gains, for example, 35 at 25 ° C and 31 at 125 ° C. This gain-temperature dependence can compensate for the increase in ppm / degrees (Celsius) in the DCR of the output inductor 220. The current sense amplifier 1515 communicates the current difference signal 1510 to the current 5 comparator 1520, which compares the current signal 1510 of all phases with the average inductor current 1045 to generate a current difference signal for communication to the charging continuous configuration 1010. 1050. A current average resistor 1525 is provided between the current signal 1510 and the average inductor current signal 1045. Because each phase output configuration 110a, 110b, 110c, ..., 110η provides a set of similar current average resistors between their respective current signals and 10 average inductor current signals 1045, the average inductor current signal 1045 has a set of The voltage is proportional to the average value of the respective current signals of the phase output configurations 110a, 110b, 110c, ..., 110n. Referring next to Fig. 16 ', an example of a phase output configuration 15 lOn and an output switch configuration 120n according to the present invention is shown. As shown in Figure 16, similar components are marked with the same symbols as used in Figures 10 to 15. In addition, the example of phase output configuration 11o in Fig. 16 provides a set of total configuration 1605, which is used to add the required output voltage (VDES) level to the sensed current signal, so the original ramp voltage can be Set to the desired output voltage (VDES) level. 2〇 Next, referring to FIG. 3, which shows an example of the multi-phase buck converter in FIG. 1, wherein the phase control configuration 105 includes a set of phase timing configurations 3 05 and a set of pulse width modulation (PWM) configurations 310, It is used to generate a phase timing signal 1030 and a PWM control signal 1040 via a phase control bus 115 (eg, a 5-metal wire analog bus), respectively. The phase control configuration 05 also includes 29, which is used to generate another control signal 330, including another circuit configuration 325, which is not required for understanding the present invention. Phase timing signal 1030 contains information

The phase sequence example No. 1030 includes a set of periodic voltage waveforms, and is then configured by the phase output in the manner described above, uOb, 110a, 110b, 110, ..., 11Λ 丄110c,..., 110. 10 Please refer to section 5® for an example of the phase timing configuration 3005 that generates a periodic phase timing ## 1030 according to this chapter. The phase timing configuration 305 includes a set of programmable seismic device configurations 505 that are electrically coupled to a periodic waveform generator 510, such as a periodic triangular waveform generator 51. The periodic triangle waveform generator 510 is configured to generate a phase timing signal 1030 according to the frequency of the configurable oscillator 505 configuration 505, which may be changed using the frequency selection input 515 of the input bus 130 or, in addition, may be used a Group external frequency selection resistors (not shown) are planned. In this way, the frequency of the tremor configuration 505 can be planned and therefore, the frequency of the periodic phase timing signal 1030 can be set to any desired frequency, for example, a frequency in the range of 20 100KΗζ to 1MHz. Referring again to FIG. 3, the PWM configuration 310 of the phase control configuration 105 is configured to generate a PWM control signal 1040, which contains information and / or data to allow the phase output configuration 110a, 110b, 110c, .... 110n decision Each of these switch configurations 110a, 110b, 110c,..., Lln is a group of high-side switches 30 200425607 205 and one group is turned on for 915. As described above, the longer the V-pass duration 915 for the high-side switch 205 is, the more current flows through the output inductor 220 " iL configured through the respective switches. In this manner, the switch on-duration 915 can be dynamically controlled to compensate for changes in load current, transient load conditions, and / or changes in the required output voltage variable (VDES). Referring next to Fig. 6, an example of a ^^^ configuration 310 for generating a pwM control number 1040 according to the present invention is shown. As shown in Figure 6,? \\ / 1 ^ 1 configuration 310 includes a set of digital-to-analog converters (daC) 605, which are configured to generate the required output voltage variable 10 (Vdes) 610 from the digital input 615 of the input bus 13. The high-gain error amplifier 620 compares the required output voltage variable (Vdes) 610 with the actual output voltage (VOUT) and generates a set of error signals 625, which are proportional to the required output voltage variable (Vdes) 61 and the actual The difference between the output voltage (V0UT). The error signal 625 can be communicated to the phase control bus 115 as the PWM control signal 1040. 15 Because the PWM configuration 310 of FIG. 6 generates a set of PWM control signals 320 'which are proportional to the difference between the required output voltage variable (VDES) 610 and the actual output voltage (Vout), the PWM control signal 326 It can be used by phase output configurations 110a, 110b, 110c ..... lln to maintain the actual output voltage (VOUT) of the required output voltage (Vdes). In this way, the PWM configuration 310 20 and the phase output configurations ii〇a, ii〇b, lloc .... lln form a turn-off to control the actual output voltage (V0UT) regardless of the load current change Circuit. For example, if the actual output voltage (V0UT) drops below the required output voltage (VDES) in response to an increase in load current, then the high side of the switch configuration 31 200425607 the turn-on of switch 205 continuously 915 can be proportional to the pwM control signal 1040 is increased, thereby causing the output inductor 220 of the switch configuration to supply more current to the output capacitor 125, which in turn causes the output voltage (VOUT) to rise. In addition, if the actual output voltage (ν〇υτ) rises above the required output voltage (VOUT) in response to a decrease in the load current, the conduction of the high-side switch 205 of the respective switch configuration can continue to be proportional to PWN The control signal 320 is reduced, thereby causing the output inductors 22 of the switch configurations to supply a smaller current to the output capacitor 125, which in turn causes the output voltage (νουτ) to decrease. The digital input 615 of the DAC 605 may include, for example, a plurality of voltage identification (VID) digital signals generated by an external circuit such as a mobile Intel Pentium IV microprocessor. A voltage identification (νπ) signal can be generated using a microprocessor to transmit a voltage operable by the processor core. In this way, the digital-to-analog converter (DAC) 605 of the PWM configuration 310 can generate the required output voltage variable (vDES) based on an appropriate 15 processor core voltage. In some cases, the requirement for a new required output voltage (Vms) can cause a change in digital input 615 (such as the 'VID input) during normal operation of the buck converter 1 () (). When the phase control configuration i 〇5 detects a change in the voltage-identification (complete) code, the phase control configuration 105 may, for example, make the signal disappear 20 for a period of time 'for example, 40 ns to ensure that it is detected. The change was not caused by skew or noise. In response to the requirement of higher required output voltage (Vdes), the high gain error amplifier 62o (via PWM control ㈣104) causes the phase output configuration 110a, 110b, 110c ... Charging continues to increase. In addition, 32 200425607 responds to the lower required output (vDES) requirements, and the high-gain error amplifier 620 causes the phase output configurations 110a, 110b, 110c, ..., lion to continue to decrease in charge. However, as mentioned above, the lower required output (VDES) requirement may disadvantageously cause a negative current flowing through the output inductor 220. 5 Therefore, according to another exemplary embodiment of the present invention, the phase control configuration 105 is

The configuration cuts off each output in response to the requirements of a lower required output (VDES) Switch configuration 120a, 120b, 120c, ..., 120η high-side and low-side switches 205, 210. For this purpose, the PWM configuration 310 may be provided with a set of step-down detection configurations 850, as shown in FIG. 10 step down detection configuration 85 0 detect a group of VID step down to prevent

Stop the aforementioned negative inductor current (i.e., the required negative inductor current in relation to the lower required voltage). To this end, the PWM configuration 310 includes a set of clamping circuit configurations 855, which are configured to clamp the output of the high gain error amplifier 82o to lower than each phase output configuration 110a, 110b, 110, ..., ιι 〇η 15 The voltage level of the ramp generator 1310. In this way, the use of the PWN control signal 1 040 generated by the PWM configuration 310 results in the charging of each phase output configuration 110a, 110b, 110c, ..., lln to be continuously configured 1010 to cut off the respective output switches. Configure the high-side and low-side switches 205, 210 of 120a, 120b, 120c, ..., 120η until the output voltage (νουτ) drops to an output voltage (VDES) which is lower than about 20. In some cases, adaptive voltage positioning may be required to reduce output voltage offset during load transients and reduce power consumption when load 135 obtains maximum current. For this purpose, the PWM configuration 310 may include a drop circuit that is configured to reduce the actual output voltage that is proportional to the increase in load current. 33 200425607 Voltage (ν〇υτ). Referring next to Fig. 7, an example different from the PWM configuration 310 shown in Fig. 6 is shown, which is configured to reduce the output voltage of 0,111, which is proportional to the increase in load current. As shown in Figure 7,? The example of the ~ ^ 1 configuration 310 further includes a drop circuit 700 including a set of current signal buffers electrically connected to the average inductor current signal 1045. In this example of the present invention, the average inductor current signal 1045 is referenced to the required output voltage variable (VDES), so the output of the current signal buffer 705 is equal to (VDES + IAVG), where Iavg is proportional to the output switch Configure the average current provided by the output inductor 220 of 120a, 120b, 120c 10,..., 120η. A drop resistor Rvdrp is provided between the output of the current signal buffer 705 and the negative input of the high gain error amplifier 620, and a set of offset resistors RFB is provided between the actual output voltage (VOUT) and the negative input of the high gain error amplifier 620 between. Therefore, the voltage (v) at the negative input terminal of the high-gain error amplifier 620 is obtained using the following equation: (4) V = (V〇es + Uvg) x [Rfb / (Rfb + Rvdrp)] + V0UT x [ Rvdrp / (Rfb + Rvdrp)] However, because the high-gain error amplifier 620 controls the voltage loop to maintain 20 equal to its positive and negative inputs, the high-gain error amplifier 620 operates to keep its negative input voltage specific to the required output voltage (Vdes ). Therefore, the actual voltage (V0UT) can be determined by the following equation: (5) (V〇ut) = (Vdes) -IAvg x (Rfb / Rvdrp) Therefore, the PWM configuration 310 example operation in Figure 6 is proportional to the output by 34 25 200425607 The average current provided by the output inductors 220a, 120b, 120c, ..., 120η of the switch configuration 120a, reduces the actual output voltage (V0UT). The positioning voltage (ν) can be planned by selecting an appropriate drop resistor Rvdrp, so the drop impedance produces the required converter output impedance. 5 Referring next to Figure 17, there is shown an example of a buck converter 100 made using discrete control and phase 1C. The step-down converter 100 example in Figure 17 includes a set of control 1C 1705, which contains all the functions of phase control configuration 105, and two-phase ICs 1250a, 1250b (see Figure 16), which includes phase output configuration 110a. , All functions of 110b. 10 Each control and phase IC 1705, 1250a, 1250b can include an over-temperature detection circuit 1805, as shown in Figure 18. The over-temperature detection circuit 1805 includes a VRHOT comparator 1810, a set of switches 1815 electrically connected to the output of the VRHOT comparator 1810, and a set of temperature-sensing configurations 1820 that are configured to use an external pin 1825 to produce a proportional to crystal The voltage of the circular temperature is 15 ℃, the temperature threshold can be used, for example, a component voltage regulator connected to VIN is set. If the wafer temperature rises above the temperature threshold, the VRHOT comparator 1810 turns on the switch Iδί5, which causes the VRHOT signal 183 to be generated. The VRHOT signal can be used, for example, to not trigger a phase or to trigger another phase to share the current load. 20 The number of phase output configurations 110a, 110b, 110c ..... 110n selected for a particular design may depend on the need to meet thermal requirements and / or minimize the number of input and output capacitors for maximum output current. However, when the output current of the buck converter 100 is smaller than the maximum output current, if the smaller phase output configuration 11a, ii0b, iioc, ..., 110η is adopted, the efficiency 35 200425607 rate will increase . When the output current decreases, cut off the phase output configuration 11 〇a,

110b, 110c, ..., 110n, because of eliminating the gate charge loss, MOSFET switching loss, and high-side and low-side switches 205, 21〇 and the output configuration of each phase 110a, 110b, 110c ..... 110n output The circulating current in the inductor increases the efficiency by 5 currents. Each unique circuit design can sequentially cut off the phase output configuration 110a, li0b, iioc, ..., iin at a specific output current level to achieve the maximum efficiency over the entire output current range. Referring next to Fig. 21, another embodiment of the present invention is shown, in which each phase output configuration 1 l0a, 110b, 110c, ..., 1 ιη is operable to a 10-phase multi-phase buck converter 100 The output current shuts off a specified set of phases. To this end, the phase output configuration 11 On includes a set of converter output current sensing configurations 2105, which are operable to generate a set of current signals representative of the multi-phase step-down converter current based on the average inductor current signal 1045 2135 'and a group of phase-closed comparators 2130 electrically coupled to the current signal 2135 and the threshold signal 15 2115. The phase output configuration 110n can be planned according to the specific application requirements by providing a specific threshold signal value of 2115. For example, in the example of the embodiment of Fig. 21, the threshold signal 2115 is provided by a pair of resistors 2120, 2125 coupled in series with each other between the reference voltage 1270 and the ground. In this manner 20, the threshold signal 2115 can be provided by using a simple set of suitable resistor values for the voltage divider. However, it should be understood that the threshold signal 2115 may be provided in another way, for example, using a digital-to-analog converter that is operable to convert the digital representation of the threshold signal 2115 required into a set of analog threshold signals 2115, It may be provided to a phase-off comparator 2130. 36 200425607 During operation, if the current signal 2135 falls below the threshold signal 2115, the phase shutdown comparator 2130 compares the current signal 2135 with the threshold signal 2115 and generates a set of phase shutdown signals 2130. The off signal 2130 causes the phase output configuration 110n to turn off both the high-side and low-side switches 205, 210 of the designated output switch configuration 12n 5 (eg, mSFET), which results in a multi-phase buck converter The output current is reduced. This in turn causes the output voltage of the multi-phase step-down converter to drop, thus causing the phase control configuration 1Q5 to be used as described above to increase the remaining phase output configurations 110a, 11〇b, 11 () e ...

110n-l duty cycle compensation. This compensation does not cause the average inductor 10 current signal 1045 to change, because this signal 1045 represents the output current of the buck converter 100 itself, and does not represent the respective phase output configuration noa, nob, 110c, ..., llon output current. Referring next to Figure 22, an example of a converter output detection configuration 2105 according to the present invention is shown. As shown in Figure 22, the converter output detection configuration 15 2105 includes a set of adder units 2205, which are electrically coupled to the average power

The sensor current signal is 1045 and reaches the required output voltage signal. In operation, the adder unit 2205 subtracts the required output voltage VDES from the average inductor current signal 1045 to generate the current signal 2135. It should be understood that although the phase shutdown circuit is as described above with the module phase 20-bit output configuration ll 〇a, U〇b, 11〇c, ..., 110η are described as examples of multi-phase step-down converters. The phase shutdown circuit can be used with a fixed number of phase output configurations or phases (for example, two-phase, three-phase , Four-phase, eight-phase) multi-phase buck converter. [Schematic description] 37 200425607 Figure 1 is a block diagram of an example of a buck converter according to the present invention. Figure 2 is a block diagram of an output switch configuration according to the present invention. Figure 3 is a block diagram showing the detailed phase control configuration of Figure 1. Fig. 4 is a reaction diagram showing an example of a step-down transformer according to the present invention in response to a reduction in the load stage. Figure 5 is a block diagram showing the detailed phase timing configuration of Figure 3. Figure 6 is a block diagram showing the detailed PWM configuration of Figure 3.

Fig. 7 is a block diagram showing a variation of the PWM configuration example of Fig. 6, which is configured to reduce the output voltage in proportion to the increase in load current. 10 Figure 8 is a block diagram showing another example of a phase control configuration according to the present invention. Figure 9a is a graph showing a continuous charging cycle duration example for an output switch configuration. Figure 9b is a diagram showing the configuration control of output switch 15 in response to a lower required output requirement.

FIG. 10 is a block diagram of a phase output configuration example according to the present invention. FIG. 11 is a block diagram of a start time configuration example according to the present invention. Fig. 12a is a graph showing an example of a phase timing signal according to the present invention. Figure 12b is a graph showing the sequence 20 signal when the phase of Figure 12a is shifted from the setpoint voltage value. Figure 12c is a graph showing the output of the phase time comparator. Figure 12d is a phase timing graph showing eight sets of phases for a set of triangular phase timing signals. Fig. 12e is a block diagram of a 20042004607 38 which shows another example of start time configuration according to the present invention. FIG. 13 is a block diagram showing an example of a continuous charging configuration according to the present invention. Fig. 14 is a block diagram showing an example of a ramp wave generator according to the present invention. FIG. 15 is a block diagram showing an example of a current sensing configuration according to the present invention. 5 FIG. 16 is a block diagram showing an example of a phase output configuration made as a discrete integrated circuit according to the present invention. Figure Π is a block diagram showing the connections between a set of phase control arrangements and a plurality of phase output arrangements according to the present invention. FIG. 18 is a block diagram showing an example of an over-temperature detection circuit according to the present invention. Fig. 19 is a diagram showing a single phase step-down converter according to the prior art. Fig. 20 is a block diagram showing a multi-phase step-down converter according to the prior art. Fig. 21 is a diagram of a phase-shutdown circuit according to the present invention. Block diagram. The block diagram of Figure 1 shows the layout of the eye wheel. Figure 2 shows the winding current of the converter according to the present invention. Example [Symbol table of the main components of the diagram] 100 ··· multi-phase buck converter 125 ··· wheel-out capacitors 110a-110n ... phase output configuration 135 ·· load 105 ··· phase control configuration 205 .. 115 ... Phase control bus 210 · · · Low-side switch l20a-120n ... Output switch configuration 215 ··· Switch node 39 200425607 220 ··· Output inductor 220a ·· Output node side 305 ··· Phase timing configuration 310 ... Pulse width modulation (PWM) configuration 315 ... Circuit configuration 320 " PWM control signal 325 ... Circuit configuration 330 ... Control signal 505 ... Oscillator configuration 510 ... Periodicity can be planned Triangle waveform generator 515 ... frequency selection input

605… digital-to-analog converter pAQ 610 ·· output voltage variable (vDES) 615 ·· digital input 620 ··· high-gain error amplifier 625 ··· error signal 700 ... drop circuit 705 ·· current signal buffer 850 " · Step-down detection configuration 855 · · Clamping circuit configuration 900 ... Periodic charging cycle lasts 905 ... Phase delay 910 ... Periodic start time 915 ... Charging continues 1005 ... Start time configuration 1010 ... Charging continuous configuration 1015 ... Current sensing configuration 1020 ... S_R lock 1025 ... AND gate 1035 ... Periodic clock pulse 1040 ... PWM control signal 1045 ... Average current 1050 ... Current difference signal 1105 ... Phase timing comparator 1110 ... Click pulse Wave generator 1115 ... Fixed setpoint voltage 1255a ... electric contact pin 1255b ... electric contact pin 1260 ... node 1265a ... resistor 1265b ... resistor 1270 ... reference voltage 1305 ... charging continuous amplifier 1310 ... continuous Equipped with 1315… individual power-off detection amplifier 1320 .. .5-R lockout 1020a ... SR lockout output 1325 ... ramp output line

40 200425607 1330… Conduct the original constant voltage output line 1340 * " PWM control signal 1350 ... Current signal 1405 ... Clamping circuit 1410 ... Programmable current source 1415 ... Operational amplifier 1415a. Wave capacitor 1430 ... Ramp resistor 1450 ... Phase error detection amplifier 1455 ... Fractional multiplier 1460 ... Switch 1465 ... Phase error signal 1505 ... Inductor current sensing configuration 1510 ... Inductor current signal 1515 ... Current sensing amplifier 1520 ... 1605 ... sum configuration 1705 ... control 1C 1805 ... overtemperature detection circuit 1810 ... VRHOT comparator 1815 ... switch 1820 ... temperature sensing configuration 1825 ... external pin 1900 ... single phase buck converter 1905 ... high-side switch 1910 ... low-side switch 1915 … Switch node 1920… output inductor 1930… control circuit 1935… load 2000… multiphase DC to DC buck converter 2005a-2005n ... output phase 2105 ... converter output current sensing configuration 2115 ... threshold signal 2130 ... Phase-off signal 2135 ... current signal 2205 ... adder unit

41

Claims (1)

200425607 Patent application scope: 1. A step-down converter for providing an output voltage to a group of loads. The output voltage is generated from a group of input voltages according to the required voltage. The step-down converter contains: 5 A set of output capacitors, the output voltage being provided by the output capacitors; A plurality of output switch configurations having separate output inductors coupled to the output, the switch configurations being controllable to provide respective phase output currents through the respective output inductors to the output capacitor 10; A plurality of phase output configurations coupled to the output switch configurations, the phase output configurations are controllable to set the respective phase output currents supplied using the output switch configurations, if a signal representing the output current of the buck converter Lowered below a separately programmable Pro 15 limit signal, each of these phase output configurations is operable to close the branch Other output switch configurations; and a set of phase control configurations that are configured to control the phase output configurations and set the respective phase output currents that are supplied using the output switch configurations, so that the output voltage is close to the required voltage. 20 2. The buck converter according to item 1 of the scope of patent application, wherein each of the output switch configurations includes a set of high-side switches and a set of low-side switches coupled to the high-side switch via a separate switching node The output inductors of each of the output switch configurations are coupled to the respective switch node. 3. The step-down converter according to item 2 of the scope of patent application, which further includes 42 200425607, which includes a set of phase control buses. The phase control configuration controls the phase output configurations via the phase control bus. The phase control bus The bank includes a set of phase timing signals, a set of PWM control signals, and a set of average inductor current signals. Each of these phase output configurations includes a set of start-time configurations that are configured to be based on the phase timing signals. The high-side switches of the respective output switch configurations are turned on, and each of the phase output configurations includes a set of continuous charging configurations configured to cut off the high-side switches of the respective output switch configurations according to the PWM control signal. 4. The step-down converter according to item 3 of the scope of patent application, wherein the starting 10 configuration includes a set of phase timing comparators electrically coupled to the phase timing signal and a set of electrical timing couples to the phase timing The click pulse generator of the comparator output is configured to generate a set of clock pulses based on the phase timing signal and a set of set point voltages, and the clock waveguide passes through the high Side switch. 5. The step-down converter according to item 4 of the application, wherein the set-point voltage is provided by a set of voltage dividers connected between a reference voltage and a ground voltage. 6. The step-down converter according to item 3 of the scope of patent application, wherein the charging continuous configuration includes a set of inclined 20-wave generators electrically coupled to the current difference signal and a set of electrically coupled to the inclined waves The generator and the charging continuous amplifier of the PWM control signal. The ramp generator is configured to generate a set of ramp output signals according to the current difference signal and a set of predetermined voltages. The charging continuous amplifier is configured to The high-side switch is turned off according to the ramp wave output signal and the PWM control signal. 43 200425607 7. The step-down converter according to item 6 of the patent application scope, wherein the ramp generator includes a set of ramp capacitors electrically coupled to the ramp output signal, and a set of electrical couplings to the ramp Wave output signal and a clamping circuit to the original voltage, and a set of programmable current sources electrically coupled between the output signal of the ramp wave and a set of ground voltage, the planable current source is based on the The current difference signal can be controlled. 8. The step-down converter according to item 7 of the scope of patent application, wherein the phase control bus includes a set of signals describing the required voltage, and each of the phase output configurations receives the signal describing the required voltage. The voltage is set according to this signal which describes the required voltage. 9. The step-down converter according to item 7 of the patent application, wherein the ramp generator further includes a set of phase error detection configurations, if the phase output configurations cannot provide a set of phase output currents to match the average inductance Current signal, the phase error detection configuration is configured to generate a set of phase error signals. 10. The step-down converter according to item 6 of the scope of patent application, wherein the continuous charging configuration further includes a set of individual power-down detection amplifiers configured to respond to the requirement to reduce the required voltage and the requirement to reduce the load current At least one of them to cut off the high-side switch and the low-side switch. 20 η · The buck converter according to item 10 of the scope of patent application, in which the requirement for reducing the required voltage and the requirement for reducing the load current are determined according to the PWM control signal. 12. The buck converter according to item 3 of the scope of patent application, wherein each of the phase output configurations further includes a set of current sensing configurations, which are electrically connected to the first set of 44 200425607 Node and a set of second nodes and connected to the average inductor current signal, the current sensing configuration is configured to detect the respective phase output current and based on the average inductor Is current signal and the respective phase output current Generates a set of current difference signals. 13. The step-down converter according to item 12 of the application, wherein the current sensing configuration includes a set of current detection configurations connected to the first and second nodes of the respective output inductors, and a set of currents A comparator, which is electrically connected to a set of outputs of the current sensing configuration and is connected to the average inductor current signal, the current sensing configuration being based on the output of the current detection configuration and the average inductor current signal This current difference signal is generated. 14. The step-down converter according to item 13 of the patent application, wherein the current detection configuration includes a set of current sense amplifiers, a set of positive inputs electrically coupled to the current sense amplifier, and the first node Resistor Rcs, and a set of capacitors Ccs electrically coupled between the positive input and a set of negative inputs of the current sense amplifier, the second node is connected to the negative input, the resistor Rcs and the The time constant of the capacitor Ccs is approximately equal to the time constant of the respective output inductor. 20 15. The buck converter according to item 3 of the scope of patent application, wherein the phase control configuration includes a set of phase timing configuration and a set of PWM configuration, the phase timing configuration is configured to generate the phase timing signal and the PWM configuration It is configured to generate the PWM control signal. 16. The step-down converter according to item 15 of the scope of patent application, wherein the phase time 45 200425607 sequence configuration includes a set of programmable oscillator configurations and a set of periodic waveforms electrically coupled to the programmable oscillator configurations. One of a group of frequencies of the programmable oscillator configuration can be selected through a set of frequency selection inputs, and the periodic waveform generator generates the phase timing signal according to the frequency of the programmable oscillator configuration. 17. The buck converter according to item 15 of the scope of patent application, wherein the pwM configuration includes a set of digital-to-analog converters configured to generate a set of variables describing the required voltage based on the majority of digital VID signals A set of south gain error amplifiers electrically coupled to the variables describing the required voltage and the output voltage, the high gain error amplifier generating the pWM control signal based on the variables describing the required voltage and the output voltage . 18. The step-down converter according to item 15 of the patent application scope, wherein the pwM configuration further includes a drop circuit configured to modify the PWM control signal 'so that the output voltage is proportional to the current flowing through the load. Increase and decrease. 19. The step-down converter according to item 15 of the scope of patent application, wherein the pwM configuration further includes an individual power-off circuit, which is configured to modify the PWM control signal 'so that the phase output configuration reflects a lower The high-side and low-side switches of the respective output switch configuration are cut off by the required output voltage. 2 · According to the step-down conversion n of the third patent scope, each of the phase control configuration and the phase output configuration includes a set of separate over-temperature detection circuits. When the temperature is close to 46 200425607 limit, the over-temperature detection circuit is configured to generate a set of VRHOT signals. 21. The buck converter according to item 1 of the scope of patent application, wherein the phase output configurations include a fixed number of phase output configurations. 5 22. —A phase output configuration of a buck converter, which phase output configuration is electrically coupled to a group of output switch configurations having a set of output inductors, a set of high-side switches, and a set of low-side switches. The buck converter provides a set of output voltages to a set of loads via a set of output capacitors electrically coupled to the output inductor, the output voltage being generated from a set of input voltages based on a set of required voltages The phase output configuration includes: a set of configurations, if the signal representing a set of output currents of the buck converter drops below a programmable threshold signal, the configuration is configured to turn off the high-side and Low-side switch. 15 23 · The phase output configuration according to item 22 of the patent scope of the application, wherein if the signal representing a group of output currents of the buck converter drops below the programmable threshold signal, the configuration is configured to Turn off the high-side and low-side switches of the output switch configuration, which includes a set of converter output current detection configurations that are operable to generate a signal representative of the output current of the buck converter; and a set of phase shutdown The comparator is electrically coupled to a signal representing the output current of the buck converter and to the programmable threshold signal, if the signal representing the output current of the buck converter falls below the programmable threshold signal , The phase shutdown comparator generates a set of shutdown signals to turn off the high-side and low-side switches of the 47 200425607 output switch configuration. 24. The phase output configuration according to item 22 of the patent application scope, wherein the programmable threshold signal is provided by a set of external circuits. 25. The phase output configuration according to item 24 of the patent application scope, wherein the external 5 circuit includes a voltage divider. 26. The phase output configuration according to item 25 of the patent application, wherein the voltage divider includes at least two sets of resistors connected in series with each other between a set of reference voltages and a set of ground voltages. 27. The phase output configuration according to item 24 of the patent application, wherein the external 10 circuit includes a set of digital-to-analog converters operable to output the programmable threshold signal. 48