TW200422942A - Performance level setting of a data processing system - Google Patents

Abstract

A target processor performance level is calculated from a utilization history of a processor in performance of a plurality of processing tasks. The method comprises calculating a task work value indicating processor utilization in performing a given processing task within a predetermined task time-interval and calculating a target processor performance level in dependence upon the task work value.

Description

200422942 玖 '[Invention of the Department of Information [The power of the power processor can be connected to the software and the above algorithm can be used as a profitable pane of energy, the description of the invention: The technical field to which the invention belongs] The present invention is related to information Processing system area. p # In particular, this issue is related to the performance level that can be set in the processor to multiple different virtual w l a «u processor performance levels. Previous technology] An important goal of processor design is to provide better performance and reduce consumption. Some modern processors offer the ability to set it to several different levels of processing performance, depending on the requirements of the application at the time. The processor takes advantage of the fact that the clock frequency of the processor is reduced, and the operating voltage may be reduced to a quadratic power consumption. However, the reduction in processing energy is only affected if the user does not feel it or has no effect on performance. It is therefore important that a reduction in the level of processor performance should not result in missed execution deadlines. Complete a specific processing task before the deadline, but it is less energy efficient to perform the task more slowly, and to perform the task slower to ensure that it meets the deadline more accurately. Known performance level setting techniques include the so-called interval-based performance. Its main concepts are described in Weiser et al., "Reducing the CPU Rank Cheng. " This known interval-based algorithm monitors the processor's history and derives an appropriate performance layer by calculating a fixed and short (10-50 milliseconds) time = ratio of idle time to busy time. . Typically, the overall processor benefit in the most recent time interval is calculated. If it exceeds a critical value, the processor's performance level is increased; otherwise, if the time interval mostly includes idle time, the performance level is decreased. Although this known method works well for regular workloads, it appears to be side-by-side for non-regular (that is, non-periodic) workloads and interactive applications. Other known techniques use the weighted average of overall processor utilization as a guide for future utilization, however this alternative technique has been shown to not produce a clock speed that can significantly increase processor utilization and reduce idle time (see Grunwald et al. The “Dynamic Clock Scheduling Strategy” published in the Proceedings of the Fourth Operating System Design and Implementation Symposium in October 2000. Therefore, for a wide range of workloads, including irregular and interactive workloads, a It is possible to more accurately predict one of the appropriate processor performance levels. Performance level setting technology. The present invention provides a method for calculating a target processor performance level from the history of processor utilization of multiple processing tasks. The method includes: Task work value, which indicates the utilization of a processor that executes a predetermined processing task within a corresponding task time interval. The target processor performance level is calculated according to the task work value. The present invention recognizes a separate processing task (or processing task) Groups) often have identifiable utilization periods at the task level, However, when estimating a proper execution performance, it may be ambiguous for all accumulated observed tasks. By focusing on processor utilization at that task level, performance setting strategies can better tune the diversity of processing tasks With regard to its required performance level, the present invention allows the performance level to be predicted directly for each processing task, rather than indirectly increasing or lowering the processor performance level by an arbitrary number specified by the overall workload 4 200422942 The task work value in a single past time pane can be used to predict an appropriate future performance level for the processing task. However, the preferred embodiment combines the task work values corresponding to several past execution tasks in the same processing task to predict 1 The future effect is at this level. This has the advantage of providing static μ and accurate performance level predictions for specific tasks. Note that the task interval can be set to a fixed value for each execution of each processing task. However, through independent Setting the task interval for each processing task can make the performance prediction system more suitable for different tasks The type of load. In particular, given that a short period of time can be suitable for an interactive processing task, and a relatively long period of time seems more suitable for a non-interactive task. If you choose an unsuitable short task interval, Can cause turbulence between performance levels. Allowing task intervals to be set independently for each processing task increases the likelihood that a stable performance prediction will be selected. In addition, 'set independently for each execution of a specific processing task Time period, the performance prediction may be suitable for considering other tasks that constitute part of the workload during execution. These other co-existing tasks are likely to affect the total execution time of a particular task due to task preemption. Task interval It can be flexibly defined if the interval is included somewhere within its scope to perform the specific processing task described above. However, the preferred embodiment defines a long task time interval so that it starts at the first of a specific processing task—the beginning of a schedule It ends before the subsequent execution of the specific processing task. This has the advantage that it is easy to implement and that the task time interval is related to the frequency of execution of that particular processing task. This makes the technique more suitable for aperiodic processing tasks. 200422942 It will be understood that a number of previously processed task work values for a particular processing task can be combined in many different ways to predict a future for the task = energy level ', for example, an -average or -weighted level that can calculate the task guard value. :. Combining task work values to calculate exponentially decayed work completion values is better because it will have a large impact on the recently calculated task work values. Negative change Although the execution deadline π of the relevant task group can be calculated, it is better to calculate the execution deadline of a task based on Ren: Base, so that the performance of the processor can be adjusted more finely. The task work value and the idle time detected during the task time interval are preferably used to calculate the task execution deadline: since the execution deadline can be normalized to take into account the task time: universal execution performance within the interval '& amp This provides a more accurate estimate than using the real time it took to complete one of the previous executions of the task. The advantage of separately recording the exponential average of the task's work value and the execution deadline of a particular processing task is that the importance of performance-level predictions can depend on the length of the interval at which the task's work value is measured. This prevents the task work value associated with the longest service interval from dominating the predictions and thus compensates for the widely changing window size. It will be understood that the task work value may only be included in the corresponding task time pane 2: the processor that determines the processing task uses 1, and in the preferred embodiment, the predetermined processing consumes other unexpected processing tasks first and the first μ :: Handling of misappropriation is included in the work completion value. This has the advantage of combining-special-ΓΓ and estimating the appropriate performance level and level accordingly. In the expected subsequent execution, the same other tasks are also likely to be preempted by 6 200422942 and the "Hyatt" task at the efficiency level. Therefore, the task execution deadline should consider these preempted tasks. Although the task time window The grid can change the size according to the execution time and the specific execution frequency, but it is better to set the upper bound of the task time pane. This advantage is that it can prevent the unused long-term processing from inappropriate performance. Continue execution at the level. When the task time pane reaches the upper bound, the performance level is recalculated. Also, in a preferred embodiment, the performance level setting method is implemented in the operating system core program software. The point H is that the software can A richer set of execution time information makes a choice, which results in better accuracy. L SUMMARY OF THE INVENTION 'It provides a method for calculating a target based on the application history, including the following steps: at the time interval of the preliminary task: and Target processor performance level. It provides an electronic product based on a processor. One of the items of the processor includes: calculating a task work value, performing a specific process within the interval, a method of a sharp tool efficiency level when the processor of the present invention further performs multiple processing tasks, the method At least one task work value is calculated, which indicates that a processor that executes a specific processing task can calculate the above-mentioned month b program from a further aspect of the present invention based on the task work value to control a computer program of a computer in A utilization history of executing multiple processing tasks is awarded to the processor performance level. The computer program is operable to calculate the task work value. The task work value is specified at a predetermined task time. 200422942 The task value calculation is detailed below. The group 11 2 smart card contains / an event called module 136 words! The core program that supplies the funds is used by a processor on the host to obtain a privileged call; and the target processor performance calculation code is based on the above The task works at the target processor performance level described above. Other objects, features, and advantages described herein will be apparent. Obviously know from the detailed description of the embodiment and the accompanying drawings. Mode] 1 diagram outlines how the power management system can be implemented in a capital system. The data processing system includes a standard core program. The core program 100 of the module includes a system call module scheduling program 1 1 4 and a conventional power management program 1 1 6. An energy management program system 1 20 is implemented in the core program and strategy coordination Program 122, a performance setting control module 1 24, and a tracking module 126. A user processing layer 丨 30 includes a system call 132, a task management module 134, and application-specific data [user processing level 130 through an application The program monitoring module 140 sends a signal to the core program 100. The core program 100 is the other central program that provides basic services to the operating system. The core program can be compared with the shell program, which interacts with user commands in the outermost part of the operating system. The core code in which it runs has full storage of physical resources like memory. Other parts of the system or an application program request the services of the core program through a system call program interface. User Processing Layer 8 200422942 112 and 132. The scheduler its order

And the core program has a system call module for each process using a processor. The conventional power management program ι manages the supply voltage by switching between a power-saving sleep mode and a standard awake mode according to the processor utilization level. The smart energy management program 120 is responsible for calculating and setting processor performance targets. The intelligent energy management program 12 reduces the operating voltage of the central processing unit (CPU) and the clock of the processor without causing the application software to miss the deadline for processing (ie, tasks), instead of relying solely on the sleep mode to reach Power saving purpose. When the CPU is running at full speed, many processing tasks will be completed within its deadline, and the processor will be idle until the next task starts. For example, a task deadline for a task that generates data is the one generated The time point at which the data is required by other tasks 0 — The deadline of the interactive task will be the user's critical threshold (50 · 丨 00 milliseconds). It runs at full efficiency and then completes the task more slowly than the slower one to make it more accurate. It is less energy efficient to meet the deadline. When the frequency of the processor drops, its voltage can be reduced to save energy. For processors implemented in complementary metal-oxide-semiconductor (CMOS) technology, the energy used for a particular workload is proportional to the square of the voltage. The strategy coordination program manages several performance setting algorithms, each of which is suitable for different running time situations. The most suitable performance setting algorithm for a specific condition is selected in the running time. The performance setting control module 1 24 receives the results of each performance setting algorithm and repeats the calculation by processing these results in priority order # 200422942 processor performance. The event tracking module i 26 monitors events located in the core program U 0 and the user processing level 130 and transmits the collected information to the performance setting control module 1 24 and the policy coordination program 1 22. In the user processing level, the monitoring and processing work is through the system call event 1 2 2. Processing task event 134, including task switching, task creation, and task leaving events, and application-specific data. The smart energy management program 120 is implemented as a set of core program modules and hooks are embedded in the standard core program functional modules and are used to control the speed and voltage of the processor. The method implemented by the smart energy management program 120 makes it relatively independent of other modules in the core program 1000. This has the advantage that the performance setting control mechanism is less likely to interfere with the main operating system. Implementation in the core program also means that the user application does not need to be adjusted. Therefore, the smart energy management program 1 2 0 coexists with the system call module 11 2, the scheduling program 114, and the core program's traditional energy management program 丨 6. Although these subsystems may require some hooks (H〇ok). The smart energy management program 120 is used to derive task deadlines and task classification information (such as whether the task is integrated with an interactive application program) from the core program of the operating system by checking the communication type between execution tasks. It is also used to monitor which system calls are accessed by each task and how data flows between the communication frameworks in the core program. Fig. 2 schematically illustrates the three-tier relationship of the performance setting algorithm according to the present technology. It should be noted that the frequency / voltage setting options on a particular processor are generally intermittent rather than continuous. Therefore, the target processor performance level must be selected from a fixed combination of predetermined values. Although known techniques for calculating the performance level of a target processor 10 200422942 include the use of a single performance setting algorithm, the count uses multiple algorithms, each of which has different characteristics suitable for different operating time conditions. For a particular processing situation, the most suitable calculation is selected during operation. The policy coordination program module 122 coordinates the performance setting algorithm and provides shared functions to multiple performance setting algorithms by connecting the hooks in the standard core program 110. The results of the multiple performance setting calculations are collated and analyzed to determine an overall estimate of a target processor performance level. Organize algorithms into a hierarchy of judgments (or stacks of algorithms), where the algorithm's output performance level indicator from the higher (more dominant) hierarchy has the right to take precedence over the lower (less dominant) hierarchy The performance level indicator of the algorithm output. The model implementation in Figure 2 has a three-tier system. There is an interactive application performance indicator at the highest level of the hierarchy, a specific application performance indicator 220 at the middle level of the hierarchy, and a processor utilization performance at the lowest level of the hierarchy. Indicator 230. The calculation of the interactive application performance indicator 210 is based on the calculations described in "Automatic Performance Settings for Dynamic Voltage Adjustment", published in the International Mobile Computing and Web Conference Proceedings by Flatner et al. In July 2001. The interactive application performance level prediction algorithm is intended to provide good interactive performance by identifying the execution period that directly affects the user experience and ensuring that the event is not unduly delayed to ensure that the algorithm uses a relative Simple technology to automatically separate interactive events. Technology relies on monitoring communication from the X server that is a GUI control program to track the execution of tasks that are triggered as a result. However, the method of the common law integration method is based on the discussion method. This and 200422942 The development of an interactive event (typically containing multiple tasks) is initiated by the user and indicated by a -GIH event, such as pressing a mouse button or a keyboard key. Therefore, the GUI control program (in this case, χ server) sends a message to the task responsible for handling this event. By monitoring the appropriate system call (Various versions of reading, writing, and selecting), the smart energy management program 120 can automatically detect the development of an interactive event. When the event starts, the GIH control program and the task to receive the message are marked Is positive in an interactive event. If the task of an interactive event communicates with an unmarked task, the unmarked task will also be marked. During this processing, the smart energy management program 1 20 tracking has been first Occupied indicates the number of tasks. When the preempted task is zero, it means that all tasks have been completed, so the event ends. Figure 3 illustrates the strategy for setting the processor performance level during an interactive event. An interactive event The period is known to change with several important sequences (from tenths of a second to about a second). However, the delay or "skip threshold" at the beginning of the conversion is set to 5 milliseconds to filter out the shortest interactions Events thus reduce the number of requested performance level transitions. Interactive events under 1 millisecond are typically the result of pressing a button repeatedly to the window or moving the mouse across the screen and redrawing a small rectangle. The skip threshold is set to 5 milliseconds because short events can be filtered from the performance indicator forecast without adversely affecting the worst case. If the skip threshold is exceeded during the interaction event, the relevant performance level value is included in the overall interaction performance level prediction. A weighted exponential decay of the performance parameters calculated for all past interaction events provides an average of 12 200422942 performance parameters for one interaction event. It should be noted that according to this technology, the interactive application performance setting algorithm uses a single overall prediction for the necessary performance level of an interactive event in the system. [This is different from the technique described in the paper mentioned above, which uses a different performance level prediction for each task depending on the task that opened the event. ] In order to limit the worst-case scenario where a wrong performance level is predicted from user experience, if the interaction event is not completed before reaching a so-called "emergency threshold", the performance level prediction at the top level is designated as the maximum performance level factor This is a top-level forecast, so the system will enforce it. At the end of the problem interactive event, the interactive algorithm calculates what the correct performance setting for the event should be and incorporates this correction into the exponential decay average that will affect future predictions. An additional optimization is performed and thus if an interactive event process When the critical threshold is reached in mid-range, the moving average is readjusted so that the modified performance level is incorporated into the exponential decay average with a higher weight (using k = 1 instead of k == 3). The performance prediction is calculated for all events older than the skip threshold. The "interaction event deadline" is used to obtain a performance level indicator for each defined interaction event. The deadline is the last time a task must be completed to avoid adversely affecting performance. It is based on the human perception associated with a particular interaction event A performance level indicator for calculating interactive events based on critical values. For example, it is known that 20 to 30 frames per second is fast enough for users to think that a series of images is a continuous flow, so an interactive image can be set to display the event feeling The critical value is 50 milliseconds. Although the actual sensory critical value depends on the user and the task in progress, a fixed value of 50 milliseconds is still considered to be suitable for the interactive algorithm of the hierarchical system. The following equation is used Calculate performance requirements for events shorter than the sensory threshold. ^ Work ise P,-~~ βη Perception Threshold where the full-speed equivalent work intestine Au is measured from the beginning of the interactive event. Program-specific performance indicators in the middle layer of the hierarchy 220 is obtained by sorting out the information output of an application that understands the performance level setting function. These application-based energy management programs 120 have been adopted to provide new API items to communicate performance requirements. The performance indicator 230 is obtained by using the algorithm based on the most used. This algorithm is for each Each task is adjusted based on the time period of a task. All types of tasks performed with expectations are the most important consideration for interactive tasks. Although the interactive certificate has a high level of effectiveness at the high-level, the algorithm based on expectations does not window Since the lowest layer of the ship system can be selected to use a longer power when appropriate. If the history pane is too short and the value between the fixed and fast earthquakes is profitable, it is given to (through the system call) wisdom to effect the month. bRequires specific information related to the system and applications to facilitate the implementation of an algorithm-based forecast and recent utilization history to estimate the processor's future tasks. Derive a usage estimate and calculate the utilization history (that is, use the history window). Grid) based algorithm to consider the processor's interactive application algorithm at the upper level. Only the application algorithm is used to calculate one for security. Level indicator and located in the hierarchical system need to be constrained by a conservative short-term history of use-a stronger power-saving strategy, the possibility of using the history pane at this stage will improve efficiency and may cause performance levels to be predicted on the two typical It is necessary to set a short utilization history 1 ^ grid when using a single unified 14 200422942, 冼 (not a combination of hierarchical systems of an algorithm) to set the performance level for all operating conditions. In order to deal with the intensive processors of 2 to 14 For interactive events, this unified algorithm must make the history pane short. The performance setting algorithm for each two-tier stack uses a way to process work at a specific time interval. In this embodiment, the A 70% working method is the full-speed (processor) equivalent work performed during this time interval. This full-speed equivalent work is estimated based on the following formula: worb ^ YjiPi i = l where i is one of the different processor performance levels implemented at that particular time interval; ti is the non-consumption consumed in performance level i Idle time in seconds; and Pi is the processor performance level i is expressed as a peak (full speed) processor performance level score. This equation is valid in systems where a time stamp counter (task counter) measures in real time. This completion is done in an alternative embodiment and can be calculated differently using a cycle counter whose count rate changes with the current processor frequency. In addition, the equation implies the assumption that a workload's operating time is inversely proportional to the processor frequency. This assumption provides a reasonable estimate of the work done. However, this assumption is not always accurate, mainly because the ratio of the bus speed to the processor speed during the performance adjustment process is non-linear. The completion calculation may be fine-tuned in alternative embodiments to take these factors into account. Figure 4 outlines the execution of a workload on a processor and the use of 15 200422942-Task A calculation history pane. The horizontal sleeve at 4th represents time. Task A starts execution at time S first, and then starts several data structures based on the task. There are four data structures corresponding to the following four parts: f) the current status of the task counter; (ii) the current time (instant); (iH ) _ The current status of the idle time counter; and (iv) set an execution bit to the logical level], indicating that the task has started execution, the service counter, counter and idle time counter are used to calculate the processor utilization related to task eight And then calculate the efficiency requirement of task Λ. At the time of pE, task a has not been completed but is occupied by another task B. Preemption occurs when the task scheduler 4 determines that his task has a higher priority than the running task. When task A is preempted, the execution bit is maintained at the logic level '丨 to indicate that the task still has tasks to be completed β at RE, task A continues to execute 0, it is rescheduled and continues to execute until completion at Tc And then voluntarily gave up processing time. Upon completion, task A can initiate a system call for the processor to perform other tasks. The execution bit is reset to logic level '0' when task A is completed at TC. After the TC hours, there is an idle period followed by an advanced task, followed by an idle period. At RS, task A starts to execute a second time. At the time of RS, the status of the execution bit '0' related to task A indicates that information exists to start calculating the performance requirements of task A. Therefore, the target performance level of the processor can be set accordingly for the re-execution of the upcoming task A. The utilization history pane of a specific task is defined as the period from the start of the first execution of the specific task to the start of the next execution of the task and should be included in the relevant pane. 16 200422942 contains at least one preemption event for the task ( In this case, task B preempts task A at 玟 £). Therefore, the utilization history pane of the task in this case is defined as a period from time S to time RS. The target performance level for task a in this pane is thus calculated as follows:

WorkEstNew = (Λ X WorkEstold + Workjse)! (K +1)

Deadline New = (kx Deadlineold + (Work) se + Idle))! (K +1)

Where k is a weight, Idle is the number of seconds between the time s and the time Rs in the fourth frame, and the deadline of task A is defined as (+. In this particular example, for the 4-round task B The preemptive task execution detection guidance algorithm determines the utilization history of each task. Processing tasks executed before the next unpreempted task A is scheduled is often highly related to the execution of task A. The interval between the TC and the RS is the "latency period", and the processor can execute a reduced level of performance during this period. However, the "work C" is included in the performance level calculation due to the reduction of the available latency period. The positions in the above equation and each represent an exponential decay average. This exponential decay average makes the updated estimate have a greater influence on the average than the old estimate. The weight k is a parameter about the exponential decay average. .K = 3 is known to work effectively and this small value indicates that each estimate is a good one. With individual tracking job predictors and deadline predictors, the importance of performance predictions is based on the use history pane Depending on the length. This ensures that performance estimates related to larger pane sizes do not dominate performance predictions. The performance level indicator for this algorithm ... epecM. vej is calculated based on 17 200422942 two-fingered Perfper's payload. It is based on self-adaptation and every known 5 equals the size of the grid, but it is used when the calculation history pane is long according to the new negator. Wait for the upper layer to calculate the average ratio of the attenuation of the applied formula to obtain: sepecrnvu-hw " heart. Calculate the unique level value for each job. In accordance with the strategy of the present technology, the% of work for a particular task is recalculated between a subordinate working time interval of 50 亳 to i 50 milliseconds. However, because% is calculated on a task-to-task basis, each executed task uses its task-based% value, and the% 4W value fact is corrected to 10 seconds (reflecting the task switching event) . This algorithm is different in interval-based algorithms. The former uses estimates for each task and adjusts the usage history window on a task by task basis. Although known uniform performance setting algorithms use exponential decay to flatten their fixed-use panes (10 to 50 milliseconds) across all tasks performed as a whole, rather than calculating a task-based utilization over a variable task-based utilization Based averaging. According to the anticipation-based algorithm of this technology, it is necessary to avoid an interactive CPU extreme task from being used without being preempted during the processing section. "Because it can only be downloaded at least once once the task is preempted." The history pane is used, so the waiting time of the performance level t prime is used for this task. To avoid unwanted performance time & calculation work estimate t is not pre-occupied 6¾ i§ set the limit value in particular If a task lasts for 100 milliseconds and is not preempted, it is recalculated based on the preset value. Considering to ensure a more urgent program history, 1¾ grid is provided to the interactive application 18 200422942 program through the hierarchical system layer 21, so choose 1 The value of 00 milliseconds. It is also considered that only user applications that may be affected by the 100 millisecond pane threshold are batch-intensive batch operations such as compilation, which may take seconds or even minutes. In this case an additional 100 milliseconds (0.  i seconds) execution time can be an important wise performance. Figure 5 outlines an implementation of the three-tier system performance strategy stack of Figure 2. The implementation includes a performance indicator strategy stack 510 and a strategy event handler 530, both of which output information to a target performance calculator 540. The target performance calculation program 540 is used to organize the results from four performance setting algorithms: a high-level interactive algorithm, a middle-level application-based algorithm, and two different low-level algorithms. The four algorithms can be executed simultaneously. The target performance calculation program 540 derives a single overall target performance level from the multiple performance indicators (four in this example) generated by the strategy stack 5 10. The strategy stack 510, together with the strategy event handler 530 and the target performance calculation program 540, provides a flexible framework for multiple performance setting strategies, so the strategy algorithms of each layer of the stack can be replaced or exchanged according to user requirements. Therefore, the performance strategy stack provides a platform for user-defined performance setting strategies for experimentation. Each of the various performance setting algorithms is dedicated to dealing with different specific types of uptime events. However, since there are four different algorithms for outputting different performance indicators in the exemplary embodiment of FIG. 5, the software must decide which of the four performance indicators is preferred to set the overall target value. 19 200422942 It is also necessary to determine the time at which one overall target performance level can be efficiently calculated, assuming that each performance setting algorithm can be executed independently and produce output at different times. At the same time, it is also necessary to consider how to combine the performance indicator under the condition that multiple performance setting algorithms all use the same processing event as a basis for determination, otherwise false target updates may occur. In order to deal with these issues, the strategy stacking 510 algorithm is organized in a three-tier system as shown in the figure, where higher-level policies may take precedence over performance-level requests that are derived from lower (not dominant) layers. Therefore, the hierarchical algorithm can take precedence over the hierarchical algorithm, and the latter can take precedence over the two algorithms of the level 0. Note that each hierarchy can itself contain multiple alternative performance setting algorithms. Different performance setting algorithms do not know their position in the hierarchy and can determine their performance based on any event in the system. When a specific algorithm requests a performance level, it sends an instruction to the strategy stack 510 along with its desired performance level. Each algorithm of the strategy stack includes a command 512, 516, 5 20, 5 24 and stores a corresponding performance level indicator 514, 518, 522, and 526. The ignore instruction 5 20 for the layer 1 algorithm indicates to the target performance calculation program 440 that the related performance level indicator should be ignored when calculating the overall performance target. The setting instructions 512 and 516 of the two algorithms that have been assigned to the level 0 make the target performance calculation light 5 40 and set the corresponding performance level regardless of any performance level request from the lower level of the hierarchy. However, this setting command cannot take precedence over performance level requests from higher-level system levels. In this embodiment, one level 0 algorithm has requested to set the performance to 55% of the peak 20 200422942 level, while the other level 0 algorithm requires to set 25% of the peak level. The target performance calculation program uses the request with the same priority in combination with the value of t in this example as the performance indicator of the layer. In level 2, if the command is specified with the same 80% performance indicator. The "set" instruction provides the target performance calculation program 54. The level must be 80 ° /. Assume that this is greater than any performance indicator from a lower class. In this example, the level 0 performance indicator is 1 and the performance indicator will be ignored so that the overall target will actually be 80% of the performance. Since the most recently calculated performance level of each algorithm is slightly stacked in the memory 5, the target performance is calculated at any time to calculate a new overall target value without the & algorithm. When one of the algorithms on the stack is able to request a hierarchy, the target performance calculation program calculates an updated overall target from the bottom to the content of the data structure. In the example in Figure 5, the overall pre-level is set at level 0. 1 remains at 55% and changes the whole at level 2 although each performance setting algorithm can be triggered (by system components) to calculate a new performance at any time when there is a set of common events that all performance settings respond to Hierarchy. During this process, 530 will monitor these events and flag them for strategic event information to the target performance calculator 54. The performance is set to an operating program to optimally set 55% if it is greater than the setting. If it is greater than the setting, the overall performance of the system level is set to 55% and the level is set as a peak indicator. The calculation program 540 can call each A new performance calculation evaluates the performance level of the command effectiveness. The estimate is 55% and the forecast is 80%. A processing event in the algorithm will tend to be strategic event processing. This handler will be divided into 21 200422942 categories including reset event 532, task switching event 534, and performance change event 536. The performance change event 536 is a notification that warns each performance setting algorithm to pay attention to the current performance level of the processor, even though it typically does not change the performance request on the policy stack 510. Regarding the strategic events 532, 534, and 536 of this special classification, the overall performance level is not calculated every time one of the algorithms sends an updated performance level indicator. On the contrary, the performance level calculation is integrated, so for each event notification, it is only calculated once after all the event handlers of all relevant performance setting algorithms have been called ** An application programming interface (API) can be provided to The device driver or the device itself. This interface enables a device to notify the strategy stack of 5 10 and / or individual performance setting algorithms of any significant changes in operating conditions. This causes the performance setting algorithm to trigger a recalculation of the target performance level and thus promptly take changes in the operating conditions. For example, when a CPU-intensive processor-bound task starts, the device may send a notification to the policy stack 510. This notification is optional and the performance setting algorithm may not need to respond to it when received. FIG. 6 schematically illustrates a work tracking counter 600 according to one of the techniques. The work tracking counter 600 includes: an incremental value register "ο, which has a software control module 620 and a hardware control module 630; an accumulator module 640, which has a work count value Register and a time count register 'a time base register 646;-an instant timer 65 and a control register 660. The work tracking counter of this exemplary embodiment can be 22 200422942 with a known time The flag counter and the CPU cycle counter are different. The increment value of the counter in this embodiment is close to or at the time when the count value is incremented, and is proportional to the actual work performed by the processor. The increment value register 610 includes a work completion calculator. , Which estimates the work completed by the processor in each counter cycle. The completed work is estimated to be obtained through the software control module 620 and / or through the hardware work module 630. The software control module implements a The amount of work is simply calculated in relation to the current processor speed. If the processor is running at 70% of peak performance, the incremental value will be 0. 7, and if the processor is operating at 40% of peak performance, the incremental value will be 0. 4. When the performance control module 620 detects that the processor is interposed in the counter cycle, the increment value is set to 0 °. In the alternative work tracking counter embodiment, a more sophisticated software algorithm is used to calculate a Precise job estimates. Table 1 lists the measurement data, which indicates one of a cpu limit loop and an MPEG video workload when considering a performance level transition between two different processor speeds (high to low in this example). The percentage difference between the expected operational period and an actual operational period. The result is based on the conversion after clear processor performance levels -300, 400 and 5 OOMhz (as shown in the leftmost stop in the table). The top column of Table 1 lists the initial performance levels that will transition to the corresponding processor speeds listed in the leftmost column. At the CPU limit loop, predictions and actual measurements cannot be distinguished from noise. However, for MPEG workloads, there is an incorrect loss of about 6% -7% at each 100Mhz processor frequency stage. The largest inaccuracies in these workloads appear to be less than 20% (19.4%), which is considered acceptable for systems with only a few fixed performance levels. However, as the available range of selectable minimum to maximum processor performance in a system increases and the range of each performance level phase decreases, it appears that a more accurate job estimation procedure will be required. CPU limit loop MPEG video workload after conversion 400Mhz 5 0 OMhz 600Mhz 400Mhz 500Mhz 600Mhz 300Mhz -0. 3% -0. 4% -0. 3% 7. 1% 1 3. 5% 19. 4% 400Mhz -0. 1% 0. 0% 6. 9% 1 3. 3% 500Mhz 0. 1% 6. 8% Table 1 replaces the more sophisticated algorithms of the exemplary embodiment using more accurate job estimation techniques, which include monitoring indication characteristics (tracking of major events such as memory access through a technology device) and estimated and actual The workload reduction ratio 'is not assuming that the completion of work is directly proportional to processor speed. A further alternative embodiment uses a cache hit ratio and a memory system performance indicator to accurately generate a job estimate. A further alternative exemplary embodiment uses software to monitor the ratio of the processing time used to execute a programming application relative to the processing time used to execute a wonder application task. The hardship control module 63 can estimate the completion of work even during the transition of the processor between two fixed performance levels. Each processor can have a pause of approximately 20 microseconds during the transition, during which time the processor will not send any instructions. This pause is due to the time required to resynchronize the phase-locked loop to the new target processor frequency. In addition, before changing the processor frequency, the voltage must be stabilized to a proper value for the new target frequency. Therefore, there is a transition time of at most one second, during which it can be assumed that the processor runs at the old target frequency but consumes energy at the new target level (because the voltage is set to the new target level, the frequency can pass through the intermediate frequency stage While jumping up several levels to measure the value register during the transition period where the shadow frequency changes dynamically, the software example embodiment uses both hardware and software to work, one of the alternative exemplary embodiments to estimate the completion of the work. Group 640 is timed from the value and added to the work count value. The work count value register is at each value. The timer time is marked as a signal. To measure the work in the accumulation module 6 4 〇 for a predetermined time The beginning of a predetermined time interval while another difference provides the completion of work. The instant timer also controls the rate of temporary increase. The time basis of this time count operates but is used to measure changes in response levels. Here the processor operates the hard艎 Control module to update and add undetected dynamic changes. Although this display control module 6 2 0, 6 3 0 can be used only after calculation In the two modules, the incremental value register 610 reads an accumulated sum stored in the incremental register. The timer time mark increases the work count value in the time interval derived by the timer 650 when the work count is increased. The value stored in the count is read twice, once at the end of the person. An indication of the time interval between these two values. The time count value register stored in the memory 644 and the work count ^: The value takes the same time consumed instead of the completed work. 25 200422942 has both a time counter and a completed work counter to form a performance deterministic algorithm. The purpose of providing a time-based register 646 is multi-platform capacity and conversion to seconds. Its It is used to specify the base (frequency) of the two counters 642, 644, so the time can be accurate and consistent, in other words, the accumulated value stored in the time count value register provides a measure that takes time milliseconds. The control register mode Group 660 contains two control registers, each of which uses one of them. A counter can be moved, stopped, or reset through an appropriate control register. Figure 7 To explain a device that can provide a number of different levels of fixed performance depending on the characteristics of the workload. The device includes a CPU 710, a timer 720, a power supply control module 730, and the incremental value of the work tracking counter in Figure 6. Register 610. The power supply control module 730 determines the fixed performance level at which the CPU is set and selects an appropriate clock for the real-time timer 720. The power supply system module 730 will The information on the current processor frequency is input to the incremental value memory 610. Therefore, the value of the increment is proportional to the processor frequency, which provides an estimate of the available work done by the processor. This strategy stacks many 5 1 0 The performance measurement algorithm uses the utilization history of the process at a specific time interval (pane) to estimate the appropriate target speed of the processor in the future. The main goal of any performance setting strategy is to maximize the busy time of the processor from the start of execution to the deadline of the task by reducing the processor frequency and voltage level to an appropriate target performance level. In order to actually predict the target performance level, the Intelligent energy management sets the pre-launch and start-up control relays between phases. 26 200422942 Formula 1 20 provides an extraction to track the actual work that the process has completed in a specific time interval . This completion work abstraction allows performance changes and lag time to be taken into account regardless of the implementation of specific hardware counters that may vary between platforms. Based on this count, in order to obtain a work measurement estimate for a time interval, each performance setting algorithm is assigned a "work structure" data structure. Each algorithm is set to call a "work start function" at the beginning of the time interval , And call a "work stop function" at the end of the specific time interval. During the completion of the work measurement, the content of the work structure is automatically updated to specify the proportion of idle time allocated by the individual performance level of the processor and Use processor time scale. The information stored in the work structure is then used to calculate the full-speed equivalent work value ('The value is then used to predict the target performance level. This completed work extraction function is implemented in the smart energy management program 1 2 0 software and provides a convenient interface to the smart energy management program 1220 for developers of performance-level prediction algorithms. The completion of the task extraction also simplifies the performance setting system of this technology. The port connection of the system is different hardware. Architecture. A major difference between alternative hardware platforms is the way in which time is measured on that platform. ° Specifically, some architectures provide a low recurrence cycle counting method through time stamp counters, while other architectures only provide externally programmable time breaks to the user. However, even if a time stamp counter is provided, it does not necessarily measure the same For example, the first hardware platform contains both Intel [RTM] and ARM [RTM] processors. In these processors, the counter calculates CPU cycles and the counting rate is related to the speed of the processor 27 200422942. The counter stops counting when the processor enters the sleep mode. The hardware platform includes the Crusoe [RTM] processor, which implements a time when the counter consistently calculates the period of the processor at the peak rate and holds the peak rate count, even if the processor is in The work extraction in the sleep mode helps the target efficiency design technology be implemented on these two platforms. The estimated work calculated in this embodiment does not determine that the work is performed at half the peak performance and is not necessarily consumed at speed. The fact that it takes twice as long to complete. One reason for this violation is that This is not the case with the processor's core program speed reduction memory system. Therefore, the core program and memory card effect increase is more beneficial to the memory. Run simulation to estimate the performance setting technology compared to a known technology 'the known technology It is built in Transrneta Crusoe CPU, 4 long run (LongRun), power management program. Transmeta CPU has 'LongRun' power management program built into the processor. LongRun is different from other known power management technologies, and it avoids the system. The need for power management to take effect. LOngRun uses historical usage to guide clock selection: if it is highly used, it will increase the degree 'and reduce performance when it is used at a low level. Unlike other implementations on more unified processors 'The power management strategy can be relatively easily implemented on the Crusoe processor, because the processor already has a hidden soft-line dynamic binary translation and optimization. The goal of this simulation is. The second standard has continued to increase. This finish is slower than replacing a full-intuition-thinking processor. Special t7 in a Crusoe body. Adjust the processor speed of the processor. Many implementations are implemented at the system level. 28 200422942 Strategies such as LongRun are implemented at such a low-level layer of the software hierarchy how to execute them effectively. This technique executes on the same processor as LongRun. This simulation was performed on a Sony Vaio PCG-C1VN laptop, which uses a Transmeta Crusoe processor and operates at a fixed performance level of 300Mhz to 600Mhz at a performance level of 100OMhz. This simulation uses one with Linux 2. 4. 4 An improved version of the acl8 core program, Mandrake 7. 2 operating system. The estimated workload for comparison is as follows: Plaympeg SDL MPEG player library, Acrobat Reader for calculating PDF files, Emaes for text editing, NetScape mail and news for reading news 4. 7.Konqueror 1_9 for web browsing. 8 and Xwelltris 1.0 as a 3D game. 〇. The performance test program for interactive shell commands is a record of a user performing miscellaneous shell operations during a period of approximately 30 minutes. In order to avoid the variability that the dynamic rendering engine of the Crusoe processor may generate, most performance test programs are executed at least twice to prepare the dynamic rendering cache memory, and all the generated simulation data except the last one is executed. be ignored. The design of the performance setting algorithm according to the present invention will not hinder the way the host platform controls the timer. For the purpose of this simulation, this technology provides a millisecond resolution timer without changing the way the Linux built-in 10ms resolution timer works. This goal is achieved by carrying a timer assignment routine (which checks for timer events) to parts of the core program that are often executed, such as schedulers and system calls. 29 200422942 Because the performance setting algorithm based on this technology is designed to have hooks to the core program so that it can break certain system calls to find interactive events and it is called at every task switch, it can be Attach some indicators to these hooks to manage timer assignments. Each hook is augmented by implementing a time-scaled & ten-counter read, a time stamp with the next timer event, a comparison, and a branch-to-timer assignment routine on success. It is found in practice that this strategy establishes a timer with sub-millisecond accuracy. Table 2 below details the timer statistics attached to this simulation. In the worst case, the resolution of the timer is limited by the time unit of 10 milliseconds (seemingly inconsistent with Table 2) in the scheduler. However, since the performance-setting algorithm based on this count focuses on measurement, which usually occurs close to the time trigger ', the resolution reached is considered sufficient. It has proven to be advantageous for the system's soft-plated timer to stop working when the processor is in sleep mode, because this means that the interruption of the timer does not change the sleep characteristics of the operating system and applications during execution. The timer used has high resolution and low overhead. The advantages of these timers facilitate the development of implementations with both active and passive modes. In the active mode, the control is based on the performance setting algorithm of this technology. In the passive mode, the built-in LongRun power management program is responsible for performance, although the smart energy management program of this technology acts as an observer of performance and performance changes. Table 2 30 200422942 30 to 40 required to access a time stamp counter Average interval of period timer check __ ~ 〇 · 1 leap second__ ~ 1 millisecond timer accuracy — average timer checks duration of allocation (including possible execution of an event handler) 1 00 to 15 The performance change produced by LongRun is similar to that achieved by the timer allocation routine. The smart energy management program 12 according to the present technology periodically reads the processor's performance level through a specific machine register and compares the result with a previous value. If the two values are different, the changes are recorded in a buffer. The smart energy management program according to the technology includes a tracking mechanism that keeps a record of major events in a core program buffer. This record contains performance level requests, task preemption, task IDs (identification tokens), and the performance level of the processor from different strategies. When running the simulation, LongRun can be compared with the performance setting algorithm of this technology during the same execution period: LongRun controls the performance setting and the intelligent energy management program 120 based on this count can be used to output its control over the same workload. A possible decision. This simulation strategy is used to objectively evaluate the difference between the known LongRun technology and the non-repeatable execution of the interactive performance test program between the technology. In order to evaluate the additional burden of using this measurement and performance setting technology, the performance setting algorithm according to this technology is equipped with a marker that continuously tracks the elapsed time of the performance setting algorithm code in runtime. Although the extra operating time burden on a Pentium II according to the technology is about 0. 1% to 31 200422942 0 · 5%, but the additional burden on the Transmeta Crusoe processor is 1% to 4%. Further measurements in virtual machines, such as 'VMWare' and 4-user mode linux, (UML) confirm that the additional burden of performance setting algorithms based on the technology may be much greater in virtual machines than on traditional processor architectures. However, this additional burden can be reduced by algorithm optimization. MPEG (Motion Picture Experts Group) video playback poses a difficult test for the performance setting algorithms of all tests. Although the performance setting algorithm typically places a periodic load on the system, the performance requirements may still vary depending on the type of MPEG frame. Therefore, if a performance setting algorithm responds to past (highly volatile) MPEG frame decoding events using a relatively long pane of time to predict future performance requirements, it may miss the execution of intensive computing frames (less representative Deadline). On the other hand, if the algorithm only considers a short interval, it will not converge to a single performance value and will quickly oscillate between multiple settings. Since each performance level change causes a conversion delay, rapid oscillation between different performance values is not satisfactory. The LongRun simulation results are confirmed in the oscillating behavior of the MPEG performance measurement program. This technology addresses the oscillating problem of this MPEG workload by setting algorithms based on interactive performance settings at the top of the hierarchy to limit the worst-case response. There are more traditional interval-based prediction algorithms at the bottom of the hierarchy that can take a longer-term view of performance-level requirements. Figure 8 is a table detailing the 'plaympeg' player (lL 本 · ίP: // www. I〇kipames. com / develor) ment / smpeg. php3) 32 200422942 Analog measurement results when playing various MPEG videos. Certain internal variables of the player have been disclosed to provide how the player is affected by the results of dynamically changing the processor performance level during execution. These numbers are shown in the MPEG decode column of the table. In particular, this 'Ahead' measures how close each frame is to the deadline. The closeness to the deadline is indicated by the cumulative number of seconds of playing each video. For maximum power efficiency, the early variable value should be as close to zero as possible, although the processor's slowest performance level places a lower limit on how early the value can be reduced. A 'just-in-time' block located on the far right of the form indicates the total number of frames that just met its deadline. The larger the number of just-in-time frames, the closer the performance setting algorithm is to the theoretical optimal value. The data of the execution statistics in the table in Figure 8 were collected by the smart energy management program 120 of the monitoring subsystem. In order to collect information about LongRun, the smart energy management program 120 is used in the passive mode to gather the trajectory of performance changes without controlling the processor performance level. The idle stop indicates the percentage of time spent in the idle loop of the core program (which may handle internal chores or only hovering), and the hibernation booth only consumes the processor when it is actually in a low-power sleep mode. Time proportion. It can be seen from Section 8 that for each of these performance measures the technology performs much better than LongRun. Figure 9 is a table listing the processor performance level statistics collected during the execution of each job load. Calculate the time ratio for each performance level as part of the total non-idle time during the execution of that workload. The ‘Average Performance, Levels’ column in the table indicates the average performance level (expressed as a percentage of peak performance) during the execution of each workload. Therefore, in all cases, the average performance level of each workload using this technology is lower than using LongRun, and the last block indicates that the average performance achieved with LongRun is reduced. The playback quality of the LongRun workload and the workload of the present invention is the same, i.e. the same frame speed and no missing frames. The results show that the technology can predict the necessary performance level more accurately than the known LongRun technology. The increased accuracy results in a 11% to 35% reduction in the average performance level of the processor during the performance test program. Since the amount of work performed between performing a workload should remain the same, this lower average performance level implies that reduced idle and hibernation times can be expected when the technology's smart energy management program is launched. The simulation results confirmed this expectation. Similarly, the number of frames that exactly meet its deadline will increase when the Smart Performance Manager of this technology starts, and the amount of time accumulated when decoding is earlier than its deadline will decrease. This intermediate performance level (emphasized by each column in the table in Figure 9) also shows significant reductions. According to the performance setting algorithm of the present invention, a single performance level below the peak is selected on most performance measurement programs to give the maximum execution time (> 88%), and LongRun usually sets the processor to run at full speed. The exception to this general rule is ‘Danse De Cable, workload, where the two lowest performance levels are selected based on the technology ’s performance setting algorithm and oscillate between these two levels. The reason for this oscillating behavior is due to the specific performance level of the Crusoe processor. The performance setting algorithm based on this technology will decide to choose a performance level that is only higher than 300 Mhz—a little bit. Because 34 200422942 and when the performance level prediction fluctuates up and down at 300 Mhz, the level will be set to the closest two performances. Level value. The most noteworthy difference between this technology and the performance of this technology is that when a large amount of processor activity is detected, it jumps very quickly and appears overly cautious. Regarding all workloads, the level level of using LongRun has never been lower than 80%, and the multiple 'Red's Nightmare Small' performance test programs set by this technology have dropped. The algorithm of this technology is more active than LongRun but is used by service agencies. Quick response when descending. Because LongRun did not have information on interactive performance, it was forced to act in a short time frame and the simulation results showed that this made it inefficient. Figure 10 contains two different MPEG meters called 'Legendary' (#Danse de Cable) (# 10B 圊). Each chart shows that the time spent for LongRun and the technology at the four-energy level (300, 400, 500, 600 MHz) is the same, but the playback quality is the same each time. The processor's peak performance time is much longer than the LongRun technology specifies for this condition. The playback of 'Legendary' depicted in Figure 10A, the movie's algorithm based on this technology selects a 500 MHz performance level. The results of the movie ‘Danse de Cable’ show that the algorithm is operational. The processor is at 300 MHz at the two performance levels. The target performance is known as LongRun. When LongRun, the performance level is equal to the processor efficiency. The blowing level is at L 52%. According to the quality display, there is anything about the ratio of the processor efficiency in the conservative 10A graph) and the shadow result graph. Although it can be seen in the table that the energy level is consumed below, the results show that according to Fig. 10B, the switching algorithm between 400 MHz 35 200422942 based on this technology and the fixed algorithm Mhz 〇 First observation. However, it is based on a goal of LongRun level. The first: the program but the execution period of the technique can be requested. In some cases, it is actually lower than the current technique. Due to the difficulty of serving the load, the type of control 120 is only set and selected. By comparing the two movies, the LongRun performance is set at most of the execution time and the peak processor speed 600 is selected. The deep LongRun in the quality of different performance setting strategies continuously and quickly alternates the performance level up and down. The processor performance level of the system controlled by this technology remains close to the heart level. The two graphs (upper row) of 11A 囷 show the performance level of the processor during the execution of a performance test program. result. Figure 11B shows the actual performance level in the circle, and Figure 11C reflects the performance level of a processor that can operate at any performance level (assuming the same maximum performance). Pay attention to the required performance level calculated by the algorithm based on the technology. The lowest performance level that can be achieved on the processor. Considering the simulation results used to compare the two techniques on interactive workloads, it is difficult to create a repetitive interactive performance test program. The interactive work is estimated to be much more difficult than the multimedia performance test program. In order to combine the experimental measurements with a simple simulation technique. Furthermore, the interactive performance test program runs under the local LongRun power management process and is executed in the intelligent energy management program based on the technology, so it only records the performance it may make without actually changing the processor. Level of effectiveness. 36 200422942 Figure 12 shows performance data collected during a simulated run for evaluating interactive workloads. Figure 12A is a graph of the performance level percentage of LongRun technology versus time (in units of 粆) and the result in this case is equivalent to the processor's actual performance level in the measurement. Fig. 12B is a numerical performance level chart, and Fig. 12C is an original performance level time function chart that can be set by the performance setting algorithm of the technology to control the processor. Note the calculations of this technique. In fact, in the control, its performance setting choices will have a different run time impact than the choices made by LongRun. Because of this factor, the time axis in the graphs of 12B and 12C 圊 will be regarded as approximate. In order to avoid the problem of time deviation of the statistics, the passive performance level trajectory of the simulation based on this technology is processed later to evaluate the impact of increased execution time that may be caused by using this technology instead of LongRun. Focus only on interactive events, not the entire performance-level trajectory. The interactive performance setting algorithm of this technology includes the function of finding an execution process that has a direct impact on the user. This technology gives effective readings regardless of the algorithm responsible for control and is therefore used to focus on our measurements. Once the execution scope of an interactive event is independent, both LongRun and the technology calculate the full speed equivalent to complete the work during the event. Since LongRun controls the CPU speed during the measurement period and its operation is faster than when controlled by this technology, the event process corresponding to the results of this technology must be extended. First, this technique calculates the remaining work based on the following formula:

Workpresent technique Remaining = W〇rkLongRun- w〇rkPresent technique 37 200422942 Second, the algorithm calculates the extent to which the length of the interactive event needs to be extended-assuming that the algorithm of this technology continues at its predicted speed operation value until it reaches an emergency Critical, and then run at full speed. The statistics are also adjusted independently. It is found that the results of using this technology are very similar to the results we observed on similar workloads (same performance test program but slightly different interactive load) to actively control the processor based on the algorithm of this technology. However, when the algorithm according to the present technology is actually responsible for control, the number of performance setting choices is reduced and the performance level is more accurate. Figure 13 shows the statistics collected using the time offset correction technique described above. The six diagrams in the figure all include two stacked sheds. The left-hand column on each watch is related to LongRun and the right-hand column is related to this technique. Each block is stacked to represent the proportion of time spent in interactive events at the four performance levels supported by the computer. These performance levels range from 300 Mhz from the bottom to the top, with an increase of 100 Mhz to 600 Mhz. Even from a high level, the algorithm obviously based on this technology consumes more time at the lower performance level than LongRun. In some performance testing programs, such as Emacs, there is almost no need to run quickly and meet the deadline for the interaction when the machine stays at its lowest possible performance level. At the other end of the map is the Acrobat Reader performance test program, which shows the behavior of two statistical methods: the processor runs at either the peak level or the minimum level. Even in this performance test program, many interactive events can be completed on time at the minimum performance level of the processor. However, when it comes to calculation pages, 38 200422942 the peak performance level of the processor is still not sufficient at the user's perception threshold. Completed within the deadline. Therefore, when a sufficiently long interactive event is encountered, the algorithm according to the present technology switches the processor performance level to a peak value. By contrast, during the execution of the Konqueror performance measurement program, algorithms based on this technology can utilize all four available levels of performance of the processor. • This * can be compared to the LongRun strategy, which consumes the processor more than half of its peak level. In summary, the simulation results detailed above with reference to Figures 8 to 13 have shown the performance of two performance setting strategies implemented in different levels of the software hierarchy on multi-media and interactive workloads. It has been found that the Transmeta LongRun power management program implemented in the processor body takes more conservative decisions than the algorithms implemented in the core program of the operating system according to this technology. The results achieved by the algorithm based on this technology in a set of multimedia performance test programs are 11% to 35% lower than the average performance level achieved using known LongRun technology. Since the performance setting algorithm based on this technology is higher in the software stack than LongRun, it can make decisions based on a richer set of runtime information, which translates to higher accuracy. Although it has been shown that LongRun's firmware is more inaccurate than an algorithm implemented in the core program, it does not reduce its practicality. LongRun has important advantages as an unknown operating system. It is understood that the gap between low-level and high-level implementations can be bridged by providing a basic performance setting algorithm such as LongRun in tough ships and exposing an operating system to optimize processor performance setting selection. The performance measurement hierarchy based on this technology provides a mechanism to support this design. The minimum setting strategy on the stack can be practically implemented in the processor's firmware. Although the illustrative embodiments of the present invention have been described in detail and taken into consideration the related drawings, it should be understood that the present invention is not limited to those precise examples, and that those skilled in the art will not deviate from the scope of the present invention as defined by the accompanying patent application. Many changes can be realized within the spirit. [Simplified illustration of the figure] Fig. 1 schematically illustrates a power management system according to one of the techniques, such as being implemented in a data processing system; Fig. 2 schematically illustrates the technique according to the present technique. The hierarchy of the performance setting algorithm. The third circle outlines the setting of processor performance in an interactive event. Figure 4 outlines the execution of a workload on the processor. Task A calculates the utilization history pane. Figure 5 outlines the implementation of the three-tier system efficiency strategy in Figure 2; Figure 6 outlines the task tracking counter according to one of the techniques; Figure 7 outlines a method that can provide numbers based on workload characteristics Equipment at a fixed performance level; Figure 8 is a table detailing the implementation of the performance accompanying parameters for playing various MPEG video calculations. Tuning can be performed at three levels and a stack of 600; a number of different signals. 20042004942942 Analog measurement results of the 'plaympeg' video player; Figure 9 is a table 'which lists the execution of each workload Statistics of processor performance levels during the period; Round 10 contains two charts showing the results of playing two different MPEG movies called 'Legendary, (Figure 10A) and' Danse de Cable '(Figure 10B); Figures 11A, 11B, and 11C outline the characteristics of two different performance setting strategies. Figures 12A, 12B, and 12C outline the simulation results of testing different performance setting algorithms on interactive workloads. Figure 13 outlines Explain the statistical data collected using a time deviation correction technique. [Simple description of component representative symbols] 1 00 core program 11 0 standard core program functionality 1 12, 132 system call module 114 scheduling program 1 1 6 conventional power management program 1 20 smart energy management system 122 strategy coordination program 124 performance Configuration control module 126 Event tracking 130 User processing layer 134 Job management module 136 Application-specific data 140 Application monitoring module 210 Interactive application performance indicator 220 Specific application performance indicator 230 Task-based processor Use the performance indicator 5 1 0 Performance indicator strategy stack 41 200422942 5 12,5 1 6,520,524 Command 5 24 If greater than set 5, 14,51 8,522,526 Performance layer 530 Strategy event handler 534 Task switching event 540 Target performance calculation program 610 Increase Value register 630 hardware control module 646 time base register 660 control register 730 power supply control module 520 ignore finger 7F device 5 3 2 reset event 5 3 6 performance change event 600 counter 620 software control Module 640 Accumulator Module 650, 720 Real-time timer 710 CPU (Central Processing Unit)

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Claims (1)

422942 Patent application scope " i A method for calculating a target processor performance level of one of the processors from a history of a processor performing a variety of processing tasks in a utilization history, the method includes at least the following steps: "Task work value" refers to the utilization of a processor that executes a specific processing task within a predetermined task time interval; and calculates the target processor performance level based on the task work value. 2. The method as described in item 1 of the scope of patent application, which at least includes calculating a plurality of task work values, which are corresponding to a plurality of previous executions of the specific processing tasks described above, and combining the plurality of task work values to the above The future execution of one of the specific processing tasks calculates the target processor performance level described above. 3. The method according to item 2 of the scope of patent application, wherein the predetermined task time interval is set independently for each of the plurality of processing tasks. 4. The method according to item 3 of the scope of patent application, wherein the predetermined task time interval is set independently for each execution of the specific processing task. 5. The method according to item 4 of the scope of patent application, wherein the predetermined task time interval extends from the beginning of the first schedule of one of the specific processing tasks to the beginning of one of the subsequent schedules of the specific task, The predetermined task time interval is associated with the first schedule. 6. The method according to item 2 of the scope of patent application, wherein the previously performed multiple task tasks corresponding to the special 43 200422942 scheduled processing task # are combined to calculate an exponential decay completion value for the specific processing task. . 7. The method according to item 1 of the scope of the patent application, which includes detecting at least a duration of idle time within a predetermined task interval, and the task working value and the duration of the idle time are used to calculate a task execution deadline for the upper task. . 8. The method as described in claim 7 of the patent scope, wherein the deadline is calculated for each of a plurality of each of the above-mentioned specific processing tasks, and the multiple task execution deadlines are calculated as an exponential decay The average task execution deadline. 9. The method as described in item 7 of the scope of the patent application, wherein the fixed processing is calculated based on the above-mentioned exponential decay average work completion value of the processing task & numerical agricultural reduction average task execution deadline. The above-mentioned target processor performance level of the task. 10. The method as described in item 11 of the scope of patent application, further comprising] during the processing period of the above-mentioned specific processing task, detecting at least a line period 'the at least one suspended execution period representative The period during which the specific processing task is switched to a further and non-tasking period before the completion of the above: and the calculation of the above-mentioned task work value for this specific processing task, because at least one period of suspended execution period includes processor utilization. The method described in item 10 of the scope of patent application, at least its value is subtracted and the average value is included in the above and based on the above characteristics The combination of execution before the execution of the scheduled task corresponds to this and the above-mentioned special steps: a suspension of the execution of the first task and the same processing. This sets an upper bound within the predetermined task interval described in 44 200422942 above, Therefore, if the specific processing task continues to be executed without detecting the suspended execution period within a duration period greater than or equal to the upper bound, the target processor performance level of the task is automatically recalculated. 1 2. As requested The scope of the patent is the widest ... Each of the tasks has a y, and if the corresponding task has been executed but has been executed, then the above flag value is displayed. 13: The method described in the second item of the scope, where When the value of any 2Γ is used to calculate the above-mentioned target processor performance of the above-mentioned future execution of the above-mentioned task, the processing performance of each task is described by a corresponding time interval on this U-test. To be normalized.% -Carrying- computer programs for controlling __Dianmao's DengTeng program products, which run from a processor to a variety of One of the tasks is to use the history to calculate = one of the processor's target processor performance levels. The above electric cat program calculates at least the task work value calculation function, which is operable to calculate-task work value. The task work value indicates a predetermined The utilization of a processor that executes a specific processing task within a task time interval; and a target processor performance calculation code that is operable to calculate the above-mentioned target processor performance level based on the above-mentioned task work value. One of the products described above, wherein the above-mentioned task work value calculation calculator calculates multiple task work values, which corresponds to the previous execution of 45 200422942 on each of the above specific processing tasks, and combines the above multiple task work values to calculate The above-mentioned target processor performance level for one of the above-mentioned specific processing tasks to be performed in the future. 16. The computer program product according to item 15 of the scope of patent application, wherein the predetermined task time interval is independently set for each of the plurality of processing tasks. 17. A computer program product as described in Item 16 of the Patent Scope, where The above-mentioned predetermined task time interval is set independently for each execution of the specific processing task. 18. The computer program product according to item 17 of the scope of patent application, wherein the predetermined task time interval is extended from the start of the first schedule of one of the specific processing tasks to the start of the subsequent schedule of one of the specific tasks. For a period of time, the predetermined task time interval is associated with the first schedule. As one of the computer program products described in item 15 of the scope of patent application, Yin combines the previously performed values of the multiple tasks corresponding to the specific processing task to calculate an exponential decay average work completion for one of the specific processing tasks. value. 20. The computer program product as described in item 14 of the scope of the patent application, which includes a detection code that can be used to measure a continuous value of the idle time within the predetermined task time interval, and is based on the task work value and the above. The idle time duration value calculates a task execution deadline for the specific processing task. 46 200422942 2 1. As one of the computer program products covered by the patent application scope of 20 $, in which the above-mentioned task execution deadline is limited to +0 ^ for each of a plurality of previous executions of the specific processing task. ^ Calculate and combine multiple task execution deadlines to calculate an exponential Fei Nong minus average task execution deadline. 22. A computer program product as described in the scope of application for patent No. 20, wherein the average exponential decay is based on the exponential decay, and the average reduction is based on the above-mentioned Shanghai Yihe sum formula corresponding to the specific processing task. The task execution deadline value is used to calculate the above-mentioned target processor performance level for the Xi & + i '疋 processing task. 23 · As one of the computer program products described in item No. 14 of the scope of application for Gule 14, it further includes: Suspended execution period and code measurement, which is capable of detecting at least one suspended execution during the processing period of the specific processing task mentioned above. Period, the at least one suspended execution period represents a period that has elapsed before switching from the specific processing task to a further and different processing task before completing the first task: and the above-mentioned target working value calculation code, which can be operated on the The processing task calculates the above-mentioned task work value, and thus it includes processor utilization during the at least one suspended execution period. 24. The computer program product as described in item 23 of the scope of patent application, wherein an upper bound is set for the predetermined task time interval, so if the specific processing task is continuously performed without detecting in a period greater than or equal to the upper bound When the above suspended execution period is detected, the above-mentioned eyepiece processor performance level of the task 47 200422942 is automatically recalculated. 25. The computer program product described in item 14 of the declared patent scope stores a flag value for each task. If the corresponding task has not been completed, the above flag value is displayed. 26. When the computer program described in 15 items is combined with the task task value to calculate the target processor performance level above the task, each task task value of one of the specific processing tasks is normalized by a corresponding time interval. Into. 27. A device for controlling a computer to calculate a target level of the processor from a utilization history of a processor in the execution of the task. The device at least contains task task calculation logic, which is operable at Calculated value 'The task work value indicates the processor utilization of a specific processing task during a predetermined task time, and the target processor performance calculation logic, which is operable to calculate the target processor performance level according to the value. 28. The device as described in item 27 of the scope of patent application, wherein the value calculation logic calculates a plurality of task work values, which are respectively previously executed on the respective processing tasks, and combine the above-mentioned values to calculate the above specific processing tasks. One does not describe the target processor performance level. 29. The device as described in item 28 of the scope of patent application, wherein the product 'wherein the execution is started but the product' wherein the scheduled tasks to be performed in the future are previously executed multiple processing tasks are performed by a processor within a task interval The task worker should perform the above-mentioned scheduled 48 422942 service time interval for the specific plurality of task workers to be set for each of the plurality of processing tasks. 30. The device as described in item 29 of the scope of patent application, wherein the predetermined task time interval is independently set for each execution of the specific processing task. 3 U The device according to item 30 of the scope of patent application, wherein the predetermined task time interval is a period extending from the start of the first schedule of one of the specific processing tasks to the start of the subsequent schedule of one of the specific tasks. The scheduled task time interval is related to the above-mentioned first schedule · 32. The device as described in item 28 of the scope of the patent application, wherein the previously-executed values of the plurality of tasks corresponding to the specific processing task are combined to calculate the above-mentioned One of the specific processing tasks exponentially decays the average work completion value. • The device as described in item 28 of the scope of patent application, which at least contains the test logic, which is operable to detect a duration of an intervening time within the above-mentioned predetermined task interval, and according to the above-mentioned task operating value and the above-mentioned interim The time duration value is used to calculate a task execution deadline for the specific processing task. ， Π " 丨 Waiting the above tasks • Deadline is calculated for a plurality of previous executives of the above specific processing task, and the multiple task execution deadlines are combined to calculate an exponential decay average task execution deadline value. 3 5 · As for the equipment listed in Item 33 of the scope of the patent application, its _ basis is corresponding to: 49 The above-mentioned processing cooking service, the above-mentioned index exponentially decaying average work completion value, and the above-mentioned special-type reducing average task execution deadline value Calculate the above-mentioned target processor performance level on 36 · Rushen: processing tasks. The equipment described in item 28 of the M range further includes: The processing period of the debt measurement service during the execution of the kiosk: 'It can be operated in the above-mentioned specific processing, and the execution is suspended. If at least one suspended execution period is measured, the at least-temporary = Represents the above-mentioned specific processing period from the above-mentioned specific processing period before completing the above-mentioned task: and, to go further-step by step and different processing tasks-time and place filial piety * working value calculation logic, which is operable to calculate the above tasks The task's work value, so it includes processor utilization during the at least one suspended execution period. ~ The device described in item 36 of the patent scope, which sets an upper bound for the above-mentioned pre-task time interval, so if the specific processing task is continuously performed without taking a test within a period greater than or equal to the upper bound When the above-mentioned pause # β, .. dispute period, the above-mentioned target processor performance level of the task is automatically recalculated. 38. The device as described in the scope of application patent (28 items), wherein a flag is stored for each task. If the corresponding task has been started but not completed, the above flag value is displayed. The device as described in claim 28 of the patent scope, wherein when the above task value is combined to calculate the target processor performance level of the future execution of the above task, a corresponding predetermined task interval 50 200422942 is used. Normalize the work value of each task previously performed by each of the specific processing tasks described above. 51