TW200419942A - High-resolution single-ended source-synchronous receiver - Google Patents
High-resolution single-ended source-synchronous receiverInfo
- Publication number
- TW200419942A TW200419942A TW092130662A TW92130662A TW200419942A TW 200419942 A TW200419942 A TW 200419942A TW 092130662 A TW092130662 A TW 092130662A TW 92130662 A TW92130662 A TW 92130662A TW 200419942 A TW200419942 A TW 200419942A
- Authority
- TW
- Taiwan
- Prior art keywords
- amplifier
- signal
- output
- receive
- providing
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
- H04L25/0264—Arrangements for coupling to transmission lines
- H04L25/0292—Arrangements specific to the receiver end
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Logic Circuits (AREA)
- Amplifiers (AREA)
- Dc Digital Transmission (AREA)
Abstract
Disclosed are novel methods and apparatus for efficiently providing high-resolution single-ended source synchronous receivers. In an embodiment of the present invention, a source-synchronous receiver is disclosed. The receiver includes: a first amplifier to receive a clock signal and a data signal, the first amplifier providing a first output signal; a second amplifier to receive a complementary clock signal and the data signal, the second amplifier providing a second output; a third amplifier to receive the complementary clock signal and the data signal, the third amplifier providing a third output signal, the second and third output signals being combined to provide a fifth output; and a fourth amplifier to receive the clock signal and the data signal, the fourth amplifier providing a fourth output signal, the first and fourth output signals being combined to provide a sixth output signal.
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/320,148 US6762623B2 (en) | 2002-12-16 | 2002-12-16 | High-resolution single-ended source-synchronous receiver |
Publications (1)
Publication Number | Publication Date |
---|---|
TW200419942A true TW200419942A (en) | 2004-10-01 |
Family
ID=32506807
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW092130662A TW200419942A (en) | 2002-12-16 | 2003-11-03 | High-resolution single-ended source-synchronous receiver |
Country Status (2)
Country | Link |
---|---|
US (1) | US6762623B2 (en) |
TW (1) | TW200419942A (en) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7823003B1 (en) * | 2007-01-23 | 2010-10-26 | 3Par, Inc. | Voltage referencing clock for source-synchronous multi-level signal buses |
KR20210097355A (en) * | 2020-01-30 | 2021-08-09 | 에스케이하이닉스 주식회사 | Data receiving device, semiconductor apparatus and semiconductor system using the same |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6104225A (en) * | 1997-04-21 | 2000-08-15 | Fujitsu Limited | Semiconductor device using complementary clock and signal input state detection circuit used for the same |
US6286072B1 (en) * | 1997-08-19 | 2001-09-04 | International Business Machines Corporation | System and method for synchronizing data communication between asynchronous buses |
US6535032B2 (en) * | 2001-04-25 | 2003-03-18 | Micron Technology, Inc. | Data receiver technology |
-
2002
- 2002-12-16 US US10/320,148 patent/US6762623B2/en not_active Expired - Lifetime
-
2003
- 2003-11-03 TW TW092130662A patent/TW200419942A/en unknown
Also Published As
Publication number | Publication date |
---|---|
US6762623B2 (en) | 2004-07-13 |
US20040113659A1 (en) | 2004-06-17 |
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