TW200419629A - A wafer start plan scheduling method for an IC foundry - Google Patents

Abstract

A wafer start plan scheduling method for an IC foundry. First, daily reasonable WIP is determined for a bottleneck equipment. Then, daily wafer start quantity is determined according to an overall capacity limit and an MPS target requirement of the IC foundry and the daily reasonable WIP of the bottleneck equipment. Afterward, a critical ratio is calculated for each of a plurality of lots, and to schedule the lots according to the corresponding critical ratio and the daily wafer start quantity, so as to generate the wafer start plan for the IC foundry. Finally, the wafer start plan is adjusted according to a production limit of each lot.

Description

200419629

P1 & hair is related to a kind of wafer under ftu (w * Start invention belongs to the technical field ° an and special ~ 丨 ancient method a and integrated circuit product manufacturing method and integrated circuit production port, and particularly Related to a kind of delistable + fabrication, Zhiguang > «j M ^ Requirement of the integrated circuit gas factory's wafer offloading book 丨 | by 卩 p 七 、 + ..β # Λ ^ ^ Exclusive method, integrated circuit product manufacturing method and integrated circuit product. Prior technology, the pursuit of the goal of Yongyan operation, the company must continuously improve its own competitiveness, and the competitiveness of the company depends on customer satisfaction The productivity of a company and the production capacity of the company are the responsibility of the production plant, and the capacity management is the biggest factor that affects the productivity. In the current economic downturn in Panji, and the competitive advantage is not easy to improve, the internal reference of the company has changed. It is necessary to be more precise and effective in terms of capacity management and management. In other words, the industry must ensure the existing capacity and improve the overall profitability and competitiveness of the enterprise by effectively managing capacity. Body Circuit Manufacturing (10Foundry), how to effectively manage and make full use of production capacity to meet customer demand without increasing the cost of half-products has also become one of the important S standards pursued by integrated circuit manufacturers. F Generally speaking There are two types of wafer offloading methods in integrated circuit manufacturing plants: MRP (Material Requirement Planning) and CONWIP (Constant Wafer In Process). Among them, MRP is a forced system (Push

0503-8882TW (Nl); TSMC2002.〇737; yianhou.ptd page 6 200419629 V. Description of the invention (2)

System), which cuts the batch of goods (Lot) into the factory building according to the demand and performs 1 (Plan) release, the situation generated by MP; Because MRP does not consider the load in the factory building, the internal product of the factory will arbitrarily exceed the negative loss of the factory building. This has resulted in unnecessary unnecessary changes in the manufacturing plant. On the other hand, COWIP is a type of acquisition system (Pu11 System), which is processed in accordance with a predetermined room. ⑽ WIP roughly V port / 2 to release the batch The delivery to the factory did not take into account customer needs, and d :::; the situation in the house 'but its MRP and C0NWIP wafer offloading method% used the factory capacity. Because this product is effective and can also meet the client ’s bathroom contamination From the ten requirements, it is impossible to consider the level of demand for production capacity by both parties, and the mechanism hinders the house ...

.-V. ·, $ Summary of Contents | In view of this, the main purpose of the present invention is to provide a wafer pick-up plan for integrated circuit manufacturing plants with integrated supply capabilities:: Need another object of the present invention is Provide a method for manufacturing integrated circuit products according to the wafer off-load plan of <1 and supply capacity; and ::: demand product manufacturing method and integrated circuit products. Integrated Circuit In order to achieve the above-mentioned object of the invention, the manufacturing method and integrated circuit product of the wafer supply plan scheduling method of the integrated circuit manufacturing factory ^ ^ ^ can be achieved. An integrated circuit product according to an embodiment of the present invention of the integrated circuit manufacturing plant under the wafer leaf cut 0503-8882TW (Nl); TSMC2002-0737; yianhou.ptd page 7 'decide bottle circuit manufacturing, and bottleneck factory each According to the rate, and the wafer lower body circuit production limit production factory every day output target. Among them, the main production line of the current production line of the target crystal neck machine factory, the number of wafers per wafer, the wafer demand of the manufacturer, the number of shipments under the main birth circle plus five, the description of the invention (3) Scheduling method, first of all, according to the target output of the integrated process, determine the critical circuit of the integrated circuit to manufacture each batch of goods, and then complete the daily production of the integrated integrated circuit system based on each batch of goods. The target volume of wafers on the day in the factory after the planned adjustment in the minimum bulk circuit manufacturing plant for the main production schedule product level. Reasonable in-process production capacity limit per day, reasonable work-in-process quantity. Afterwards, the criticality rate of shipments will be reduced to the wafer offloading plan from small to large. Loading plan. The delivered quantity is the overall target output quantity of the daily production schedule of the bottleneck machine, and when the item needs to be integrated, the past: unsuccessful product water level. The main production drainage level must be calculated to calculate the corresponding small and integrated goods. Finally, according to the reasonable capacity limit, the demand is to load the wafer, circuit manufacturing, and wafer discharge.

In addition, in the manufacture of integrated circuit products according to the embodiments of the present invention, first, the daily work-in-process water level of the bottleneck machine is determined. The overall capacity limit in the integrated circuit manufacturing plant, the output of the production schedule: standard demand, and the daily reasonable work-in-progress water level of the bottleneck machine determine the daily wafer offload quantity of the integrated circuit manufacturing plant. After that, calculate the critical rate of each batch of goods, and schedule the batches from small to large according to the criticality of each batch and the daily wafer shipment quantity of the integrated circuit manufacturer. Wafer drop-off plan of integrated circuit manufacturing factory, and adjust the wafer drop-off plan according to the production limit of each lot. Finally, according to the wafer offloading plan,

200419629 V. Description of the invention (4) Dispatch the corresponding batch to manufacture the corresponding integrated circuit products. Implementation In actual situations, the wafer off-load plan must be based on the monthly MPS (Master Production Schedule) target, the front-end machine status of the plant, the status of online work in progress, customer requirements and human Experience to decide. Therefore, in order to balance the needs from demand and supply, the present invention proposes four factors that must be considered in the scheduling of wafer offloading in integrated circuit manufacturing plants: (1) Critical Ratio (C / R), ( 2) MPS output target demand, (3) Capacity Limit, and (4) Front End Line Balance (75) are explained below. (1) Critical rate (C / R) The critical rate (C / R) is used to evaluate the urgency of each shipment to make it a shipment schedule. The critical rate (C / R) is the remainder from the delivery date: the ratio of the finished product time, the formula is as follows: al, C / R = (Μ PS date-W / S date) / (forecast cycle time) where ', 、 MPS date 〃 can be the turn of 0 generated in MPS or the delivery date is deducted by a buffer time (such as the first two dates of the delivery date 'AW / S date' is the time when the wafer is unloaded; 'The mouth includes the production time (Run Time) and / or one (Queue Time) required for a product, where each product has a different production time, and the time to wait can be known through simulation.

200419629 V. Description of the invention (5) Note that during the batch production process, the critical rate (c / R) can be dynamically changed. During batch production, the formula for the critical rate (C / R) is: C / R = (MPS date-current date) / (forecast cycle time-current date). When the critical rate (C / R) is between, it means that the shipment has progressed in the future; when the critical rate (C / R) is greater than i, it means that the shipment has exceeded the schedule. When / R) is equal to i, it means that this batch of f exactly meets the schedule. Since the period is calculated based on the conditions in the abandoned house, the critical rate (C / R) can reflect the demand and supply demand. In autumn, because the conditions in the plant are dynamically changing, for example, #The front end of the plant is full of work in progress, and the interval between the batches that have not yet begun will be very long, so the production of a peptide batch ^ "In the hope ^ is close to i or even small W. At this time, U = i: fC / R) may be connected to the product. The situation will be more serious. This will be released immediately to catch up with the schedule, which will only damage the factory building. It will not help. Appropriate shipments to Qiaoding Hexing increased factory operations, and wafer offloading planning methods cannot only consider this factor. (2) MPS output target demand The wafer delivery plan can be calculated using a fixed cycle time that requires careful consideration. A simple example (with the date and time) and in this case, the cycle time of product A is early J Example :: shown in Figure 1. At 6 days. It is specially designed for 8 days, and the cycle time of Product B is in the actual situation. Due to the production capacity and demand, the monthly output of MPS does not correspond to the ten days in the current month. The total amount

200419629 V. Invention description (6) does not correspond. However, when the above conditions are consistent and-an integrated system is established, the factor for MPS output target demand can be unnecessary and included by the critical rate (C / R). (3) Capacity Limit In addition to demand requirements, the plant conditions should also be considered to produce a complete and effective wafer offloading plan. Plant capacity limit (CapacUy

Limit and Front End Line Balance are two basic factors, which are considered to reflect actual plant conditions. As machine conditions, work in progress profiles (Pr0fi1e), and operator efficiency have been changing, the plant's production capacity has changed dynamically. In order to effectively reflect the dynamics of the plant, at least four capacity limits must be considered. (a) Capacity limit of special tool group (c 0 n s tr a i η) Under certain product combinations (Mixes), some specific tool groups may become bottlenecks in the plant. For example, if there are too many memory products, Poly-Etcher may become a bottleneck. In addition, when the overlay is a problem with the yellow area, the scanner's load balance needs to be maintained. To prevent machine overload, whether through simulation or a simple static model (S i mp 1 e S t a t i c Mod e 1), these capacity limits must be considered. (b) Furnace batch size optimization In the semiconductor front-end wafer manufacturing process, many furnace tubes are used to

200419629 V. Description of the invention (7) Specific film. Furnace tube has the largest batch size and long-term processing. CA Fanyu In order to make full use of the furnace tube, batches with the same formula (ReCiPe) are assembled together to form a batch for simultaneous processing. (c) Restrictions on the yellow light mask (Mask) ^ The tools can be used and the shipment can only start when the yellow light mask is ready: 行. Each product has its own specific light region for each yellow light layer. There are many batches of goods using the same photomask at the same time, which will cause yellow light congestion. When many steppers and scanners are available In ancient times, shipments had to be waited for due to insufficient masks. According to experience, it is recommended that a product with a mask set (Set) cannot release more than 12 batches in one day &gt; 0 (ύ) overall capacity limitation system inflammation = MPS output demand on the demand side is different, the overall capacity limit is at At:? The monthly output and the cycle time target of the terminal sigma can be generated according to Wei Ba々 · + ... ill: y). In addition, according to Little + period time = ThrughPut Rate, when the λ target of m period is known, the required WIP level is calculated by ^ calculation. The wafer unloading plan must attempt to adjust the target in-printing water level to achieve the required WIP level. The overall capacity limit can be calculated using Hibiscus &lt; ⑷ ^ Juristic) estimates. Use ^ / person to calculate official plan calculation, and inspiration / number of work in progress is 8_〇, this month's current situation 'assuming that the output rate is i 2 00 wafer / day, week

200419629 V. Description of the invention (8) The time target is 2.2 seconds / layer, and the output rate required for next month is 40,000 wafers / month. According to the Li i 111 e formula, the required work-in-progress = cycle time x output rate = 2.2x40000 = 88000. Therefore, in order to achieve the required number of work in progress in the middle of the month (15th), the wafer off volume on the first day of the next month = (88000-80000) / 15 + 1200 = 1733 〇 In addition, for heuristic estimation, In other words, it is assumed that the bottleneck is in the yellow light region, the cycle time target is 2.2 μs / layer, and the output rate is 40,000 wafers / month. According to Li tt le formula, work in process = cycle time X output rate = 2.2 X 40000 = 88000. Therefore, it is converted into a yellow light layer to calculate · 880000 χ (the average number of layers of the batch / 2) = the number of layers remaining in all batches + the number of layers under the wafer χ average batch. Therefore, the wafer off-load quantity can be obtained. (4) Front-end balance (Front End Li in semiconductor factories, the front-end fluctuates greatly. As mentioned earlier, the characteristics of the furnace processing. Therefore, when the number of products will quickly accumulate. In the calculation of the front-end reasonable in-process Identified, it must have the WIP usually in front of the front-end machine to unload the wafer and the bottleneck tool or historical WIP data forecast. The bottom line plan needs to adjust the current WIP picture 2 The display according to this hair bow ie Balance) *. · * · _ ^ .... &gt; · Human products are usually ΐ! The furnace tube is unstable and the tube has the largest batch size and the furnace tube is unstable for a long time. In a short time, before the product level, the front-end bottleneck must have high utilization or large variability, so it accumulates. After the bottleneck tool is identified, the reasonable WIP water level can be simulated through, like the overall capacity limit, the wafer water level can reach the reasonable WIP water level. ^ Examples of integrated circuit manufacturers

V. Description of the invention (9) The operation flow of the crystal slicing scheduling method. Scheduling: ΪΪ! The wafers of the integrated circuit manufacturing plant of the embodiment are unloaded ▲ "Two: ί ': If the steps are kissed, verify that the integrated circuit manufactures the Λ bottle continuation machine, and follow step S22, &lt; The water level of the product is high. /, The bottleneck machine is a reasonable daily manufacturer. If step S 2 3, the imitation storage section 1 can limit the output of the main production schedule. Σ y target requirements, and bottleneck machines, such as step _, according to each batch rate, and the number of wafer shipments' from small to large batches of scheduling 2 = wafers of integrated circuit manufacturing plants Unloading plan. After the maintenance, if step S26 is performed, adjust the weighing and unloading according to the production limit of each batch of goods. After this step, the production line g of the integrated circuit manufacturing plant can be correspondingly based on the unloading of the wafer 2 The batches are released for production to produce the corresponding product. The integrated circuit manufacturing plant's daily wafer offload quantity is the overall production system, the main production schedule outputs the target demand, and the daily bottleneck machine is combined. ^ = The lowest product water level. Among them, the main production schedule output target needs to be under the wafer of the day in the bulk circuit manufacturing factory. The target quantity. Ma Ji noted that when the wafer off-loading plan is adjusted, if there are any restrictions that can restrict the shipment of the goods being violated and there are other batches of stock that can be released, the violating part of the batch may be rejected. Is pushed out (Push 〇ut) and other batches are pulled in (Pull In) to make up for the original production quantity, and when the wafer is released,

0503-8882TWF (Nl): TSMC2002-0737; yianhou.ptd Page 14 Description of the invention (10) After the plan has been adjusted, the target under-wafer order in the main manufacturing plant for the day is based on the integrated circuit under-target Quantity. τ quantity plus wafers that have not been reached in the past. Figure 3 shows that a wafer is off-load. The target output demand is 5 batches per day; row = sub. Assume that the main production batches, #days of the same product, and the production-restriction maximum of 6 colors per day, a maximum of 3 batches per day; 4 batches on the evening, the black reasonable in-process water level in Figure 3 ( RWIP) are g, respectively, and the daily shipments of machines q (dl to d5) are ranked according to their critical rate (C / R), cabinet 8, and 7; and per-sequence (WSO). The wafers are arranged as shown in the figure. In this case, the limit, the main production schedule output (requirement HWSQ) is-the smallest overall product in-process water level, 〆, '瓶 # 机 台 every Reasonable date = 5. d2 The number of batches that should be dropped = 1 and the number of _ is-(5, 6 '5) :. The maximum number of batches per day is U; =, 6, :) = ^ Dropped, and originally planned to be dropped-, This batch of goods a is forced to be delayed to d3, and the batch of goods b that should be shipped Jβ is pulled to d2 to be shipped. Batches, and the main production row = n (5,6'3) = 3, because the heart can only place 3 batches, so the next-Λ output target demand is 5 batches per day (difference 2 per day W = 7 batches of two == production = process output target demand increased to min (5 + 2,6 8) -6. The number of batches that should not be ^ is a batch and d4 can only be 6 = the main production row The target demand of the process output is 7 production schedule output ΓΓ 2 Λ (a difference of 1 batch), so the next-day master's delivery capacity of the shipment;) = 6 5 + 1 = 6 batches per day, so Ying

200419629 Fifth invention description (11) Therefore, by using the cargo planning and scheduling method provided by the present invention, τ α # # #. I have an effective mechanism for supplying seven lives under the wafers of the manufacturer to simultaneously say that the core capacity is not related to the capacity of the factory. The supply capacity is tested when the customer needs to complete the delivery plan and effectively manage the crystal miscellaneous orders in the Li integrated circuit manufacturing plant to manage and use the capacity in the plant. Xinyang Although the present invention has been disclosed in the preferred embodiment as above, it is limited to the present invention. Anyone who is familiar with this art, it is not used to .; It can be modified and retouched. Therefore, the fine scope of the two inventions §Subject to the scope of the patent application attached. 1 protection

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In order to make the above-mentioned objects, features, and advantages of the present invention more comprehensible, the following specific examples are given in conjunction with the accompanying drawings to explain in detail as follows: Figure 1 shows a calculation using demand data and a fixed cycle time. An example of a wafer offloading plan. FIG. 2 is a flowchart showing an operation flow of a method for scheduling a wafer off-loading plan of a integrated circuit manufacturing plant according to an embodiment of the present invention. Figure 3 shows an example of a wafer pick-up schedule. Symbol description S21, S22, ..., S26 ~ operation steps; a, b ~ batch; d1, d2, d3, d4, d5 ~ date. RWIP ~ reasonable work in progress water level; C / R ~ critical rate; wso ~ wafer order; WSQ ~ wafer order.

Claims (1)

200419629 1 · A wafer loading plan scheduling method for an integrated circuit manufacturing plant, including the following steps: determining at least one bottleneck machine's daily work-in-progress water level; based on an overall capacity limit of the integrated circuit manufacturing plant With a main production schedule (MPS) output target demand, and the bottleneck machine's daily reasonable, the HP water level is determined, and the number of wafers shipped per day at Rongji Circuit Manufacturing Factory is calculated accordingly. Critical rate of one batch of shipments; and, — According to the magnitude of the criticality of each batch of shipments and the number of known wafers on the mother day of the integrated circuit manufacturing plant, the batches are processed from small to large Schedule 'to complete the wafer offloading plan of the integrated circuit manufacturing plant. W ^ According to the crystal of the product manufacturing circuit manufacturer described in item 1 of the patent application, the circle: h plan scheduling method, and further includes identifying the bottleneck machine in the product manufacturing circuit factory. 3. The method of scheduling the wafer round-off plan of the integrated circuit manufacturing plant as described in item 1 of the scope of the patent application, further including adjusting the wafer round-off plan based on the production restrictions of each of these batches. 〇 \ As the crystal of the integrated circuit manufacturing plant described in item 1 of the scope of the patent application, the method of scheduling the delivery plan, wherein the target output demand of the main production schedule is the wafer delivery of the day in the integrated circuit manufacturing plant. The number of goals. . 5 · According to the method described in item 4 of the patent scope of the integrated circuit manufacturing factory, the method of scheduling is described below, in which the integrated circuit manufacturing process is performed on the wafer every day for the entire production capacity. Limitation, the target output of the main production schedule, and the minimum of the reasonable work-in-process water level of the side bottleneck machine daily. 200419629 6. Application Patent Scope 6. As described in the integrated circuit manufacturing round-off plan scheduling method described in item 3 of the scope of application for patents, "The main production schedule is lost under the wafer in the manufacturing factory in Dianluo Road. The target number of shipments plus the target quantity of wafers delivered. 7. According to the integrated circuit manufacturer's round-off plan schedule m described in item 1 of the scope of the patent application, the emergency rate is used to evaluate the urgency of batch B, one per factory, and the emergency rate is Calculated according to the following formula: C / R = (MPS date-w / S date) / (predicted cycle time) at the turn of the two C / R: A; rush rate, Mps date produced in the main production schedule "Parent>" or "Parent's Day" deducts a buffer time, w / s time round off time, and the predicted cycle time is the door time and / or waiting time of the product. Throne time and% = method of manufacturing physical circuit products, including: ¾ the following steps: 疋 v a bottleneck machine daily reasonable work-in-progress water level · according to one of the integrated circuit manufacturing plant's overall capacity limit and production capacity scheduling Process (MPS) output target demand, and the daily product water level of the bottleneck machine, determine one wafer per day for the integrated circuit manufacturing plant; the wafer delivery plan for the number of factories; and corresponding Dispatch the batches of goods, calculate the corresponding batches of batches based on the number of wafers shipped on the mother day of the dangerous factory for each batch of shipments, and complete the manufacturing of the integrated circuit. Wafer shipment plans will be used to manufacture the corresponding integrated circuit products. One of the critical rate; the magnitude of the critical rate and the integrated circuit system are as small as large and the batch of goods is imported = 200419629 9) The method for manufacturing integrated circuit products as described in item 8 of the scope of the patent application for Shenyang, including the identification of the bottleneck machine in the integrated circuit manufacturing plant. 1 〇 The manufacturer of integrated circuit products as described in item 8 of the patent scope of Shenyin 22 also includes adjusting the wafer intention I 丨 according to the production limit of each of these batches. Be 11: If the method of patent application No. 8 method, in which the main production schedule outputs the target quantity of wafer offload at the moment. The demand for the integrated circuit product manufacturing standard is an obstacle to the manufacture of the integrated circuit. 12. The integrated circuit product manufacturing method described in item 11 of the scope of application for a patent, wherein the daily quantity of the wafers that the integrated circuit manufacturing plant orders is 誃 1, the production capacity limit, and the main production schedule output target Requires &amp; 'the minimum of the reasonable work-in-progress water level per day. 贝, 13. The manufacturing method of the bulk circuit product as described in item 10 of the scope of patent application, where the output target of the main production schedule needs to be The number of wafer shipment targets in the integrated circuit manufacturing plant at that time plus the number of wafers that have not been reached in the past ^. 14. The method of manufacturing integrated circuit products as described in item 8 of the scope of patent application, wherein the emergency rate is used to evaluate the urgency of each batch of goods, and the emergency rate is calculated according to the following formula: C / R = (MPS date-W / S date) / (predicted cycle time) where 'C / R is the critical rate and the MPS date is the parent date only generated in the production schedule' or the parent date is deducted for a while The punch time, w / S date is the time when the wafer is unloaded, and the predicted cycle time is 09 / or the waiting time when the product is required. door" 200419629 VI. Scope of patent application 1 5 · —A kind of integrated circuit product is manufactured in accordance with the application of the method for manufacturing integrated circuit products. 1 Scope of Item 8 16. A Λ-body two-way formula made by Yiyi * is manufactured according to the method for manufacturing integrated circuit products of the scope of application for patent No. 9 _. 17. —A kind of integrated circuit product is manufactured according to the manufacturing method of integrated circuit product described in Item 10 of the scope of patent application. 18. —A kind of integrated circuit product is manufactured according to the manufacturing method of integrated circuit product described in item 丨 丨 of the scope of patent application. 19. An integrated circuit product manufactured in accordance with the method for manufacturing an integrated circuit product described in item 12 of the scope of patent application. 20 · —A kind of integrated circuit product, which is manufactured according to the manufacturing method of integrated circuit product described in item 13 of the scope of patent application. 3, 21 · —Semiconductor circuit product printing is manufactured according to the method for manufacturing integrated circuit products described in item 14 of the scope of employment benefits. 5 'order 0503-8882TWF (Nl); TSMC2002-0737; yianhou.ptd page 21