TW200418158A - Flip chip package and method of fabrication - Google Patents

Abstract

The present invention fabricates single heat dissipation bump or multiple heat dissipation bumps between the flip chip and the substrate by printing heat dissipation paste on single zone or multiple zones, or fabricate a solder bump having a large area on the working surface of the flip chip die, or fabricate a solder bump having a large area on the working surface of the substrate. The heat dissipation rate of the flip chip package is therefore improved by the large area contact of the chip and the substrate. By applying the present invention flip chip package and method of fabrication on a practical production line, not only the device failures due to over concentrated heat dissipation paths is avoided, the working surface of the chip can sustain higher current and higher thermal stress.

Description

200418158

Field of the Invention Prior Art In recent years, Ik has written notebook computers, personal data assistants (PDAs and mobile phones, miniaturized and highly functional portable devices, and central, processing unit (CPU) and memory modules ( Memory f 0 (ju 1 e) and other functions f hybridization, so that semiconductor processes not only need to develop towards high accumulation, but also must develop towards high density (high density) packaging, so all kinds of light, thin, short, small Packages have been continuously developed. Compared with traditional package structures, flip chip (FC) package structure has the advantages of fast heat dissipation, low inductance, multiple terminals, and chip size. Its application range is due to these advantages It is constantly being expanded, and its usage will grow several times in the next few years. Please refer to Fig. 1. Fig. 1 is a schematic cross-sectional view of the structure 30 of a conventional f 1 ipchip package (FC package). As shown in FIG. 1, the conventional flip-chip packaging structure 30 includes a die 3 2. The die 3 2 has an active surface 34 and a plurality of bonding pads.

Page 6 200418158 V. Description of the invention (2) (die pad (not shown)) is arranged on the active surface 34. The flip-chip package structure 30 further includes a substrate 36, which is a multilayer board. The substrate 36 has an upper surface 38, and a plurality of bump pads (not shown) are disposed on the upper surface. Above 38. The active surface 3 4 of the die 3 2 faces the upper surface 3 8 of the substrate 3 6 during packaging, and the position (s 丨 te) of each bonding pad (not shown) is the position of each bump (not shown). Corresponding. A plurality of solder bumps 4 2 are respectively disposed between each bonding pad (not shown) and each bump (not shown) to provide each bonding pad (not shown) to each bump ( (Not shown). Generally, an undef bump metal lurgy layer (not shown) is included between each bonding pad (not shown) and each solder bump 42. Depending on the needs of the process and component design, it can be used as A bonding layer, a barrier layer, a wetting layer, or a conductive layer. At the same time, the die 32 contains at least one very large scale integration (VLSI) or at least one ultra large scale integration (ULSI) level integrated circuit. It is electrically connected to the board through each of the bonding pads (not shown), the solder bumps 42 and the bump pads (not shown). The flip chip package structure 30 further includes an underfill material (underfill). material) layer 44, the bottom sealing material layer 44 is the gap between the substrate 36 and the die 32 to protect the flip-chip package structure 30.

$ 7 pages 200418158

Affected by the harsh environment, and eliminates the stress at the solder bump 4 2 connection. Above a lower surface 45 of one of the substrates 36, a plurality of solder bal 1 pads 46 are provided, and a plurality of fresh solder balls (30 (16) : 5 & 113) 48. On one of the back faces 47 of the die, a heat sink 49 such as a heat sink, a heat sink fin, or a fan is provided. Μ Please refer to FIG. 2, which is a conventional technique. Flow chart 50 for making a flip-chip package structure. As shown in FIG. 2, a plurality of solder bumps are first fabricated on a wafer (step 52). The wafer is usually a silicon wafer, and It contains a plurality of dies', and each of the dies includes an active surface and a plurality of bonding pads provided on the active surface. A protective layer (not shown) covers the surface of the wafer, and the protective layer (not shown) (Shown) each part of the bonding pad is exposed, so-called making a plurality of solder bumps on the wafer, that is, a solder bump is made above each bonding pad, and a bump intermetal is interposed between the solder bump and the bonding pad. Layer. Then a wafer sawing process ( Step 54), in order to dice each die into a separated state (a plural ity 0; f separate dies), the wafer cutting process further includes a wafer mount process and a wafer saw process. Next, a die bond process is performed (step 56), that is, the active surface of at least one die is placed toward the upper surface of a substrate, and a plurality of bump pads (bumps) are provided on the upper surface of the substrate. It is worth noting that each bonding pad must be aligned with the corresponding bump pad.

Page 8 200418158

5. Description of the invention (4) A reflow (ref 1 0w) process (step 58) is performed to fix the crystal grains on the substrate by using each solder bump. Subsequently, a plasma clean process (step 62) is performed, because after the crystal grains are cut into a separated state, a process of attaching a flux (f 1 ux) is further included to facilitate soldering during the reflow process. Therefore, after the soldering is completed, the electropolymerization cleaning process must be performed to clean the surface of the die and the substrate. Next, an under fi 1 1 process is performed (step 64), and an underfill material is used to fill the gap between the substrate and the die. A curing process is performed (step 66) to cure the bottom sealing material. Then, a ball implant (s 〇 derba 11 m untunting) process is performed (step 68), that is, a plurality of solder ball pads are formed on the lower surface of the substrate, and then under each solder ball pad, respectively A solder ball is formed. Finally, a heat-dissipating device is attached (three-step Λ 弋). The back side of the i-grain is provided with a heat-dissipating device. Seriously, there is a flip-chip package structure 30 of the S-Ti technology, which is very small, that is, because the cross-sectional area of the solder bump is too small. 'At the same time, the bottom sealing material is poor in heat dissipation = often 2 flip-chip packaging structure 3 ° through the active surface of the crystal grains 2 conductive back surface. The main path of heat dissipation caused by 2 bran is through the crystal • Λ in the conventional technology In the flip-chip package structure 3,

200418158 V. Description of the invention (5) A heat dissipation device is installed on the back of the die to avoid the destruction of components due to too late heat dissipation when the heat dissipation path is too concentrated. However, high accumulation and speed are required everywhere. Today, while maintaining high reliability, this design is no longer applicable to many new products. Therefore, how to develop a new flip-chip packaging structure and its manufacturing method to solve the above problems has become a very important issue. SUMMARY OF THE INVENTION The main manufacturing method of the present invention is to increase the heat dissipation characteristics and high availability. The purpose is to provide a flip-chip package structure and a way to dissipate heat from a mounting substrate, so as to provide better high reliability performance. The surface of the chip package is convexly divided and then at least the surface of the grain is cut on one of the most active surfaces of the present invention. The protective layer is divided into preferred embodiments. Each of the joints exposes a metal process and a convexity. The bump intersects the metal layer, and the block intersects one of the heat sinks of each of the grains, and cuts into a separate shape. A plurality of the active surface states are included, and then in the bump pad, the first grain is formed. Uniform package, and a part of each process and at least a wafer cutting of a front side to provide a base, and then to provide a predetermined process with a protective layer covering the bonding to each of the material bumps, one of the substrates and one of the substrates On the main wafer of the crystal grain, a plurality of crystals are arranged on the wafer, and then stacked on top of the bonding pad, and are produced in the area to separate the respective wafers.

Page 10 200418158

V. Description of the invention (6) The moving surface is placed toward the upper surface of the substrate, and each of the bonding pads is in contact with the corresponding bump pad, and finally a reflow process is performed ^ using each solder bump The die is fixed on the substrate. The present invention is to apply one or more blocks of thermal paste to make one or more heat sinks between the wafer and the substrate, or to make large area solder bumps on the working surface of the wafer, or A large area solder bump is made on the substrate surface. The contact between the chip and the large area of the substrate is used to increase the heat dissipation path, thereby achieving the purpose of improving the heat dissipation rate of the flip-chip package structure. When applying the flip-chip packaging structure of the present invention and the manufacturing method thereof in an actual production line, not only can the problem of component destruction caused by too concentrated heat dissipation paths be avoided, but the working surface of the wafer can also bear greater current and thermal stress, and at the same time Can produce flip-chip packaging products with high accumulation, high speed and high reliability. Embodiment Please refer to FIG. 3, which is a schematic cross-sectional view of a flip-chip package structure 1000 in a first embodiment of the present invention. As shown in FIG. 3, the flip-chip package structure 100 includes a die 102, the die 102 has an active surface 104, and a plurality of bonding pads (not shown) are disposed on the active surface 104. on. The flip-chip package structure 100 also includes a substrate 106, which is a multilayer board, and the material constituting the substrate 106 includes ceramic, plastic (P 1 astic), or glass ( g 1 ass). The substrate 1 0 6 has an upper surface

Page 11 200418158

^^ Fulou Zhang 6 pads (not shown) are set on 108, 108, on the upper surface. Product 1 The active surface 1 0 is installed on the temple / say / plate 1 〇2, which is turned toward the base plate 106 on the table rail 4, and the position (site) where it is combined (not shown) is welded to each bump. ί I 112 ^ Zhi Jiu Jiu I 丨 丨 Xian 7Γ) and the bump pads (not shown) to mention the physical connection of the two pads A (not shown) to the bump pads (not shown)

Next, I also includes a bump intermetallic layer (not shown) between each bonding pad (not shown) and each solder bump 1 12. Depending on the needs of the process and component design, I uses ^ as the bonding layer, Barrier layer, wet layer or conductive layer. It is worth noting that at least one heat dissipation bump 113 is provided between the die 102 and the substrate 106 to improve the heat dissipation performance of the flip-chip package structure 1000. Generally, the die 102 includes a core circuit region (not shown) and a non-core circuit region (not shown), and the heat sink 11 ^ can be located in the core circuit. Area (not shown); or located below the #core circuit area (not shown). The heat sink 11 3 is a metal heat sink, such as a tin-silver-alloy heat sink, a tin-lead-alloy heat sink, or a graphite additive heat sink. .

Page 12 200418158 V. Description of the invention (8) At the same time, the "grain 1 102" contains at least one ultra-large integrated circuit or at least one ultra-large integrated circuit with a level above the integrated circuit. A pad (not shown), each solder bump 112, and each bump pad (not shown) are electrically connected to the substrate 106. The flip-chip packaging structure 100 further includes a bottom sealing material layer 11 4. The bottom sealing material layer i 4 fills the gap between the substrate 106 and the die 100 to protect the flip-chip packaging structure 1. 〇〇It is protected from the harsh environment and eliminates the stress of the solder bump i2. On the lower surface 1 15 of the substrate 106, a plurality of solder ball pads 1 1 6 and a plurality of solder ball pads i i 6 Ιίί ball 118 are provided. On the back surface 117 of the wafer 102, a heat sink 119 is provided. Cover IV. Figure 4 is a flowchart of the first method of fabricating a flip-chip in the first embodiment of the present invention ^ ^. As shown in FIG. 4, first, a plurality of solder bumps are made for two or two ί (step 132). The chip usually contains: a main 5 ϋ contains a plurality of crystal grains, and each crystallizer has an active surface and a plurality of piles on the active surface (ΐ Μ Μ Μ 1 一 (not shown) cover) The surface of the wafer, and the protective layer (the joints of the unexposed parts are referred to as being fabricated on the wafer = bump replacement ,; bucket bumps, that is, a solder and a solder bump and a bonding are respectively prepared above each bonding pad). The bumps are interposed between the metal layers. / Half-in: The method of making bumps usually includes the following two methods: The first method is to use a non-electroplating process (electroless process) on each connection.

Page 13 200418158 V. Description of the invention (9) A bump metal layer is formed on the top of the pad, and then a stencil is used for a coating process to print solder on each bump metal layer ( solder). The second method is to first use a sputtering process or a physical vapor deposition process (PVD process) to form a whole layer of the bump intermetallic layer over each bonding pad, and then A patterned photoresist layer is formed over the bump " metal layer, and the patterned photoresist layer includes a plurality of openings (0pening) directly to each of the bump-metal layers, and then a The electroplating process is performed to form each solder bump, and each solder bump fills each of the openings and extends to a portion of the patterned photoresist layer, patterning the photoresist layer, and finally using each solder to press the tongue The etch-down process is performed by removing a portion of the bump mm-the corresponding bump-to-metal layer of the button becomes agitation: each solder bump and a plurality of independent stacked structures are taken.

Next, a coating process is performed (step 134), and (thermal paste) is applied to each die's main service area, government area, X area (predefined area), and at least one predetermined area of the open surface includes a core. Circuit area and a non-eucalyptus, ..., block. Because the general predetermined area of the die can be designed according to the needs of the design, w ^ = the circuit area, so the material of the thermal paste, or the thermal paste provided in the non-core electrical circuit area, can include tin-silver alloy, which is as good as people. Bu constitutes a political object. Gold tin alloy or graphite

200418158 V. Description of the invention (10) Then a wafer dicing process (step 136) is performed to cut each die into a separated state. The wafer dicing process includes an adhesive tape right and a dicing process. Next, a die bonding process (138) is performed, that is, the active surface of at least one die is placed toward an upper surface of a substrate, and a plurality of pads are disposed on the upper surface of the substrate. The value idea is that 'each bonding pad must be aligned with the corresponding bump pad. ‘One more time, the die is fixed to the substrate 144), because a flux-attached pellet and the surface of the substrate are soldered. Filling process of the sealing material (step 1 48) process (step 15 2), and finally attaching a heat dissipation device to complete the reading 'refer to FIG. 5 The second method of manufacturing the package structure on the wafer is no longer the first one described above To repeat. Stream process (step 142) to make use of each solder bump to die. Subsequently, a plasma cleaning process is performed (after the second step is to cut the day into a separated state, it also includes a step to help the soldering process when the reflow process is ordered. Because of the [cleaning process to clean the crystal substrate and the iS step, again,-/ , A plurality of materials. Then a ball planting device (step 154) /, the substrate solder ball pad bonding. The flip-chip package structure is made on the back of one of the dies and is provided on the back. Figure 5 is the present invention & In the flowchart of this method, the flip chip is used to make a plurality of solders. As shown in Figure 5, the first method reveals the ghost (step 16 2). Since the step 132 of making the exposed road is exactly the same, so

Page 15 200418158 V. Description of the invention (11) Then a wafer dicing process (step 164) is performed to cut each die into a separated state. The wafer dicing process also includes the-paste% cloth process and One cutting process. Next, a coating process is performed (step 166). The method is to apply a heat sink paste to at least a predetermined area on an upper surface of a substrate. The predetermined area can be set on the substrate in the core circuit area corresponding to the crystal grains according to the needs of the design; or it can be set on the substrate ^ in the non-core circuit area of the crystal grains. In addition, the material constituting the thermal paste may include tin-silver alloy, tin boat alloy or graphite additive. Next, a sticky crystal process (step 1 68), a reflow process (step 172), a plasma cleaning process (step I74), a filling process (step 176), and a baking process (step 1) are sequentially performed. 7 8), a ball-planting process (step 182), and finally attaching a heat sink (step 184) to complete the fabrication of the flip-chip package structure. The steps 138, I42, 144, 146, 148, 152, and 154 disclosed in the above-mentioned first method are completely the same as those disclosed in the first method, so they will not be described again. From the above, it is known that the manufacturing method of the first embodiment of the present invention is different from the conventional technique in that a thermal paste coating process is performed on the active surface of the die (the first method, that is, FIG. 4) or the upper surface of the substrate ( The second method is to form a heat sink of the present invention in a predetermined area of FIG. 5). 200418158 V. Description of the invention (12) Please refer to FIG. 6. FIG. 6 is a schematic cross-sectional view of a flip-chip packaging structure 2000 according to a second embodiment of the present invention. As shown in FIG. 6, the flip-chip package structure 200 includes a die 202, the die 202 has an active surface 204, and a plurality of bonding pads (not shown) are disposed on the active surface 204. The flip-chip packaging structure 2000 also includes a substrate 206, which is a multilayer board, and the material constituting the substrate 206 includes ceramic, plastic, or glass. The substrate 206 has an upper surface 208, and a plurality of bump pads (not shown) are disposed on the upper surface 208. During packaging, the active surface 2 of the die 202 is oriented toward the upper surface f 0 8 ′ of the substrate 20 6 and the position of each bonding pad (not shown) is relative to the position of each bump pad (not shown). correspond. A plurality of solder bumps 2 丨 2 are provided between each bonding pad (not shown) and each bump pad (not shown) or between the die 2 0 2 and the base plate 2 0 6 to provide The physical connection f from the die 20 2 to the substrate 20 6 It is worth noting that the physical 3 used to provide the die 2 02 to the substrate 2 06 = the glow bumps 212 have the same height, but different Λde 11. Similarly, a bump intermetallic layer (not shown) is also included between each bonding pad (not shown) and each soldering piece 1. Depending on the needs of the manufacturing process ^ ^ ^, it can be used as a bonding layer and a barrier. Layer, wet, moist, and because each fresh material bump has a different area, each bump intermetallic layer also has a different area. The feature of this embodiment is the flip-chip packaging structure

Page 17 200418158 V. Description of the invention (13) contains a large-area bump-metal layer and is provided by a large-area solder bump 212 'between the grain 202 and the substrate 2 06. Large area heat dissipation path, and may be used to provide additional signals (si gna 1), ground (ground), power (power) and even unconnected (NC) terminals. Therefore, there is no need to set a heat sink in the flip-chip packaging structure 2000, but if there is a design need, a heat sink can still be set. In addition, at least one ultra-large integrated circuit or at least one ultra-large integrated circuit included in the t of the crystal grain 202 is passed through the above-mentioned joints (not shown) and solder bumps. The block 2 1 2 and each bump pad (not shown) are electrically connected to the substrate 2 06. The flip-chip packaging structure 2000 further includes a bottom sealing material layer 2 1 4. The bottom sealing material layer 2 1 4 fills the gap between the substrate 2 06 and the die 2 02 to protect the flip-chip packaging structure. 2 0 〇 is protected from the harsh environment, and eliminates the stress at the solder bumps 2 and 2. The lower surface 2 1 5 of the substrate 2 6 is provided with a plurality of solder ball pads 2 1 6 and a plurality of solder balls 2 1 8 located below the respective solder ball pads 2 1 6. On the back surface 2 1 7 of the chip 202, a heat dissipation device 2 1 9 is provided. Please refer to FIG. 7, which is a flowchart of a first method for fabricating a flip-chip package structure according to the second embodiment of the present invention. As shown in FIG. 7, a hybrid bump metal design (hybrid UBM design, step 2 3 1) is first provided. The so-called hybrid bump metal design is to first design the difference in area (size) according to actual needs. Bump-to-metal layer

Page 18 200418158 V. Description of the invention (14) After the production of fresh material bumps, the surface will be automatically formed according to the solder bumps on the surface of the bump-to-metal layer and the zinc material. They are of different sizes and are used as heat sinks. A plurality of solder bumps are then formed on a wafer (step 232). The chip is usually a silicon wafer, and the chip contains a plurality of crystal grains, and each crystal grain includes an active surface and a plurality of bonding pads disposed on the active surface, and a protective layer (not shown) covers the wafer. Surface, and the protective layer (not shown) respectively exposes part of each bonding pad, so-called to make a plurality of solder bumps on the wafer, 77 is to make a plurality of fresh blocks and a plurality of wafers on the wafer according to the mixed bump-metal design. A bump-to-metal layer. Since the method of manufacturing the convex-convex metal layer and the solder bump in this embodiment refers to the previous embodiment, it will be described in detail in the following. It is worth noting that the solder bumps used to provide the physical connection of the dies (not shown) to ^ (not shown) have the same high-second board but different areas. Then, a wafer dicing process (step 2 3 4) is performed to cut each wafer into a separated state, and the wafer dicing process further includes an adhesive 39 ^ dicing process and a dicing process. Then perform a sticky crystal process (step 2 3 6) / that is, the active surface of at least one die of 9 is placed toward the upper surface of the substrate, and the upper surface is provided with a plurality of bumps. Yes, the pads must be aligned with the corresponding bump pads. Pick up

200418158 --- 5. Description of the invention (15) Another reflow process is performed (step 2 The die is fixed on the substrate. Then enter) 'to use each solder bump to 242), because each die is cut into two Plasma cleaning process (the first step is the process of dipping the flux in order to carry out the 垴 = off state and also include this. After the soldering is complete, this process must be performed to help the welding due to the particles and the surface of the substrate. Then, one filling and two cleanings are performed. The process is to fill the substrate and the die with a clean sealing material (step 244), and a bottom I process (step 246) to solidify the seal / gap at the bottom. Then, a baking process is performed. Step 248) In the process, a plurality of solders are placed. Then, a ball is implanted and a heat sink is attached (step 252). 7 The substrate solder ball is bonded. The heat sink is used to complete the flip-chip packaging structure. Refer to Figure 8 for setting one. Figure 8 is the first method of the apricot package structure of the present invention, and the original ti J. In the embodiment, a flip-chip two supply is made. ， 工 ❻J convex ： Metal design can refer to this The first embodiment is described in: W. Then proceed-wafer cutting! Dagger = glue; process and-cutting system Γ Then, according to RR, metal S and juice, a plurality of solder bumps are made on a substrate. 'Because the bump-metal layer and the solder Λ 乂 are produced in this embodiment, too, you can refer to the previous embodiment, so I will not repeat them here. ㈡ = Fang: Each: display) to the substrate; not shown) = Pick up. Condylar bumps have the same height but different areas. Take page 20, 200418158. 5. Description of the invention (16) A die bond process (step 2 6 8) is performed, that is, the active surface of at least one die is placed toward the upper surface of the substrate, and each joint is bonded. The pads must be aligned with the corresponding bump pads. Next, a sticky crystal process (step 268), a reflow process (step 2 72), a plasma cleaning process (step 274), a filling process (step 2 7 6), and a baking process are sequentially performed. Step 2 7 8), a ball-planting process (step 282), and finally attaching a heat sink (step 284) to complete the fabrication of the flip-chip package structure. Since the above manufacturing method is exactly the same as the steps 236, 238, 242, 244, 246, 248, and 252 disclosed in the first method, it will not be described again. It can be known from the above that the manufacturing method of the second embodiment of the present invention is different from the conventional technology in that a mixed bump-metal design is provided first, and then a fit is formed on the active surface of the grain (the first method, FIG. 7). After a solder bump of this design is provided, a mixed bump-metal design is provided, and then a solder bump matching this design is formed on the upper surface of the substrate (second method, FIG. 8). In short, the present invention uses a method of applying one or more blocks of thermal paste, or a method of making a large area of solder bumps on the working surface of a wafer, or a method of making a large area on the working surface of a substrate. Solder bumps to increase the area of heat dissipation. When applying the flip-chip packaging structure of the present invention and the manufacturing method thereof, an actual production line can be produced

Page 21 200418158 V. Description of the invention (17) Flip-chip package products with high accumulation, high speed and high reliability. Please refer to FIG. 9, which is a schematic diagram of the distribution of the heat sink 308 in the present invention. As shown in FIG. 9, a plurality of heat sinks 308 are disposed in one of the non-core circuit areas 306 of a die 300. However, as mentioned above, the heat sink 3 0 8 can also be arranged in the core circuit area 3 0 4 of the die 3 2 (not shown). Compared with the conventional heat dissipation method of a flip-chip package structure, the present invention uses one or more heat dissipation pastes to make one or more heat dissipation blocks between the wafer and the substrate, or the wafer. Large-area solder bumps are produced on the working surface, or large-area solder bumps are produced on the working surface of the substrate. The contact between the chip and the large area of the substrate increases the heat dissipation path to improve the heat dissipation rate of the flip-chip package structure ( heat dissipation rate). In this way, not only can avoid the problem of component damage caused by too concentrated heat dissipation paths, but also the wafer working surface can withstand greater current and thermal stress, thereby improving the electrical performance of the package at high temperatures and Reliability. The above description is only a preferred embodiment of the present invention, and any equivalent changes and modifications made in accordance with the scope of the patent application of the present invention shall fall within the scope of the patent of the present invention.

Page 22 200418158 Brief description of the diagram Brief description of the diagram: Figure 1 is a schematic cross-sectional view of a conventional flip-chip package structure. FIG. 2 is a flowchart of manufacturing a flip-chip package structure in the conventional technology. FIG. 3 is a schematic cross-sectional view of a flip-chip package structure according to the first embodiment of the present invention. FIG. 4 is a flowchart of a first method for fabricating a flip-chip package structure in the first embodiment of the present invention.

FIG. 5 is a flowchart of a second method for fabricating a flip-chip package structure in the first embodiment of the present invention. FIG. 6 is a schematic cross-sectional view of a flip-chip package structure according to a second embodiment of the present invention. FIG. 7 is a flowchart of a first method for fabricating a flip-chip package structure in the second embodiment of the present invention. FIG. 8 is a flowchart of a second method for fabricating a flip-chip package structure in the second embodiment of the present invention. FIG. 9 is a schematic diagram showing the distribution of heat dissipation blocks in the present invention. Explanation of symbols in the figure: flip-chip package structure die active surface of die substrate

30, 100, 200 32, 102, 202 34, 104, 204 36, 106, 206

Page 23 200418158 Brief description of the drawings 38, 108, 208 42, 112, 212 113 44, 114, 214 45 '115 46, 116, 216 47, 117, 217 48, 118, 218 49, 119, 219 50 ~ 130 ~ 52 ~ 132 ~ 134, 166 54, 136, 56 ^ 138 > 58, 142 '62, 144, 64, 146, 66, 148, 68' 152 ~ 72, 154, 23 262 266 302 304 160 ^ 162, Perform 164, 168, 172 ~ 174, 176 ~ 178-182, 184 'mixed on a die substrate upper surface solder bump heat sink bottom sealing material layer substrate lower surface solder ball pad die back solder ball heat dissipation device flow chart 2 3 2 Make a plurality of coating processes on a wafer, perform a wafer dicing process, perform a die attach process, perform a reflow process, perform a plasma cleaning process, perform a filling process, perform a baking process, and attach a ball planting process. A plurality of solder bumps are fabricated on a UBM design substrate of a heat sink 234 236 238 242 244 246 248 252 264 268 272 274 276 278 282 284 Core circuit area

200418158 Brief description of the diagram 3 0 6 Non-core circuit area 3 08 Heat sink IIHI] Page 25

Claims (1)

200418158 6. Scope of Patent Application 1. A manufacturing method of flip chip (FP) package structure with excellent heat dissipation performance, the manufacturing method includes the following steps: ^ Provide a wafer The wafer includes a plurality of dies, each of which includes a plurality of die pads disposed on an active surface of one of the dies, and a protective layer ( passivation layer) covers the surface of the wafer, and the protective layer & do not expose each of the bonding pads; An under bump metallurgy process and a bumping process are performed to form an under bump metallurgy layer above each bonding pad and a solder bump (solder bump) ); Making at least one heat dissipation bump in at least one predefined area of the active surface of each die; and performing a wafer saw process to separate each of the A dice is cut into a plurality of separate dies; a substrate is provided, and an upper surface of one of the substrates includes a plurality of bump pads; and at least one of the dice is The active surface is placed toward the upper surface of the substrate, and the solder bumps are brought into contact with the corresponding bump pads; and a ref low process is performed to fix and electrically connect the crystal grains. connection Page 26 200418158 6. The scope of patent application is on the substrate. 2. For the manufacturing method of item 1 of the application scope, wherein the die includes a core circuit region (cor ecir cu itr eg i on) and a non-core circuit region, and the predetermined region is set Within the core circuit area. 3. For the manufacturing method of item 1 of the application scope, wherein the die includes a core circuit area and a non-core circuit area, and the predetermined area is disposed within the non-core circuit area. 4. For example, the manufacturing method of the scope of patent application, wherein the method of manufacturing the heat dissipation block is to apply a thermal paste within the predetermined area. 5. The manufacture of the scope of patent application, the fourth category Method, wherein the material constituting the heat dissipation paste includes tin-silver-alloy, tin-lead-alloy, or graphite additive The manufacturing method of item further includes the following steps after performing the reflow process: performing a filling (underfi 1 1) process, filling a bottom sealing material (underfi 1 1 materia 1) between the substrate and the die Null 200418158 VI. Patent application gap; a curing process is performed to cure the bottom sealing material. 7. The manufacturing method of item 1 of the scope of patent application, which further includes a solder ball mounting process. 8. The manufacturing method according to item 1 of the scope of patent application, further comprising providing a heat sink on a back side of the die. 9. A manufacturing method of a flip-chip package structure with excellent heat dissipation characteristics, the manufacturing method includes the following steps: a wafer is provided, the wafer includes a plurality of crystal grains, and each of the crystal grains includes a plurality of crystal grains provided on the crystal wafer; A bonding pad on an active surface of the chip, and a protective layer covering the surface of the wafer, and the protective layer respectively exposes a part of each of the bonding pads; a bump-to-metal process and a bump process are performed for each bonding A bump intermetallic layer and a solder bump stack are formed above the pads, respectively; Performing a wafer dicing process to cut each of the crystal grains into separated pieces, providing a substrate, one of which has a plurality of bump pads on an upper surface thereof; at least one predetermined area on the upper surface of the substrate Produced at least Page 28 200418158 VI. Patent application scope-heat sink; Place the active surface of at least one die toward the upper surface of the substrate, and make each solder bump correspond to the corresponding bump pad. Making contact; and performing a reflow process to fix the die and electrically connect the die to the substrate. 1 0 · The method of making item 9 of the scope of application, wherein the die includes a core circuit area and a non-core circuit area, and the predetermined area is disposed on the substrate corresponding to the core of the die. Within the circuit area. 11 · According to the manufacturing method of item 9 of the application scope, 1n has a core circuit area and a non-nuclear power square core area which are arranged on the substrate opposite; the ft ^ s f domain, and the predetermined area m. Corresponding to the non-core circuit i 2 of the die, as in the method for making item 9 of the scope of patent application, the method of bean pieces is to apply heat dissipation paste in the predetermined area. Make the heat sink in the middle 3. Make the method around the 12th item. The material of the thermal paste ... tin-silver alloy, tin alloy or stone = government Page 29 200418158 VI. Application scope of patent 14. The manufacturing method of item 9 of the scope of patent application, which includes the following steps after the reflow process is performed: A filling process is performed to fill the substrate with a bottom sealing material And a gap between the crystal grains; and performing a baking process to cure the bottom sealing material. 15. The manufacturing method according to item 9 of the patent application scope, which further includes performing a ball planting process. 16. The manufacturing method according to item 9 of the scope of patent application, further comprising providing a heat sink on the back of one of the dies. 1 7. A manufacturing method of a flip-chip package structure having excellent heat dissipation characteristics, the manufacturing method includes the following steps: a wafer is provided, the wafer includes a plurality of crystal grains, each of the crystal grains includes a plurality of crystal grains provided in A bonding pad on an active surface of the die and a protective layer covering the surface of the wafer, and the protective layer respectively exposes a part of each of the bonding pads; a hybrid bump metal (hybrid U B Μ) is used to design A plurality of bump-metal layers with different areas are formed on the wafer; a solder bump having an area corresponding to each of the bump-metal layers is formed on each of the bump-metal layers; and a wafer cutting process is performed. 'To cut each of the grains into a separated state; 200418158 6. The scope of the patent application provides a substrate, one of which has a plurality of bump pads on its upper surface; the active surface of at least one of the grains is placed toward the upper surface of the substrate, and each of the solder The bumps are in contact with the corresponding bump pads; and a reflow process is used to fix and electrically connect the die to the substrate; wherein the solder bumps with a larger area are used to provide the wafers. And the large area of the substrate, thereby increasing the heat dissipation rate of the flip-chip package structure. 18. The manufacturing method according to item 17 of the scope of patent application, further comprising the following steps after the reflow process is performed: a filling process is performed, and a bottom sealing material is used to fill a gap between the substrate and the crystal grains And performing a baking process to cure the bottom sealing material. 19. The manufacturing method of item 17 in the scope of patent application, which further includes performing a ball planting process. 20. The manufacturing method according to item 17 of the scope of patent application, further comprising disposing a heat sink on the back of one of the dies. 2 1, —manufacturing method of flip-chip packaging structure with excellent heat dissipation characteristics Page 31, 200418158 6. The patent application method, the manufacturing method includes the following steps: Provide a wafer 'the wafer contains a plurality of crystal grains', each of which includes a plurality of active surfaces provided on one of the crystal grains A bonding pad and a protective layer covering the surface of the wafer, and the protective layer respectively exposes a part of each of the bonding pads; a mixed bump metal design is used to form a plurality of bump media of different areas on the wafer. A metal layer; performing a wafer cutting process to cut each of the crystal grains into a separated state; providing a substrate, one of which includes a plurality of bump pads on an upper surface thereof; and forming a plurality of areas on the substrate, respectively A solder bump corresponding to each of the bump-to-metal layers; placing the active surface of at least one of the grains toward the upper surface of the substrate, and causing each of the solder bumps to correspond to each of the bump-to-bumps The metal layers are in contact with each other; and a reflow process is performed to fix and electrically connect the die to the substrate; wherein the solder bump having a larger area is used to provide the die and The large area contact of the substrate further improves the heat dissipation rate of the flip-chip package structure. 2 2. The manufacturing method according to item 21 of the patent application scope, further comprising the following steps after performing the reflow process: Page 32 200418158 VI. Scope of patent application A filling process is performed to fill a gap between the substrate and the crystal with a bottom sealing material; and a baking process is performed to solidify the bottom sealing material. 2 3. The manufacturing method according to item 21 of the scope of patent application, which further includes performing a ball planting process. 24. The manufacturing method according to item 21 of the patent application scope, further comprising providing a heat sink on the back of one of the dies. 2 5. A flip-chip package structure with excellent heat dissipation characteristics, the package structure includes: a substrate, the substrate has a plurality of bump pads on an upper surface; at least one die, the die has A plurality of bonding pads provided on an active surface of the die, and each of the bonding pads corresponds to each of the bump pads; a plurality of solder bumps located between each of the bonding pads and each of the bump pads Block for providing electrical connection between each of the bonding pads and each of the bump pads; and at least one heat sink is disposed between the die and the substrate and is used to provide the die and a large area of the substrate. Contact, thereby increasing the heat dissipation rate of the flip-chip package structure. 200418158 VI. Scope of patent application 26. The structure according to item 25 of the patent application scope, wherein a bump intermetallic layer is further included between each of the bonding pads and each of the solder bumps. 27. The structure according to item 25 of the scope of patent application, wherein the heat sink comprises a tin-silver alloy heat sink, a tin boat alloy heat sink, or a graphite additive heat sink. 28. The structure according to item 25 of the scope of application, wherein the die includes a core circuit area and a non-core circuit area, and the heat sink is located in the core circuit area. 29. The structure of item 25 in the scope of application, wherein the die includes a core circuit area and a non-core circuit area, and the heat sink is located in the non-core circuit area. 30. The structure according to item 25 of the scope of patent application, wherein the heat sink is a solder bump having an area larger than that of other solder bumps. 3 1. The structure of item 25 in the scope of application, wherein the heat sink can be used to transmit a signal. 32. The structure according to item 25 of the scope of patent application, further comprising a bottom sealing material layer filling the gap between the substrate and the crystal grains. Page 34 200418158 VI. Scope of patent application 33. The structure of item 25 of the patent application scope further includes a heat dissipation device arranged on the back of one of the grains. 3 4. The structure according to item 25 of the scope of patent application, which further comprises a plurality of solder balls (s ο 1 d e r b a 1 1) respectively disposed on the lower surface of each substrate. Page 35