TW200417036A - Method for fabricating a thin film transistor liquid crystal display panel - Google Patents

Abstract

An array of scan lines, data line strips, and gate electrodes are defined on a substrate using one mask. The scan lines and the data line strips are in same plane. Each of the data line strip is disposed between two adjacent scan lines in a substantially orthogonal manner with a distance from the scan lines thereof. Thereafter, a dielectric layer, a semiconductor layer, and an etching stop layer are sequentially formed over the array of scan lines and data line strips. A heavily doped amorphous silicon layer is deposited and then partially etched to form an active area over each of the gate electrodes. Two contact holes are formed on portions of the data line strips on two opposite sides of a scan line. A transparent conductive layer is deposited to fill the contact holes, thereby electrically connecting the data line strips across the scan lines.

Description

200417036 V. Description of the invention (l) Technical field to which the invention belongs The present invention provides a thin film transistor liquid crystal display (T h i n F i 1 m

Transistor Liquid Crystal Display (TFT-LCD) panel manufacturing method, especially a TFT-LCD panel manufacturing method in which scanning lines and data lines are defined with the same mask so that they are located on the same plane, thereby avoiding short-circuiting of the scanning lines / data lines . With the rapid development of the electronic information industry in the past, the application range and market demand of liquid crystal displays (LCDs) are also constantly expanding, from small products such as electronic blood pressure monitors to portable information products such as Personal digital assistants (PDAs), notebook computers (notebooks), and even large-screen displays that are about to be commercialized in the future, can be seen in liquid crystal displays are widely used. This is because the structure of the liquid crystal display is very thin, short and small, and it also has the advantage of no radiation pollution. The conventional thin film transistor liquid crystal display basically includes a transparent substrate having thin film transistors arranged in an array, pixel electrodes, and scanning lines (sca η 1 ine) located on different planes. And data line (data 1 ine), a color filter, a color filter and a liquid crystal material filled between the transparent substrate and the filter plate, and cooperate with appropriate capacitors, connection pads and other electronic components to

200417036 V. Description of the invention (2) ___ Move the liquid crystal pixels to produce rich and beautiful ones. When the thin film transistor liquid crystal display is used, the scan time is too high. At the same time, the production process of the liquid crystal display device or man-made factors causes the daily production of πα to produce point defects or line defects. Please refer to Figure 1. Figure 1 is the conventional tftlcd 3 j. 7 and data line 36 are defined in different planes: and ΐ Λ ^ the transistor source 34 needs to pass through a via hole = electricity. Formed during the process) and the pixel electronics master refer to FIGS. 2A to E, and FIGS. 2A to E are the cross-sections of the conventional fabrication of a TFT LCD. As shown in FIG. 2A, the conventional method for making a few panels is to first deposit a first metal layer on the surface of the glass substrate 11, and then perform a first yellow light and etching process on the glass substrate. A gate electrode 16 and a scan line 18 passing through the staggered region 4 are formed on the surface of the transistor region 12 respectively. As shown in FIG. 2b, a gate insulator 22, a semiconductor layer 24, and an etch stop layer 26 are sequentially deposited on the glass substrate u in order, and a second yellow light and The etching process is used to define the etch stop layer 26, and the purpose of forming the etch stop layer 2 6 is to protect the semiconductor layer 2 4 from being broken by the subsequent surname process.

200417036

Bad aggression. The upper part of 2 6 The upper part defines the area. As shown in fossil or nitrogen and a protective layer hole 41 (on the glass substrate ITO) or bright conductive layer source 34 as shown in FIG. 2F, then the semiconductor layer 24 and the etch stop layer are stacked with N The doped semiconductor layer 28 is followed by a second metal layer on the doped semiconductor layer, and a third yellow light and etching process is performed on the data line 36, the drain 32, the source 34, and the active. As shown in D, a passivatioI1 layer 38 consisting of oxite is then formed on the glass substrate. The fourth yellow light and etching process is performed, and the removed portion is located above the source electrode 3 8 'for the protective layer. In 38, a source is formed up to the surface of the source 34, and a part of the source 34 is exposed. Finally, as shown in Figure 2E,

A transparent lens made of indium tin oxide (indium zinc oxide, indium zinc oxide, IZ) is deposited on top of 11 and a fifth yellow light and money engraving process is performed to form a sexually connected pixel. Electrode (pixel electrode) 42. From the above, it can be known that the method of manufacturing the conventional TFTLCD panel is to use the data line 3 6 and the sweep line 18 to alternately arrange the structure on different planes. In addition, the conventional method of manufacturing a TFT LCD panel requires Carry out the yellow light and etching process five times. Therefore, the thin film transistor liquid crystal display is very easy to affect the production yield due to various defects. And when the size of the liquid crystal panel produced is getting larger and larger, this kind of problem will become more serious. Especially It is near the staggered area where the data line and the scan line pass at the same time, and the vicinity of the thin film transistor area. Often, the scan line or gate electrode located at the lower layer is not good enough in shape, and the scan line or gate line (gate 1 ine) is not good enough. Undercut phenomenon, metal eruption phenomenon, and semiconductor layer and gate insulation layer

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V. Explanation of the invention (4) Unexpected contamination particles (the scan line i data is generated after the layer is layered) [12] The specific factor is the second gold short deposition. From the above, we can see that the two-two-two-signal theory is still waiting to be further improved in the production steps, process yield and production technology. The production structure is not ideal, and therefore, the number of TFTLCD panel design processes is used to avoid problems such as reducing the deposition or etching maintenance-fixed production problems such as shorting of data lines, etc. question. In order to make an important lesson when making a TFTLCD panel, 0 is mainly to provide—a kind of TFTLCD panel production method to avoid: the scanning lines and data lines of the board are defined in the same i: to avoid the intersection of drawing lines / data lines The occurrence of short-term failures does not require the same method of manufacturing the TFTLCD panel. In addition, the present invention can simplify the manufacturing steps, which includes a metal layer and a guarantee ratio. Intermediate I ^ steps, significantly improve the process efficiency and in accordance with the preferred embodiment of the present invention, first provide a sub-pixel region, a " '' soil fb: ΐΓ: two areas and A scan line / data line staggered area. First deposit a metal layer on the surface of the substrate to perform a first yellow light and etching 200417036 V. Description of the invention (5) Photo-etching-process (PEP), define a scan line and a A discontinuous data line that is not in contact with the scanning line, and a gate of the thin film transistor is formed in the transistor region, and then a gate insulator and a semiconductor layer are sequentially deposited. semi conductor layer) and an etching stop layer, followed by a second yellow light and etching process, removing the etching stop layer outside the transistor area and the scan line / data line staggered area, and then depositing a highly doped layer A heavy doped semiconductor layer, and a third yellow light and etching process is performed to form an active region of the thin film transistor, and then a fourth yellow light and etching process is performed. A contact hole is formed in the gate insulating layer on both sides, exposing part of the data lines on both sides of the scanning line, and then a transparent conducting layer (transparent conducting laye) is deposited. r) and fill the contact hole to bridge the data lines on both sides of the scan line, and finally perform a fifth photolithography and etching process to form a pixel electrode, a source, and a drain 'And connect the data line to the source. Because the TFTLCD fabric line of the present invention is placed on the same plane, that is, the scan line and the scan line are defined at that time, then the transparent conductive layer is used for a metal deposition process and a short circuit in the protection area. Further, the manufacturing method is The scanning line and the first yellow light and etching process, that is, the discontinuous data lines that are not in contact with each other, are connected to the material line. This can not only reduce the process of layer deposition, but also avoid staggering and improve production yield.

Page 10 200417036 V. Description of the invention (6) In order to allow your reviewers to further understand the features and techniques of the present invention, please refer to the following detailed drawings of the present invention = The drawings are for reference and explanation only. It is not used to send = to: The implementation method is full. Please refer to Figure 3. Figure 3 is a part of the layout of the TFTLCD panel of the present invention. L: J month system, using five road yellow light and #etching process in a transparent glass. The base 1 forms a tftlcd system 100, in which the glass substrate is also a stone substrate or a plastic substrate. As shown in FIG. 3, the present invention is characterized in that the scanning line 102 and the data line 104 of the TFT LCD are located in the same plane and vertical arrangement, but do not touch each other in the interlaced area 118, but use the same type. The IL-type transparent conductive layer I32 is bridged through the contact hole 138, and the L · type, moon-conductive layer 1 32 is electrically connected to the drain electrode of the thin film transistor. Like =, \ 14, and ^ are electrically connected to the source of the thin-film transistor 108 without going through any holes. Here, the pixel electrode 114 and the L-shaped transparent conductive layer ι32 are defined by a transparent conductive material. Please refer to FIGS. 4A to E. FIGS. 4A to E are schematic cross-sectional views of a TFT LCD panel manufacturing process according to a preferred embodiment of the present invention. First, as shown in FIG. 4A, a metal layer is deposited on the surface of the glass substrate 101, and then a first yellow light and etching process is performed. The metal layer is defined on the surface of the glass substrate 10 to form a plurality of strips. Scan line 1 〇2 (within area 1 1 8), plural

Page 11 200417036 V. Description of the invention (7) Discontinuous data line segments (data 1 ine 86〇1: 1〇11〇 "(13 7 8 11 116 31: 1 " 1 mouth) 104 which are not in contact with the scanning line 104 (Located in area 112), and a gate electrode 106 (located in area 116). The gate electrode 106 is connected to a corresponding scanning line. Each data line segment 104 is located in two The adjacent scanning lines are arranged orthogonally to the scanning lines on the same plane (see Figure 3). For convenience, the area 116 is called the transistor area, and the area 1 12 is called the contact hole area. The area 1 丨 8 is called the staggered area. In the subsequent process, the data line segments 104 located on both sides of a scanning line will be electrically connected to each other through a transparent conductive layer and a contact hole through the intersection area 1 18 to Form $ = line and data line array. The metal layer may be a single metal layer or / is a composite metal layer. If it is the former, the material constituting the metal layer & Indium alloy. If it is the latter, it constitutes the multilayer gold ^ = two $ mainly composed of aluminum (A1) or a combination of aluminum as the main component The upper layer I material contains an alloy of titanium (Ti), chromium and molybdenum, or a tungsten-molybdenum alloy 9 as shown in FIG. 4B, and then is sequentially deposited on a glass substrate 101-a gate insulator. 124. A semiconductor layer L, a semiconductor 1 ayer 1 2 6 and an etch stop layer 128, and perform a second yellow light and etch the crystal region 1 1 6 region and the staggered region 1 1 The etch stop layer other than 8 and the two electrode removal insulating layers 124 may be a single dielectric layer or 9 is a composite dielectric gate, composed of silicon oxide (SiOx), nitride = It is composed of silicon oxynitride (SiOxNy). The semiconductor layer i26 is also called active layer 1Ny) or (act ive layer), which is an amorphous silicon layer containing hydrogen.

200417036 V. Description of the invention (8) Use of the channel when the membrane transistor is turned on. As shown in FIG. 4C, a highly doped semiconductor layer 130 is then deposited to provide an ohmic contact between the semiconductor layer 12 6 and a subsequently deposited transparent conductive layer to reduce resistance, and A third yellow light and etching process is performed to define the active area of the thin film transistor. In the third yellow light and etching process, except for the highly-doped semiconductor layer 130 in the transistor region 116, the highly-doped semiconductor layer 130 in other regions is removed. As shown in FIG. 4D, a fourth yellow light and etching process is then performed. In the gate insulating layer 1 2 4 on both sides of the scan line 10 2, a contact hole 1 3 8 is formed above the data line segment 104. The data line segments 1 0 2 on both sides of the exposed scanning line 10 are exposed as shown in FIG. 4E. Finally, a transparent conductive layer 132 is deposited and filled in the contact hole 1 38 to bridge the scanning line 1 0. 2 data line segments 104 on both sides, and then a fifth yellow light and etching process is performed to define pixel electrodes 1 1 4 which are directly electrically connected to the source electrode 108, and electrically connected to the drain electrode 1 1 0 and the data line segment 1 〇4, and pass through the L-shaped transparent conductive layer 132 of the staggered region 118. The transparent conductive layer 132 may be made of indium tin oxide (ITO) or indium zinc oxide (IZO). In order to further understand the TFTLCD manufacturing method of the present invention and the conventional technology,

Page 13 200417036 V. Description of the invention (9) For differences, please refer to Figure 5. FIG. 5 is a comparison diagram of a TFTLCD manufacturing process of the present invention and a conventional TFTLCD manufacturing process. The manufacturing process of the conventional TFTLCD is described as follows: Step 501: depositing the first metal layer; step 502: defining the scan line and the gate electrode by using the first yellow light and etching process; step 503: continuously depositing the gate insulating layer / Semiconductor layer / cut stop layer; Step 504: Define an etch stop layer with the second yellow light and etching process; Step 505: Deposit a highly doped semiconductor layer; Step 506: Deposit a second metal layer; Step 5 0 7 : Define the data line, source, drain, and active area with the third yellow light and etching process; step 508: deposit a protective layer; step 509: define the contact hole with the fourth yellow light and etching process; Step 5 1 0: deposit a transparent conductive layer; Step 5 1 1: define the pixel electrode by the fifth yellow light and etching process; and the manufacturing process of the TFTLCD of the present invention is described as follows: Step 521: deposit a first metal layer; Step 5 2 2: Define the scan line, gate, and discontinuous data lines that are not in contact with the scan line using the first yellow light and etching process; Step 5 2 3: Continuously deposit the gate insulation layer / semiconductor layer / remaining stop layer;

Page 14 200417036 V. Explanation of the invention (ίο) Step 5 2 4: Define the etching stop layer by the second yellow light and etching process; Step 5 2 5: Deposit a highly doped semiconductor layer; Step 5 2 6 ··· Three yellow light and etching processes define the active area; Step 5 2 7: Define the contact hole with the fourth yellow light and etching process; Step 5 2 8: Deposit a transparent conductive layer; Step 5 2 9: Use the fifth yellow light The etch process defines a source electrode, a drain electrode, a channel region, and a pixel electrode, and a discontinuous data line is bridged through a contact hole. Compared with the conventional technology, the present invention is in the first yellow light etch process, and The scan line and discontinuous data line segments are defined, that is, the scan line and the data line are in the same plane, and the contact hole 1 3 8 is subsequently etched in the gate insulating layer 1 2 4 in the contact hole area 11 2. An L-shaped transparent conductive layer 1 3 2 is used to bridge the data line segments 104 on both sides of the scanning line 10 2 and the source electrode 110 of the thin film transistor, so that not only can a metal deposition process and a protective layer be simplified in manufacturing Deposition process, and can avoid short circuit in staggered area. Improve process performance and yield. The above are only the preferred embodiments of the present invention. Any equivalent changes and modifications made in accordance with the scope of the patent application for the present invention shall fall within the scope of the patent of the present invention.

Page 15 200417036 Simple illustration of the diagram Simple illustration of the diagram Figure 1 is a top view of the layout of a conventional TFTLCD. Figs. 2A to E are schematic cross-sectional views of a conventional TFT LCD. FIG. 3 is a top view of the layout of a TFT LCD of the present invention. 4A to 4E are schematic cross-sectional views of a TFT LCD manufactured by the present invention. FIG. 5 is a comparison diagram of the TFTLCD manufacturing process of the present invention and the conventional technology. Symbol description

10 TFTLCD system 11 glass substrate 12 transistor region 14 staggered region 16 gate electrode 18 scan line 22 gate insulation layer 24 semiconductor layer 26 etch stop layer 28 highly doped semiconductor layer 32 drain 34 source 36 data line 38 protective layer 40 transparent conductive layer 41 via hole 42 pixel electrode 100 TFTLCD system 101 glass substrate 102 scan line 104 data line 106 gate electrode 108 source electrode 110 drain electrode 112 contact hole region 114 pixel electrode

Page 16 200417036 Brief description of the diagram 116 transistor region 118 staggered region 1 2 4 gate insulating layer 1 2 6 semiconductor layer 128 etch stop layer 130 highly doped semiconductor layer 1 3 2 transparent conductive layer 1 3 8 contact hole 501 deposition First metal layer 502 First yellow light and etching process 5 0 3 Sequentially deposit gate insulation layer / semiconductor layer / etch stop layer 5 0 4 Second yellow light and etching process 505 deposit highly doped semiconductor layer 5 0 6 Deposit second metal layer 5 0 7 Third yellow light and etching process

5 0 8 Deposit protective layer 509 Fourth yellow light and etching process 5 1 0 Deposit transparent conductive layer 5 1 1 Fifth yellow light and etching process 521 Deposit first metal layer 522 First yellow light and etching process 5 2 3 Sequential deposition of gate insulation layer / semiconductor layer / stop stop layer 5 2 4 second yellow light and etching process 525 deposition of highly doped semiconductor layer 5 2 6 third yellow light and etching process

527 Fourth yellow light and etching process 528 Deposition of transparent conductive layer 5 2 9 Fifth yellow light and etching process

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Claims (1)

200417036 VI. Application Patent Scope 1. A method for manufacturing a thin-film transistor liquid crystal display panel, comprising the following steps: providing a substrate on which a metal layer is deposited, the substrate including a transistor region, a staggered region, and a The contact hole area, in which the transistor area forms a thin film transistor, performs a first yellow light and money engraving process, defines the metal layer, and simultaneously defines a scan line and two scan lines on the substrate The lean material segments on both sides that are not in contact with the scan line 'and the gate electrode of the thin film transistor; a dielectric layer, a semiconductor layer, and a stop layer are deposited sequentially; a second yellow light and etching are performed Process, removing the moment stop layer outside the transistor region and the staggered region; depositing a highly doped semiconductor layer; performing a third yellow light and etching process to remove the highly doped semiconductor layer outside the transistor region Performing a fourth yellow light and etching process to form a contact hole in the dielectric layer, exposing part of the data line segments on both sides of the scan line; and Shen Jiyi a transparent guide Layer, and filling the contact holes. 2. The manufacturing method according to item 1 of the scope of patent application, wherein the substrate comprises a glass substrate, a quartz substrate or a plastic substrate. 3. The manufacturing method described in item 1 of the scope of patent application, wherein the first metal layer is a single-layer metal structure and the material constituting the first metal layer Page 18 200417036 6. Scope of patent application Contains chromium (Cr), thorium (M0) or tungsten-rhenium alloy (MoW alloy). 4 · The manufacturing method described in item 1 of the scope of patent application, wherein the metal layer is a multilayer composite metal structure, and the material constituting the multilayer metal structure includes an inscription (A1) or an inscription alloy, copper (Cu) or Copper alloy. 5. The manufacturing method as described in item 1 of the scope of the patent application, wherein the dielectric layer is a gateinsu 1 ating (GI) layer, and includes silicon oxide (Si 0X) and nitride nitride (si Ny) or oxynitride (SiON). 6. The manufacturing method as described in item 1 of the scope of the patent application, wherein the semiconductor layer is an amorphous silicon layer (amorphous silicon layer, a -Si layer), a polycrystalline silicon evening layer (p〇iCryStai siiicon iayer) or single-crystal silicon layer. 7 The manufacturing method as described in item 1 of the scope of patent application, wherein the rest stop layer is made of silicon nitride. 8. The manufacturing method as described in item 1 of the scope of patent application, wherein the transparent conductive layer is composed of indium tin oxide (ITO) or indium zinc oxide (IZO). 9 · The production method described in item 1 of the scope of patent application, wherein the information Page 19 200417036 6. Scope of patent application The line segment and the scanning line are on the same plane. 10. The manufacturing method as described in item 1 of the scope of patent application, wherein the data line segment is bridged by the transparent conductive layer in the interlaced area. 11. The manufacturing method according to item 1 of the scope of patent application, wherein in the second yellow light and etching process, the etch stop layer in the staggered region can be removed. 12. The manufacturing method as described in item 1 of the scope of patent application, wherein in the third yellow light and etching process, the highly doped semiconductor layer in the staggered region may be retained. 13. The manufacturing method as described in item 1 of the scope of patent application, wherein the data line is bridged by the transparent conductive layer in the staggered area. 14. The manufacturing method described in item 1 of the scope of patent application, wherein the transparent conductive layer is deposited, and the manufacturing method further includes: performing a fifth yellow light and etching process to define a direct electrical connection to the thin film transistor The pixel electrode of the drain electrode and the source electrode of the thin film transistor and the data line segment are electrically connected and pass through a transparent conductive layer of the interlaced region. Page 20