TW200416446A - Pixels of in-plane switching LCD and manufacturing process - Google Patents

Pixels of in-plane switching LCD and manufacturing process Download PDF

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TW200416446A
TW200416446A TW92103846A TW92103846A TW200416446A TW 200416446 A TW200416446 A TW 200416446A TW 92103846 A TW92103846 A TW 92103846A TW 92103846 A TW92103846 A TW 92103846A TW 200416446 A TW200416446 A TW 200416446A
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TW92103846A
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Hong-Da Liu
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Hong-Da Liu
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Abstract

The present invention discloses pixels of in-plane switching (IPS) LCD and manufacturing process of the same whose reflector provides nano scale surface roughness to scatter light source and raise contrast. Because the coarse surface is of nano scale, the scattering effect aspect will have greater scattering angle and smoothing effect. Even if the reflection won't vary dramatically with view angle, good anti-flare effect can still be obtained. Furthermore, the rough surface is formed by utilizing the relation between crystallization of material characteristics without additional mask.

Description

200416446 五、發明說明(1) 發明領域 本發明係有關一種橫向電場液晶顯示器,特別是關於 一種具有奈米級粗糙面反射板之橫向電場液晶顯示器的畫 素及製程。 發明背景 在習知技術中,液晶顯示器(1丨q u i d c r y s t a i display ;LCD)係使用TN模式及stn模式,然而,TN模式及 STN模式的LCD具有視角狹窄的缺點,因此,有人提出一種 具有廣角之橫向電場(in-plane switching ; lps) , 該I P S模式L C D除了具有廣視角外,還具有不須補償膜以及 響應時間快等優點,且其製程比T N模式L C D少一道光罩, 但疋’該IPS模式LCD的畫素電極(pixei eiec^r〇(je)及共 電極(counter electrode)係由不透光金屬所製成且具有 一光滑面,故反射時為鏡面反射,因而降低了對比度,雖 然’可以在該畫素電極及共電極下方形成一由有機材料, 例如’樹脂(r e s i n ),所構成之粗糙面來改善此缺點,然 而’增加該有機材料須要多加光罩數,故會增加製程的複 雜度及成本,且有機材料的耐熱性不佳,約2 5 〇度,此 外’由於該粗糙面的高低落差過大,在〇 5uin到i.5um之, 間’因而造成液晶顯示器的間隙變化過大,使得反射光效 率的降低’由理想的丨〇 〇 %降到6 〇 %〜8 5 %之間。 因此’一種具有奈米級粗糙面且能減少光罩數之橫向 電場液晶顯示器仍為所冀。200416446 V. Description of the invention (1) Field of the invention The present invention relates to a lateral electric field liquid crystal display, and more particularly to a pixel and a process for a transverse electric field liquid crystal display having a nano-level rough surface reflective plate. BACKGROUND OF THE INVENTION In the conventional art, a liquid crystal display (LCD) uses a TN mode and a stn mode. However, the LCDs of the TN mode and the STN mode have the disadvantage of a narrow viewing angle. Therefore, some people have proposed a wide-angle horizontal Electric field (in-plane switching; lps). In addition to the wide viewing angle, the IPS mode LCD also has the advantages of no compensation film and fast response time. The manufacturing process is one less than that of the TN mode LCD. However, the IPS The pixel electrode (pixei eiec ^ r0 (je) and counter electrode) of the mode LCD are made of opaque metal and have a smooth surface. Therefore, the reflection is specular, which reduces the contrast. 'A rough surface made of organic materials such as' resin 'can be formed under the pixel electrode and the common electrode to improve this disadvantage. However,' increasing the number of photomasks for the organic material will increase the manufacturing process. Complexity and cost, and the heat resistance of organic materials is not good, about 250 degrees. In addition, because the height difference of the rough surface is too large, Between uin and i.5um, the gap of the liquid crystal display is changed too much, so that the decrease of the reflected light efficiency is reduced from the ideal 丨 〇% to 60% ~ 85%. Therefore, 'a kind of nanometer A horizontal electric field liquid crystal display that has a rough surface and can reduce the number of photomasks is still desired.

200416446 五、發明說明(2) 發明目的與概述 本發明的目的之一,在於一種具有奈米級粗糙面之橫 向電場液晶顯示器的晝素及製程。 本發明的目的之一,又在於一種減少光罩數之橫向電 場液晶顯示器的畫素及製程。 根據本發明,一種橫向電場液晶顯示器的畫素及製 程,在第一實施例之畫素包括一第一結構在一基底上,具 有一奈米級粗糙面以散射光源及提高對比度,且該第一結 構包含一第一部分及第二部分、一第二結構在該第一部分 上以形成一開關元件、一液晶層在該第二結構及第二部分 上,以及一第三結構在該液晶層上,其中該第二部分係多 個具有該奈米級粗糙面之反射板,該第三結構係一光學疊 層,此外,該液晶層可以是正型或負型液晶。該粗糙面係 因為結晶及材料本身特性的關係而形成,由於該第一部分 與第二部分之反射板係一同製作,故本發明之液晶顯示器 僅須四道光罩,比習知之散亂式液晶顯示器所須之八或九 道光罩少了一半,進而大幅降低成本,而且,由於該粗糙 面係奈米級,故在散亂效果方面會有較大的散亂角度和平 緩的效果,即反射率不隨視角做劇烈變化,也有很好的抗 炫光效果(Anti-glare)。此外,由於該粗韃面的高低落差 比現行散亂式内層反射板之粗糙面的高低落差更小,故能 降低液晶層(1 i q u i d c r y s t a 1 c e 1 1 )間隙的變化,使反射 光效率保持在最佳狀況。該反射板係利用無機薄膜製程來200416446 V. Description of the invention (2) Object and summary of the invention One of the objects of the present invention is a day field element and a process for a horizontal electric field liquid crystal display with a nano-scale rough surface. One object of the present invention is to provide a pixel and a process for a lateral electric field liquid crystal display with a reduced number of photomasks. According to the present invention, a pixel and a process for a lateral electric field liquid crystal display. The pixel in the first embodiment includes a first structure on a substrate, and has a nano-scale rough surface to scatter light sources and improve contrast. A structure includes a first portion and a second portion, a second structure on the first portion to form a switching element, a liquid crystal layer on the second structure and the second portion, and a third structure on the liquid crystal layer The second part is a plurality of reflective plates having the nano-level rough surface, the third structure is an optical stack, and the liquid crystal layer may be a positive type or a negative type liquid crystal. The rough surface is formed due to the relationship between the crystal and the characteristics of the material itself. Since the first part and the second part of the reflective plate are made together, the liquid crystal display of the present invention only needs four masks, which is better than the conventional scattered liquid crystal display. The required eight or nine masks are reduced by half, which greatly reduces the cost, and because the rough surface is nano-level, the scattering effect will have a larger scattering angle and a smooth effect, that is, reflectivity. Does not change drastically with the viewing angle, but also has a good anti-glare effect (Anti-glare). In addition, since the height difference of the rough surface is smaller than the height difference of the rough surface of the current scattered inner layer reflecting plate, the change of the gap of the liquid crystal layer (1 iquidcrysta 1 ce 1 1) can be reduced, and the reflected light efficiency can be maintained at Best condition. The reflecting plate is produced by an inorganic thin film process.

200416446 五、發明說明(3) 製作,故比一般有機材料更耐高溫。 在第二及第三實施例之畫素底板中,包括一基底、一 薄膜電晶體在該基底上、多個反射板、一護層覆蓋該多個 反射板,以及一第二金屬層在該護層上,穿過該第一護層 搭接到該多個反射板的其中之一,其中,每一該反射板包 含一具有一奈米級粗链面之微散亂層,以及一反射層在該 微散亂層上,與該微散亂層的粗糙面共形而具有該粗糙 面,該反射層與薄膜電晶體之閘極係同一層金屬。該微散 亂層包括一導電層以I T0構成,以及一絕緣層在該導電層 上,由於絕緣層材料本身特性的關係因而形成該具有奈米 級之粗糙面,而該反射層係高反射率金屬構成。在第二及 第三實施例中,由於薄膜電晶體之閘極與反射板並非一同 製作,因此,須多加一道光罩。 詳細說明 圖一係本發明之橫向電場液晶顯示器畫素構造1 0 0之 一實施例,其為一穿透反射式LCD,包括一具有一奈米級 粗糙面之第一結構在基底102上,該第一結構包含第一部 分及第二部分,其中該第一部分為閘極電極1 1 0,而該第 二部分為反射板1 1 2及1 1 4,一護層1 1 6覆蓋該第一結構, 一第二結構在該閘極電極1 1 〇上方之護層1 1 6上,該第二結 構包括一汲極電極1 2 4、一源極電極1 2 6以及一由非晶石夕半 導體薄膜1 1 8所形成之通道區在汲極電極1 2 4及源極電極 1 2 6之間,該閘極電極1 1 0與第二結構形成一開關元件一薄200416446 V. Description of the invention (3) Production, so it is more resistant to high temperature than general organic materials. The pixel substrates of the second and third embodiments include a substrate, a thin film transistor on the substrate, a plurality of reflective plates, a protective layer covering the plurality of reflective plates, and a second metal layer on the substrate. The protective layer passes through the first protective layer and is connected to one of the plurality of reflective plates, wherein each of the reflective plates includes a micro scattered layer with a nano-scale coarse chain surface, and a reflective layer. The layer is on the micro-scattered layer and conforms to the rough surface of the micro-scattered layer to have the rough surface. The reflective layer is the same metal as the gate electrode of the thin film transistor. The slightly scattered layer includes a conductive layer composed of I T0 and an insulating layer on the conductive layer. Due to the characteristics of the material of the insulating layer, the rough surface with a nanometer level is formed, and the reflective layer is highly reflective. Rate metal composition. In the second and third embodiments, since the gate of the thin film transistor and the reflecting plate are not made together, an additional photomask must be added. DETAILED DESCRIPTION FIG. 1 is an embodiment of a pixel structure 100 of a lateral electric field liquid crystal display of the present invention, which is a transflective LCD including a first structure having a nanometer-level rough surface on a substrate 102. The first structure includes a first part and a second part, wherein the first part is a gate electrode 1 1 0, and the second part is a reflective plate 1 1 2 and 1 1 4; a protective layer 1 1 6 covers the first part Structure, a second structure on the protective layer 1 16 above the gate electrode 110, the second structure includes a drain electrode 1 24, a source electrode 1 26, and an amorphous stone The channel region formed by the semiconductor thin film 1 1 8 is between the drain electrode 1 2 4 and the source electrode 1 2 6. The gate electrode 1 1 0 and the second structure form a switching element and are thin.

200416446 五、發明說明(4) 膜電晶體1 2 2,且汲極電極1 2 4經由護層1 1 6上的通孔 (contact hole)120搭接至反射板114,當一電壓作用在該 薄膜電晶體時,在反射板1 1 2及1 1 4之間產生一橫向電場E 以扭轉液晶分子1 3 2,另一護層1 2 8覆蓋該第二結構,一後 端偏光膜在基底102下方,一液晶層130夾置在護層128及 一弟二結構之間’其中’該液晶層130可以是正型液晶或 負型液晶,在本實施例中,液晶層係使用負型液晶,其複 屈折射率及相位延遲的較佳實施範圍分別為〇 . 〇 5 _ 0 ·;[ 4 及5 0 - 4 1 0 n m,此外,本實施例的薄膜電晶體丨2 2係N Μ 〇 S電 晶體(η-type Metal- Oxide-Semiconductor transistor) ° 該弟二結構包括一形色滤光片1 3 8,一散射膜在彩色 渡光片1 3 8及液晶層1 3 0之間,一黑色矩陣1 3 6在彩多漬光 偏光膜142在该補你膜上方’其中黑色矩陣136並非cr金屬 材質而是由黑色樹脂(Black Resin)所構成。該閘極電極 110與反射板112及114的構造包括,—導電層1〇.4由〖το或 IZ0所構成,一絕緣層106在該導電層上由矽氮化物(SiNx) 所構成,以及一反射層108在該絕緣層上由高反射率之金 屬,例如,銘、銀及銘合金所構成,當絕緣層1〇6 導電層1〇4上時,且由於結晶及材料本身特性的關係,進 而在絕緣層1 06的表面形成奈米級的粗糙面,因此,不須 像習知技術一般多加一層樹酯層來形成粗糙面, 由 於反射板U2及U4係與問極電極11〇_同製作,故能夠以200416446 V. Description of the invention (4) The film transistor 1 2 2 and the drain electrode 1 2 4 are connected to the reflective plate 114 through the contact hole 120 on the protective layer 1 1 6. When a voltage is applied to the When a thin film transistor is formed, a lateral electric field E is generated between the reflective plates 1 12 and 1 1 4 to twist the liquid crystal molecules 1 3 2 and another protective layer 1 2 8 covers the second structure. A rear polarizing film is on the substrate. Below 102, a liquid crystal layer 130 is sandwiched between the protective layer 128 and the first and second structures, where the liquid crystal layer 130 may be a positive type liquid crystal or a negative type liquid crystal. In this embodiment, the liquid crystal layer is a negative type liquid crystal. The preferred implementation ranges of the birefringence index and phase retardation are respectively 0.05 _ 0 ·; [4 and 50-4 1 0 nm. In addition, the thin film transistor of this embodiment 丨 2 2 series N Μ 〇 S transistor (η-type Metal- Oxide-Semiconductor transistor) ° The second structure includes a shape filter 1 3 8, a scattering film between the color light filter 1 3 8 and the liquid crystal layer 1 3 0, A black matrix 1 3 6 on the multi-stained light polarizing film 142 is on top of the film, where the black matrix 136 is not a cr metal material but is made of black It is made of black resin. The structures of the gate electrode 110 and the reflective plates 112 and 114 include:-the conductive layer 10.4 is composed of το or IZ0, an insulating layer 106 is composed of silicon nitride (SiNx) on the conductive layer, and A reflective layer 108 is made of a metal with high reflectivity on the insulating layer, such as Ming, silver, and Ming alloy. When the insulating layer 106 is on the conductive layer 104, and due to the relationship between the crystal and the characteristics of the material itself Furthermore, a nano-level rough surface is formed on the surface of the insulating layer 106. Therefore, it is not necessary to add an additional resin layer to form a rough surface as in conventional techniques. Because the reflecting plates U2 and U4 are connected to the question electrode 11〇_ The same production, so you can

200416446 五、發明說明(5) 四道光罩來製程液晶顯不!§的晝素構造1 〇 〇 ’其比習知的 散亂式穿透反射式LCD之8道或9道光罩的製程少了 一半的 光罩數,故可大幅減少成本。 反射板112及114所具有之粗糙面有較小的起伏落差及 起伏週期,故在散亂效果方面,有較大的散亂角度和平緩 的效果,即反射率不隨視角做劇烈變化,也有很好的抗炫 光效果,亦可使反射光效率保持在最佳狀況,且因為可利 用無機薄膜製程,故可以比一般使用有機材料的反射式元 件更耐南溫。 圖二係圖一液晶顯示器畫素構造1 〇 〇之俯視圖,其中 該源極電極1 2 6係連接至匯流排線1 2 7。 圖三係本發明所使用之反射板的粗糙面與習知散亂式 反射板粗糙面之比較,圖三(A )係習知散亂式反射板之粗 糙面,其起伏落Η差在0.5um到1.5um之間,起伏週期L在 5 um到2 Oum之間,圖三(B)係本發明所使用之反射板的粗糙 面,其高低落差H’在5nm到50nm之間,起伏週期L’在20nm 以下,由於超微型反射板粗糙面的高低落差較小,因此, 減少液晶分子間隙的變化,進而使反射光效率保持在最佳 狀況,同時,使得散亂角度更廣更均勻。 圖四〜圖八係圖一液晶顯示器畫素構造1 〇 〇製程步驟之 俯視圖及剖面圖,首先,如圖四所示,在基底102上沈積 一層由IT0所構成之導電層104,再沈積一層由矽氮化物 (S i N X )所構成之絕緣層1 〇 6在導電層1 0 4上。在絕緣層1 0 6 形成在導電層1 0 4上時,且由於結晶及材料本身特性的關200416446 V. Description of the invention (5) Four masks to make liquid crystal display! The daytime structure 100 ′ is less than half the number of masks compared with the conventional 8- or 9-mask process of the scattered transparent reflection LCD, so the cost can be greatly reduced. The rough surfaces of the reflecting plates 112 and 114 have smaller fluctuations and fluctuation periods. Therefore, in terms of the scattering effect, there is a larger scattering angle and a gentle effect, that is, the reflectivity does not change drastically with the viewing angle. Very good anti-glare effect, can also keep the reflected light efficiency at the best condition, and because the inorganic thin film process can be used, it can be more resistant to south temperature than reflective elements using organic materials. FIG. 2 is a top view of the pixel structure 100 of the liquid crystal display 1, wherein the source electrode 1 2 6 is connected to the bus line 1 2 7. Fig. 3 is a comparison between the rough surface of the reflecting plate used in the present invention and the rough surface of the conventional scattered reflection plate, and Fig. 3 (A) shows the rough surface of the conventional scattered reflection plate, whose fluctuation difference is 0.5. Between um and 1.5um, the undulation period L is between 5 um and 2 Oum. Figure 3 (B) is the rough surface of the reflecting plate used in the present invention, and its height difference H 'is between 5nm and 50nm. L 'is below 20nm, because the difference in height between the rough surface of the ultra-micro-reflective plate is small, so the change of the gap between the liquid crystal molecules is reduced, so that the reflected light efficiency is kept at the optimal state, and the scattering angle is wider and more uniform. Figures 4 to 8 are top and cross-sectional views of the pixel structure 100 process steps of the liquid crystal display. First, as shown in Figure 4, a conductive layer 104 composed of IT0 is deposited on the substrate 102, and then a layer is deposited. An insulating layer 106 made of silicon nitride (S i NX) is on the conductive layer 104. When the insulating layer 1 0 6 is formed on the conductive layer 104, and due to the relationship between the crystal and the characteristics of the material itself,

第10頁 200416446 五、發明說明(6) 係’進而在絕緣層1 0 4的表面形成一奈米級的粗韆面,如 圖三(B)所示,接著,在絕緣層1〇4上以形成一由高反射率 之金屬,例如,鋁、銀或鋁合金等所構成之反射層丨〇 8, 反射層1 0 8與絕緣層1 0 4之粗糙面共形而具有該奈米級粗韃 面,然後,#刻反射層1 0 8、絕緣層1 〇 6以及導電層1 〇 4以 形成具有奈米級粗鏠面的電極1 1 0、1 1 2以及1 1 4。 跟著參照圖五’形成一護層1 1 6覆蓋電極1 1,〇、1 1 2以 及1 1 4,並在電極1 1 0上方形成一非晶石夕半導體薄膜1 1 8。 接著,如圖六所示,蝕刻電極1 1 4上方的護層1 1 6直到露出 電極1 1 4以形成一通孔1 20。 再來,在護層116上形成一第二金屬層,再部分钮刻 該第二金屬層以形成一薄膜電晶體1 2 2,如圖七所示,薄 膜電晶體1 2 2的閘極電極係電極1 1 0,而部分餘刻後之第二 金屬層為其沒極電極1 2 4及源極電極1 2 6,沒極電極1 2 4係 通過通孔1 2 0搭接到反射板1 1 4,而源極電極1 2 6連接到匯 流排線1 2 7。最後,再沈積一第二護層1 2 8覆蓋薄膜電晶體 122,如圖八所示。在第八圖中透光區144及由反射板112 及1 1 4所構成的反射區的面積比為1 〇 %至4 0 0 %之間。 圖九〜圖十三係另一橫向電場薄膜電晶體構造2 0 0的製 程步驟,其製程方法與上述之橫向電場薄膜電晶體構造 100的製程方法相同,其構造的差異處在於薄膜電晶體構 造200的反射板202及204係彎曲的。 圖十四係圖一畫素中底板之另一實施例,底板3 0 0包 括一基底302、一薄膜電晶體304在基底302上、一絕緣層Page 10 200416446 V. Description of the invention (6) The system further forms a nano-scale rough surface on the surface of the insulating layer 104, as shown in FIG. 3 (B), and then on the insulating layer 104 In order to form a reflective layer composed of a metal with high reflectivity, for example, aluminum, silver, or aluminum alloy, the rough surface of the reflective layer 108 and the insulating layer 104 is conformal to have the nanometer level. The rough surface is then #etched into the reflective layer 108, the insulating layer 10 and the conductive layer 104 to form electrodes 1 10, 1 12 and 1 1 4 having a nano-scale rough surface. With reference to FIG. 5 ', a protective layer 1 1 6 is formed to cover the electrodes 1 0, 1 12 and 1 1 4 and an amorphous semiconductor film 1 1 8 is formed over the electrode 1 10. Next, as shown in FIG. 6, the protective layer 1 1 6 over the electrodes 1 1 4 is etched until the electrodes 1 1 4 are exposed to form a through hole 120. Next, a second metal layer is formed on the protective layer 116, and the second metal layer is partially etched to form a thin film transistor 1 2 2. As shown in FIG. 7, the gate electrode of the thin film transistor 1 2 2 The electrode 1 1 0, and the second metal layer after the rest of the time is its electrode electrode 1 2 4 and the source electrode 1 2 6. The electrode electrode 1 2 4 is connected to the reflection plate through the through hole 1 2 0 1 1 4 and the source electrode 1 2 6 is connected to the bus line 1 2 7. Finally, a second protective layer 1 2 8 is deposited to cover the thin film transistor 122, as shown in FIG. In the eighth figure, the area ratio of the light-transmitting region 144 and the reflection region composed of the reflection plates 112 and 114 is between 10% and 400%. Figures 9 to 13 are the manufacturing steps of another transverse electric field thin film transistor structure 2000. The manufacturing method is the same as that of the transverse electric field thin film transistor structure 100 described above. The difference between the structures lies in the thin film transistor structure. The reflecting plates 202 and 204 of 200 are curved. FIG. 14 is another embodiment of the bottom plate in the pixel of FIG. 1. The bottom plate 300 includes a substrate 302, a thin film transistor 304 on the substrate 302, and an insulating layer.

第11頁 200416446 五、發明說明(7) 30 6在基底302上、反射板308及310在絕緣層306上、一護 層312覆蓋該反射板308及310、一金屬層314在護層312 上,穿過護層3 1 2搭接到反射板3 1 0,以及另一護層3 1 6覆 蓋金屬層314,其中,薄膜電晶體30 4係PMOS電晶體(p-type Metal-Oxide - Semiconductor transistor),且金屬 層3 14與薄膜電晶體3 0 4之汲極3 0 4 2。反射板3 0 8及310均包 含一由I T 0層3 1 8及絕緣層3 2 0之微散亂層,絕緣、層3 2 0具有 一奈米級粗糙面,以及一反射層3 2 2在絕緣層3 2 0上,與絕 緣層320的粗糙面共形而具有該粗糙面,反射層322與薄膜 電晶體3 0 4之閘極3 0 4 4係同一層金屬。絕緣層3 2 0除前述之 材質外,亦可由非晶矽、多晶矽構成。該微散亂層除上述 構造外亦可由一晶種層及一絕緣層經高溫燒結長晶製程。 在此實施例中,電晶體3 0 4之閘極3 0 4 4與反射板3 〇 8及3 1 0 並非一同製程,因此,比第一實施例多須一道光罩。 圖十五係圖一晝素中底板之又一實施例,底板4 Q 〇之 構造與底板300同樣包括一基底30 2、一薄膜電晶體304、 一絕緣層3 0 6、反射板3 0 8及310、一護層312、一金屬層 314,以及另一護層316,不同之處在於薄膜電晶體3〇4係 CMOS 電晶體(Complementary Metal-Oxide-Semiconductor transistor) ° 以上對於本發明之較佳實施例所作的敘述係為閣明之 目的’而無意限定本發明精確地為所揭露的形式7某於以 上的教導或從本發明的實施例學習而作修改或變化^可能 的,實施例係為解說本發明的原理以及讓熟習該項技術^Page 11 200416446 V. Description of the invention (7) 30 6 on the substrate 302, the reflective plates 308 and 310 on the insulating layer 306, a protective layer 312 covering the reflective plates 308 and 310, and a metal layer 314 on the protective layer 312 Through the protective layer 3 1 2 to the reflective plate 3 1 0, and another protective layer 3 1 6 covers the metal layer 314, wherein the thin film transistor 30 4 series PMOS transistor (p-type Metal-Oxide-Semiconductor transistor), and the drain layer 3 0 4 2 of the metal layer 3 14 and the thin film transistor 3 0 4. The reflective plates 3 0 8 and 310 each include a slightly scattered layer consisting of an IT 0 layer 3 1 8 and an insulating layer 3 2 0. The insulating and layer 3 2 0 has a nano-scale rough surface and a reflective layer 3 2 2 The insulating layer 3 2 0 is conformal to the rough surface of the insulating layer 320 and has the rough surface. The reflective layer 322 is the same metal as the gate electrode 3 0 4 4 of the thin film transistor 3 0 4. In addition to the aforementioned materials, the insulating layer 3 2 0 may be composed of amorphous silicon or polycrystalline silicon. In addition to the above structure, the micro-scattered layer can also be formed by a seed layer and an insulating layer through a high-temperature sintering process. In this embodiment, the gates 3 04 of the transistor 3 0 4 and the reflective plates 3 08 and 3 1 0 are not manufactured together. Therefore, a photomask is required more than in the first embodiment. Fig. 15 is another embodiment of the bottom plate in Fig. 1. The structure of the bottom plate 4 Q 0 is the same as that of the bottom plate 300. It includes a substrate 30 2, a thin film transistor 304, an insulating layer 3 0 6 and a reflective plate 3 0 8 And 310, a protective layer 312, a metal layer 314, and another protective layer 316, the difference is that the thin film transistor 304 series CMOS transistor (Complementary Metal-Oxide-Semiconductor transistor) ° The description of the preferred embodiment is for the sake of clarity, and it is not intended to limit the present invention to precisely the form 7 disclosed above, or to modify or change it from the teaching of the embodiment of the present invention. To explain the principles of the invention and to familiarize yourself with the technology ^

第12頁 200416446 五、發明說明(8) 以各種實施例利用本發明在實際應用上而選擇及敘述,本 發明的技術思想企圖由以下的申請專利範圍及其均等來決 定0Page 12 200416446 V. Description of the invention (8) Various embodiments are used to select and describe the present invention in practical applications. The technical idea of the present invention is intended to be determined by the following patent application scope and its equality.

第13頁 200416446 圖式簡單說明 對於熟習本技藝之人士而言,從以下所作的詳細敘述 配合伴隨的圖式,本發明將能夠更清楚地被瞭解,其上述 及其他目的及優點將會變得更明顯,其中: 圖一係本發明之橫向電場液晶顯示器畫素之一實施 例; 圖二係圖一液晶顯示器晝素構造之俯視圖; 圖三(A )係現行反射板的粗輪面; ^ 圖三(B )係本發明所使用之反射板的粗糙面; 圖四〜圖八係圖一之橫向電場薄膜電晶體構造的的製 程步驟; 圖九〜圖十三係另一橫向電場薄膜電晶體構造的的製 程步驟。 圖十四係圖一畫素中底板之另一實施例;以及 圖十五係圖一晝素中底板之又一實施例。 圖式標號說明 100 畫素構造 101 偏光膜 102 基底 104 導電層 1 0 6 絕緣層 108 反射層 110 問極電極 1 1 2 反射板Page 16 200416446 Schematic description For those skilled in the art, from the following detailed description and accompanying drawings, the present invention will be more clearly understood, its above and other objectives and advantages will become It is more obvious, in which: FIG. 1 is an embodiment of the horizontal electric field liquid crystal display pixel of the present invention; FIG. 2 is a top view of the daylight structure of the liquid crystal display; FIG. 3 (A) is a rough wheel surface of the current reflecting plate; ^ Fig. 3 (B) is a rough surface of a reflective plate used in the present invention; Fig. 4 ~ Fig. 8 are the process steps of the transverse electric field thin film transistor structure of Fig. 1; Fig. 9 ~ Fig. 13 are another transverse electric field film transistor Process steps for crystal structure. FIG. 14 is another embodiment of a base plate in a pixel of FIG. 1; and FIG. 15 is another embodiment of a base plate in a pixel of FIG. Description of the reference numerals 100 pixel structure 101 Polarizing film 102 Base 104 Conductive layer 1 0 6 Insulating layer 108 Reflective layer 110 Question electrode 1 1 2 Reflective plate

第14頁Page 14

V 200416446V 200416446

第15頁 圖式簡單說明 114 反 射 板 116 護 層 118 非 晶 矽 半 導 體 薄 膜 120 通 孔 122 薄 膜 電 晶 體 124 薄 膜 電 晶 體 的 汲 極電極 126 薄 膜 電 晶 體 的 源 極電極 127 匯 流排線 128 護 層 130 液 晶 層 132 液 晶 分 子 134 散 射 膜 136 黑 色矩陣 138 彩 色 濾 光 片 140 補 償 膜 142 偏 光 膜 144 透 光 區 200 薄 膜 電 晶體構造 202 彎 曲 反 射 板 204 彎 曲 反 射 板 300 畫 素 的 底 板 302 基底 304 薄 膜 電 晶 體 3 0 42 薄 膜 電 晶體3 0 4之 >及極 200416446 圖式簡單說明 3 0 4 4 薄膜電晶體3 0 4之閘極 3 0 6 絕緣層 3 0 8 反射板 310 反射板 312 護層 314 金屬層 316 護層 318 ITO 層 3 2 0 絕緣層 3 2 2 反射層 4 0 0 畫素的底板 4 0 2 薄膜電晶體Brief description of drawings on page 15 114 Reflective plate 116 Protective layer 118 Amorphous silicon semiconductor film 120 Through hole 122 Thin film transistor 124 Drain electrode of thin film transistor 126 Source electrode of thin film transistor 127 Bus line 128 Protective layer 130 Liquid crystal layer 132 Liquid crystal molecules 134 Scattering film 136 Black matrix 138 Color filter 140 Compensation film 142 Polarizing film 144 Light transmission area 200 Thin film transistor structure 202 Bending reflection plate 204 Bending reflection plate 300 Pixel base plate 302 Substrate 304 Thin film transistor 3 0 42 Thin film transistor 3 0 4 > and 200416446 Brief description of the diagram 3 0 4 4 Thin film transistor 3 0 4 Gate 3 0 6 Insulating layer 3 0 8 Reflective plate 310 Reflective plate 312 Protective layer 314 Metal Layer 316 Protective layer 318 ITO layer 3 2 0 Insulating layer 3 2 2 Reflective layer 4 0 0 Pixel base plate 4 0 2 Thin film transistor

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Claims (1)

200416446 六、申請專利範圍 1. 一種橫向電場液晶顯不Is畫素1包括· 一第一結構,在一基底上,具有一奈米級粗鏠面以散 射光源及提高對比度,該第一結構包含一第一部 分及第二部分; 一第二結構,在該第一部分上形成一開關元件; 一液晶層,在該第二結構及第二部分上;以及 一第三結構,在該液晶層上。 2. 如申請專利範圍第1項之畫素,其中該液晶層係正 型液晶,具有複屈折射率,該折射率的最佳範圍為0 . 0 5 -0.12° 3 ·如申請專利範圍第1項之畫素,其中該液晶層係負 型液晶,具有複屈折射率及相位延遲,該折射率的最佳 輯圍為0 · 0 5 - 0 · 1 4,而該相位延遲的最佳範圍為1 5 0 -4 1 0nm 〇 4.如申請專利範圍第1項之畫素,其中該粗糙面具有 一起伏落差的範圍在5nm到50nm之間。 5 .如申請專利範圍第1項之畫素,其中該粗糙面具有 一起伏週期的範圍在10nm到500nm。 6 ·如申請專利範圍第1項之畫素,其中該第一結構之 構造包括: 一微散亂層,在該基底上,具有該奈米級粗縫面; 一反射層,在該微散亂層上,與該微散亂層之粗糙面 共形而具有該粗糙面,且由高反射率金屬構成。 7.如申請專利範圍第6項之畫素,其中該微散亂層包200416446 6. Scope of patent application 1. A transverse electric field liquid crystal display Is pixel 1 includes a first structure on a substrate with a nano-scale rough surface to scatter light sources and improve contrast. The first structure includes A first part and a second part; a second structure on which a switching element is formed; a liquid crystal layer on the second structure and the second part; and a third structure on the liquid crystal layer. 2. For example, the pixel in the first patent application range, wherein the liquid crystal layer is a positive type liquid crystal and has a complex refractive index, and the optimal range of the refractive index is 0.05 to 0.12 ° 3. The pixel of item 1, wherein the liquid crystal layer is a negative type liquid crystal and has a complex refractive index and a phase retardation. The optimal range of the refractive index is 0 · 0 5-0 · 1 4 and the optimal phase retardation is. The range is 1 50-4 10 nm. 4. The pixel of the first item of the patent application range, wherein the rough surface has a range of 5 to 50 nm. 5. The pixel according to item 1 of the patent application range, wherein the rough surface has a volt period ranging from 10 nm to 500 nm. 6. The pixel according to item 1 of the scope of the patent application, wherein the structure of the first structure includes: a slightly scattered layer having the nano-scale rough seam surface on the substrate; a reflective layer on the slightly scattered The chaotic layer is conformal to the rough surface of the slightly scattered chaotic layer and has the rough surface, and is composed of a high-reflectivity metal. 7. The pixel according to item 6 of the patent application scope, wherein the slightly scattered layer package 第17頁 200416446 六、申請專利範圍 括: 一導電層,在該基底上;以及 一絕緣層,在該導電層上,具有該奈米級粗糙面。 8 .如申請專利範圍第7項之晝素,其中該導電層係由 I T 0或I Z 0構成。 9.如申請專利範圍第7項之畫素,其中該絕緣層係由 氮化矽、氧化矽或氮氧化矽構成。 1 0 .如申請專利範圍第6項之畫素,其中該微散亂層至 少包括一具有該奈米級粗糙面之絕緣層。Page 17 200416446 6. The scope of patent application includes: a conductive layer on the substrate; and an insulating layer on the conductive layer with the nano-level rough surface. 8. The day element of claim 7 in the scope of the patent application, wherein the conductive layer is composed of I T 0 or I Z 0. 9. The pixel according to item 7 of the application, wherein the insulating layer is composed of silicon nitride, silicon oxide, or silicon oxynitride. 10. The pixel according to item 6 of the scope of the patent application, wherein the slightly scattered layer includes at least an insulating layer having the nano-level rough surface. 1 1 .如申請專利範圍第1 0項之畫素,其中該絕緣層係 由非晶矽、多晶矽、氮化矽、氧化矽或氮氧化矽構成。 1 2 .如申請專利範圍第6項之畫素,其中該微散亂層至 少包括一晶種層及一具有該奈米級粗糙面之絕緣層。 1 3 .如申請專利範圍第1 2項之畫素,其中該絕緣層係 經高溫燒結長晶製程。 1 4.如申請專利範圍第6項之晝素,其中該高反射率金 屬係銘、銀或紹合金。 1 5 .如申請專利範圍第1項之畫素,其中該第二部分係 多個具有該奈米級粗鏠面之反射板。11. The pixel according to item 10 of the patent application scope, wherein the insulating layer is composed of amorphous silicon, polycrystalline silicon, silicon nitride, silicon oxide, or silicon oxynitride. 12. The pixel according to item 6 of the patent application scope, wherein the micro-scattered layer includes at least a seed layer and an insulating layer having the nano-level rough surface. 13. The pixel according to item 12 of the scope of patent application, wherein the insulating layer is subjected to a high-temperature sintering growth process. 1 4. The daily element of item 6 of the scope of application for a patent, wherein the high reflectivity metal is a motto, silver or a Shao alloy. 15. The pixel according to item 1 of the scope of patent application, wherein the second part is a plurality of reflecting plates having the nano-scale rough surface. 1 6 .如申請專利範圍第1 5項之畫素,其中該多個反射 板係彎曲的構造。 1 7.如申請專利範圍第1項之畫素,其中該第一部分係 閘極電極。 1 8.如申請專利範圍第1項之畫素,其中該開關元件係16. The pixel according to item 15 of the scope of patent application, wherein the plurality of reflecting plates are curved structures. 1 7. The pixel according to item 1 of the patent application scope, wherein the first part is a gate electrode. 1 8. The pixel according to item 1 of the patent application scope, wherein the switching element is 第18頁 200416446 六、申請專利範圍 一薄膜電晶體。 1 9.如申請專利範圍第1項之畫素,其中該第三結構包 括: 一彩色濾光片; 一散射膜,夾置在該彩色濾光片及液晶層之間;以及 一偏光膜,在該彩色濾光片上。 2 0 .如申請專利範圍第1項之畫素,其中該第一結構係 由無機薄膜製程形成。 2 1 .如申請專利範圍第1項之晝素,其中該第一結構更 包括一透光區,該透光區具有一第一面積,該第二部分具 有一第二面積,該第一面積對該第二面積比為10 %至 4 0 0% ° 2 2 . —種橫向電場薄膜電晶體液晶顯示器畫素的製 程,包括下列步驟: 在一基底上形成一具有一奈米級粗縫面之第一結構; 部分蝕刻該第一結構以形成一第一部分及第二部分; 在該第一部分上形成一第二結構,以當作一開關元 件; 在該第二結構及第二部分上形成一液晶層;以及 在該液晶層上形成一第三結構。 2 3.如申請專利範圍第2 2項之製程,其中形成該第一 結構的步驟包括: 在該基底上形成一微散亂層;以及 在該絕緣層上形成一層具有高反射率之反射層。Page 18 200416446 6. Scope of patent application A thin film transistor. 19. The pixel according to item 1 of the patent application scope, wherein the third structure includes: a color filter; a scattering film sandwiched between the color filter and the liquid crystal layer; and a polarizing film, On this color filter. 20. The pixel according to item 1 of the patent application scope, wherein the first structure is formed by an inorganic thin film process. 2 1. The daylight element as described in the first item of the patent application scope, wherein the first structure further includes a light-transmitting area, the light-transmitting area has a first area, the second part has a second area, and the first area The second area ratio is from 10% to 400% ° 2 2. — A process for manufacturing a horizontal electric field thin film transistor liquid crystal display pixel, including the following steps: forming a nano-scale rough surface on a substrate A first structure; partially etching the first structure to form a first portion and a second portion; forming a second structure on the first portion to be used as a switching element; forming on the second structure and the second portion A liquid crystal layer; and forming a third structure on the liquid crystal layer. 2 3. The process of claim 22 in the scope of patent application, wherein the step of forming the first structure includes: forming a slightly scattered layer on the substrate; and forming a reflective layer with a high reflectance on the insulating layer . 第19頁 200416446 六、申請專利範圍 2 4.如申請專利範圍第2 3項之製程,其中形成該微散 亂層之步驟包括: 在該基底上形成一導電層;以及 在該導電層上沈積一絕緣層以形成該奈米級粗糙面。 2 5 .如申請專利範圍第2 4項之製程,其中形成該導電 層的步驟包括由ΙΤ0或ΙΖ0形成。 2 6 .如申請專利範圍第2 4項之製程,其中形成該絕緣 層的步驟包括由氮化碎、氧化石夕或氮氧化碎形成。 2 7.如申請專利範圍第2 3項之製程,其中形成該微散 亂層的步驟至少包括形成一具有該奈米級粗糙面之絕緣 層。 2 8 .如申請專利範圍第2 7項之製程,其中形成該絕緣 層的步驟包括由非晶矽、多晶矽、氮化矽、氧化矽或氮氧 化石夕形成。 2 9 .如申請專利範圍第2 3項之製程,其中形成該微散 脔L層的步驟至少包括形成一晶種層及一具有該奈米級粗糙 面之絕緣層。 3 0 .如申請專利範圍第2 9項之製程,其中形成該絕緣 層的步驟包括高溫燒結長晶製程。 3 1 .如申請專利範圍第2 3項之製程,其中形成該反射 層的步驟包括使用鋁、銀或鋁合金來形成。 3 2 .如申請專利範圍第2 2項之製程,其中形成該第一 部分的步驟包括形成一閘極電極。 3 3 .如申請專利範圍第2 2項之製程,其中形成該第二Page 19, 200416446 VI. Application for patent scope 2 4. The process of applying for patent scope No. 23, wherein the step of forming the slightly scattered layer includes: forming a conductive layer on the substrate; and depositing on the conductive layer An insulating layer is formed to form the nano-scale rough surface. 25. The process of claim 24, wherein the step of forming the conductive layer includes forming ITO or IZ0. 26. The process according to item 24 of the scope of patent application, wherein the step of forming the insulating layer includes forming by nitriding, oxidizing stone or oxynitriding. 2 7. The process according to item 23 of the scope of patent application, wherein the step of forming the slightly scattered layer includes at least forming an insulating layer having the nano-level rough surface. 28. The process according to item 27 of the scope of patent application, wherein the step of forming the insulating layer includes forming from amorphous silicon, polycrystalline silicon, silicon nitride, silicon oxide, or oxynitride. 29. The process according to item 23 of the scope of patent application, wherein the step of forming the finely divided 脔 L layer includes at least forming a seed layer and an insulating layer having the nano-level rough surface. 30. The process of claim 29, wherein the step of forming the insulating layer includes a high-temperature sintering process. 31. The process of claim 23, wherein the step of forming the reflective layer includes using aluminum, silver, or an aluminum alloy. 32. The process of claim 22, wherein the step of forming the first part includes forming a gate electrode. 3 3. If the process of item 22 of the scope of patent application, which forms the second 第20頁 200416446 六、申請專利範圍 部分的步驟包括形成多個具有該奈米級粗糙面之反射板。 3 4.如申請專利範圍第2 2項之製程,其中形成該第二 部分的步驟包括形成多個具有該奈米級粗糙面之彎曲反射 板。 3 5 .如申請專利範圍第2 2項之製程,其中形成該第一 結構的步驟包括使用無機薄膜製程來形成。 3 6 .如申請專利範圍第2 2項之製程,其中形、成該開關 元件之步驟包括形成一薄膜電晶體。Page 20 200416446 6. The scope of the patent application part of the steps includes forming a plurality of reflective plates with the nano-scale rough surface. 3 4. The process according to item 22 of the scope of patent application, wherein the step of forming the second part includes forming a plurality of curved reflective plates having the nano-level rough surface. 35. The process of claim 22 in the scope of patent application, wherein the step of forming the first structure includes forming using an inorganic thin film process. 36. The process of claim 22 in the scope of patent application, wherein the step of forming and forming the switching element includes forming a thin film transistor. 3 7.如申請專利範圍第2 2項之製程,其中形成該第三 結構的步驟至少包括: 形成一散射膜; 在該散射膜上形成一彩色濾光片;以及 在彩色濾光片上形成一偏光膜。 38. —種橫向電場液晶顯不|§晝素的底板5包括· 一基底; 一薄膜電晶體,在該基底上; 多個反射板,每一該反射板包含: 一微散亂層,具有一奈米級粗糙面;37. The process according to item 22 of the scope of patent application, wherein the step of forming the third structure includes at least: forming a scattering film; forming a color filter on the scattering film; and forming on the color filter. A polarizing film. 38. A transverse electric field liquid crystal display | § The base plate 5 of the day element includes a substrate; a thin film transistor on the substrate; a plurality of reflective plates, each of which includes: a slightly scattered layer having One nanometer rough surface; 一反射層,在該微散亂層上,與該微散亂層的粗糙面 共形而具有該粗糙面,該反射層與薄膜電晶體之 閘極係同一層金屬; 一護層,覆蓋該多個反射板;以及 一金屬層,在該護層上,穿過該護層搭接到該多個反 射板的其中之一。A reflective layer on the micro-scattered layer conforming to the rough surface of the micro-scattered layer to have the rough surface, the reflective layer and the gate of the thin film transistor are the same metal; a protective layer covering the A plurality of reflective plates; and a metal layer on the protective layer, and passing through the protective layer to overlap one of the plurality of reflective plates. 第21頁 200416446 六、申請專利範圍 3 9 .如申請專利範圍第3 8項之底板,其中該粗糙面具 有一起伏落差的範圍在5nm到50nm之間。 4 0 .如申請專利範圍第3 8項之底板,其中該粗糙面具 有一起伏週期的範圍在10nm到500nm。 4 1 .如申請專利範圍第3 8項之底板,其中該微散亂 層,包括: 一導電層; , 一絕緣層,在該導電層上,具有該奈米級粗糙面。 4 2 .如申請專利範圍第4 1項之底板,其中該導電層係 由IT0或IZ0構成。 4 3 .如申請專利範圍第4 1項之底板,其中該絕緣層係 由氮化矽、氧化矽或氮氧化矽構成。 4 4.如申請專利範圍第3 8項之底板,其中該微散亂層 至少包括一具有該奈米級粗缝面之絕緣層。 4 5 .如申請專利範圍第4 4項之底板,其中該絕緣層係 由非晶矽、多晶矽、氮化矽、氧化矽或氮氧化矽構成。 4 6 .如申請專利範圍第3 8項之底板,其中該微散亂層 至少包括一晶種層及一具有該奈米級粗糙面之絕緣層。 4 7.如申請專利範圍第4 6項之底板,其中該絕緣層係 經高溫燒結長晶製程。 4 8 .如申請專利範圍第3 8項之底板,其中該微散亂層 係由無機薄膜製程形成。 4 9 .如申請專利範圍第3 8項之底板,其中該反射層係 高反射率金屬構成。Page 21 200416446 6. Application for patent scope 39. For example, the bottom plate for scope 38 of the patent application scope, wherein the rough mask has a voltage drop range between 5nm and 50nm. 40. The base plate according to item 38 of the scope of the patent application, wherein the rough mask has a volt period ranging from 10 nm to 500 nm. 41. The bottom plate according to item 38 of the scope of patent application, wherein the slightly scattered layer includes: a conductive layer; and an insulating layer having the nano-level rough surface on the conductive layer. 4 2. The base plate according to item 41 of the patent application scope, wherein the conductive layer is composed of IT0 or IZ0. 43. The baseplate according to item 41 of the scope of patent application, wherein the insulating layer is composed of silicon nitride, silicon oxide, or silicon oxynitride. 4 4. The bottom plate according to item 38 of the scope of patent application, wherein the slightly scattered layer includes at least an insulating layer having the nano-scale rough seam surface. 4 5. The base plate according to item 44 of the patent application scope, wherein the insulating layer is composed of amorphous silicon, polycrystalline silicon, silicon nitride, silicon oxide, or silicon oxynitride. 46. The bottom plate according to item 38 of the scope of patent application, wherein the slightly scattered layer includes at least a seed layer and an insulating layer having the nano-level rough surface. 47. The base plate according to item 46 of the patent application scope, wherein the insulating layer is subjected to a high-temperature sintering growth process. 48. The bottom plate according to item 38 of the scope of patent application, wherein the slightly scattered layer is formed by an inorganic thin film process. 49. The base plate according to item 38 of the scope of patent application, wherein the reflective layer is made of a high reflectivity metal. 第22頁 200416446 六、申請專利範圍 5 0 .如申請專利範圍第3 8項之底板,其中該薄膜電晶 體包含NM0S電晶體。 5 1 .如申請專利範圍第3 8項之底板,其中該薄膜電晶 體包含PM0S電晶體。 5 2 .如申請專利範圍第3 8項之底板,其中該薄膜電晶 體包含CMOS電晶體。 5 3 .如申請專利範圍第3 8項之底板,更包括一透光區 具有一第一面積,而該多個反射板具有一第二面積,該第 一面積對該第二面積比為1 0 %至4 0 0 %。Page 22 200416446 VI. Application scope of patent 50. For the base plate of item 38 of the scope of patent application, wherein the thin film transistor includes NMOS transistor. 51. The substrate according to item 38 of the scope of patent application, wherein the thin film transistor comprises a PMOS transistor. 52. The substrate according to item 38 of the scope of patent application, wherein the thin film transistor includes a CMOS transistor. 53. As for the bottom plate of the 38th patent application scope, it further includes a light-transmitting area having a first area, and the plurality of reflective plates having a second area, and the ratio of the first area to the second area is 1 0% to 4 0%. 第23頁Page 23
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