TW200415778A - Layout structure of standard cell - Google Patents
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200415778200415778
發明所屬之技術領域: 本發明係有關於一種標準元件(standard Cell)之佈局姓 構,特別:系有關於積體電路佈局時所應用的標準元件: 局結構。猎著縮減標準元件内電晶體與操作電源 之間的距離,以增加電晶體的尺寸,…不改變標準連接 件之南度和面積下提升標準元件的工作效率。 先前技術: 隨者半導體技術的進步,半導體元件的尺寸愈來愈小Technical field to which the invention belongs: The present invention relates to a layout name structure of a standard cell, and in particular: it relates to a standard component used in integrated circuit layout: a local structure. Hunting to reduce the distance between the transistor and the operating power in the standard component to increase the size of the transistor,… to improve the efficiency of the standard component without changing the south and area of the standard connector. Previous technology: With the advancement of semiconductor technology, the size of semiconductor components is getting smaller and smaller
體電路愈來愈精密’"體元件在有限的空間内不斷堆J 的結果,造成半導體元件進入次微米(Sub_Micr〇)甚至深次 微米(Deep Sub-Micro)的領域時,為了使積體電路的運作 效率提高和元件佔面積的考量,半導體元件的尺寸需大 幅縮小,而精確的積體電路佈局,便是先進的製程控制中 一項主要的任務。 f體電路的佈局在晶片設計的過程中是非常重要的步驟, 佈局的好壞直接影響到面積、可繞性與晶片效能。其中, 標準元件佈局設計方法(Standard CeU Uy〇ut ““卯The body circuit is getting more and more precise 'As a result of the continuous stacking of J in the limited space of the body element, when the semiconductor element enters the sub-micron (Sub_Micr0) or even the deep sub-micron (Deep Sub-Micro) field, in order to make the integrated circuit Considering the improvement of circuit operating efficiency and the area occupied by components, the size of semiconductor components needs to be greatly reduced, and accurate integrated circuit layout is a major task in advanced process control. The layout of the f-body circuit is a very important step in the process of chip design. The quality of the layout directly affects the area, windability and chip performance. Among them, the standard component layout design method (Standard CeU Uy〇ut "" 卯
Methodology)是目前最常應用的積體電路設計方法,因為 標準元件佈局設計方法主要係自標準元件庫(standard =U Library)中選取各種不同的標準元件(如標準⑶⑽元 :)來進行設計,所以佈局處理(Lay〇ut Pr〇cess)可以全部 動化’ & S十製造時間非常短’同時具有高生產信賴度。 例如,請參考第1圖和第2圖,第丨圖所繪示為包含有p型電 晶體和N型電晶體的標準元件之佈局上視圖,第2圖所繪示Methodology) is currently the most commonly used integrated circuit design method, because the standard component layout design method is mainly selected from the standard component library (standard = U Library) to select a variety of different standard components (such as the standard CD element :) for design, Therefore, the layout processing (Lay〇ut Pr〇cess) can be fully automated '& S ten manufacturing time is very short' while having high production reliability. For example, please refer to Figure 1 and Figure 2. Figure 丨 shows the top view of the layout of standard components including p-type transistors and N-type transistors, and Figure 2 shows
200415778 五、發明說明(2) 為沿著第1圖中AA,截面線所得之結構示意圖。如第j圖和第 2圖所示,標準元件1〇的佈局中包括有p型電晶體和n型電晶 體的佈局,由P型井80和N型井70,以及p型井8〇中的p+摻雜 區82與N+摻雜區84和N型井70中的P+摻雜區74與“摻雜區72 構成,半導體材料層6 0作為閘極。其中,標準元件丨〇具有 尺寸44,插塞32係用以電性連接p型操作層12&p型操j乍層 12上方的金屬層20,插塞36係用以電性連接]^型操作層以曰及 N型操作層22上方的金屬層3〇。 P型電晶體的p型操作層12中至少包括有主操作區14和延伸 =乍區16 ’主操作區14具有尺寸46,而延伸操作區16透過 接觸插塞18與上方的金屬層2〇作電性連接 型操作層22中至少包括有主操作區24和延伸操作區26體的主 區24具有尺寸48 ’而延伸操作區26透過接觸插塞28與 上方的金屬層30作電性連接。金屬層2〇和金屬層㈣二者之 一可電性連接至操作電壓(未繪示),另一者則可接地(未繪 =。同時,介電層90位於金屬層2〇和p型操作層12之間, =屬,30和N型操作層22之間’以及金屬線42與基材心之 操作Lf。8則帛以電性連接金屬線42和?型操作層12與\型 :T作圖區比準:件1 〇之佈局中,可發現延伸操作區1 6和延 漳=时26白而要透過接觸插塞才能與上方的金屬層作電 二由於接觸插塞會在佈局電路圖中佔有一定的空 ^使,主操作區14和主操作區24的面積被限制在一定範 ,例如經由量測後,可得知第1圖中主操作區14的尺寸200415778 V. Description of the invention (2) Schematic diagram of the structure obtained along the line AA and section in Figure 1. As shown in Fig. J and Fig. 2, the layout of the standard element 10 includes a layout of p-type transistors and n-type transistors. The P-type well 80 and the N-type well 70, and the p-type well 80 The p + doped region 82 and the N + doped region 84 and the P + doped region 74 and the "doped region 72" in the N-type well 70 are formed, and the semiconductor material layer 60 is used as a gate. Among them, the standard element has a size 44 The plug 32 is used to electrically connect the p-type operation layer 12 & p-type operation layer 12 above the metal layer 20, and the plug 36 is used to electrically connect the ^ -type operation layer to the N-type operation layer The metal layer 30 above 22. The p-type operation layer 12 of the P-type transistor includes at least a main operation area 14 and an extension = 16. The main operation area 14 has a size of 46, and the extended operation area 16 passes through the contact plug. 18 and the upper metal layer 20. Electrically-connected operation layer 22 includes at least a main operation area 24 and an extended operation area 26. The main area 24 has a size of 48 ', and the extended operation area 26 is connected to the top through the contact plug 28. The metal layer 30 is electrically connected. One of the metal layer 20 and the metal layer 可 can be electrically connected to an operating voltage (not shown), and the other can be connected. (Not shown). Meanwhile, the dielectric layer 90 is located between the metal layer 20 and the p-type operation layer 12, and the metal layer 42 is between the 30 and the N-type operation layer 22 ′ and the operation Lf of the metal wire 42 and the substrate core. In 8 layouts, electrically connecting the metal wire 42 and the? -Type operation layer 12 to the \ type: T drawing area alignment: the layout of the piece 10, it can be found that the extended operation area 16 and Yanzhang = time 26 The contact plug can be used to make electricity with the upper metal layer. Because the contact plug occupies a certain space in the layout circuit diagram, the areas of the main operating area 14 and the main operating area 24 are limited to a certain range, for example, through measurement Later, we can know the size of the main operating area 14 in the first figure
第6頁 200415778 、發明說明(3) 约為0.56 主操作區24的尺寸則約為〇·36 請參考第3圖和第4圖,第3圖所緣示為包含有p 型電晶體的標準元件之佈局上視圖,第4圖所繪示為沿著第 3一圖中BB’截面線所得之結構示意圖。如第3圖和第4圖所 不’標準元件50的佈局中同樣包括有p型電晶體和n型電晶 ^佈局。其中’標準元件5〇具有尺寸92,插塞32係用以 ,性連接P型操作層12W型操作層12上方的金屬層2〇,插 Γ層^用以電性連接N型操作層22 ^型操作層22上方的金 操作層12中至少包括有主操作,和L形延 口 刼作區14具有尺寸86,而1形延伸操作區94 n ^ Α 2 Λ ^ ^2 ° ^ ^ ^ ,, t a, ^ ^ θ / ι括有主操作區24和L形延伸操作區 插塞= 電延伸操作區96亦係透過 =(未\^電性連接至操作㈣(切心另-者則可 ΐ:1 圖圖中和佔第有2圖於接觸插塞18和接觸插塞28在佈局 的面積内使Γ操作區14和主操作區24 高产和面接在 乾圍内,為了在不改變標準元件10之 22:主操力的?籍操作層12之主操作區14和 率,傳统的積’從而提升標準元件10的工作效 塞28,從而糸去除第1 ®令之接觸插塞18和接觸插 又付第3圖和第4圖所示之標準元件5 〇。同時, 第7頁 200415778 五、發明說明(4) ------ 基:製程設備的製程條件下’將第i圖中之延伸操作區 =申操作區26改變為如第3圖所*之[形,讓L形延伸操作區 94和L形延伸操作區96分別透過插塞32和插塞36直接分別盥 上方的金屬層20和金屬層30作電性連接。於是p型操作層& 之主操作區1 4和N型操作層22之主操作區24的面積得以& 大,例如經由量測後,可得知第3圖中主操作區14的尺寸86 約為0.66 ,與第i圖中主操作區14的尺寸46相比增加了 0.1私Π1。主操作區24的尺寸88則約為〇.46 #m,與第1圖 中主操作區24的尺寸48相比增加了oj ,而且,第3圖 中標準元件50的尺寸92與第1圖中標準元件1〇的尺寸44相 同。 然而,當半導體製程發展至奈米等級時,標準元件的尺寸 大幅縮小,使得標準元件的驅動能力減弱,如何提升標準 元件的驅動能力便成為製程提升的關鍵。 發明内容: 雲於上述之發明背景中,隨著半導體技術的進步,半導體 元件的尺寸愈來愈小,積體電路愈來愈精密,使得精確的 積體電路佈局在先進製程控制佔有非常重要的地位,而標Page 6 200415778, description of the invention (3) is about 0.56. The size of the main operating area 24 is about 0.36. Please refer to Figures 3 and 4, which are shown in Figure 3 as a standard that includes p-type transistors. The top view of the layout of the components, shown in Figure 4 is a schematic diagram of the structure obtained along the BB 'section line in Figure 3.1. As shown in Figs. 3 and 4, the layout of the standard element 50 also includes a p-type transistor and an n-type transistor. Among them, the “standard component 50” has a size of 92, and the plug 32 is used to sexually connect the metal layer 20 above the P-type operation layer 12 and the W-type operation layer 12 and the Γ layer is used to electrically connect the N-type operation layer 22 ^ The gold operation layer 12 above the type operation layer 22 includes at least a main operation, and the L-shaped extended mouth operation area 14 has a size of 86, and the 1-shaped extension operation area 94 n ^ Α 2 Λ ^ ^ 2 ° ^ ^ ^, , ta, ^ ^ θ / ι includes the main operating area 24 and the L-shaped extended operating area plug = the electrically extended operating area 96 is also connected to the operating through = (not \ ^ electrically connected to the other-you can ΐ: 1 and 2 in the figure, the contact plug 18 and contact plug 28 make the Γ operation area 14 and the main operation area 24 high-yield and face within the dry area within the layout area, in order not to change the standard Element 10-22: the main operating force? Based on the main operating area 14 and the rate of the operating layer 12, the traditional product is used to improve the work efficiency plug 28 of the standard component 10, thereby removing the first plug of the contact plug 18 and The contact plug also pays the standard component 5 shown in Figures 3 and 4. At the same time, page 7 200415778 V. Description of the invention (4) ------ Basic: Process conditions of the process equipment 'Change the extended operation area in the i-th figure to the Shen operation area 26 to the [shape as shown in Figure 3, and let the L-shaped extended operation area 94 and the L-shaped extended operation area 96 pass through the plug 32 and the plug 36, respectively. The metal layer 20 and the metal layer 30 directly above are respectively electrically connected. Therefore, the areas of the main operation area 14 of the p-type operation layer & 14 and the main operation area 24 of the N-type operation layer 22 are & large, for example, via After the measurement, it can be seen that the size 86 of the main operation area 14 in FIG. 3 is about 0.66, which is 0.1% larger than the size 46 of the main operation area 14 in FIG. I. The size of the main operation area 24 is 88 Approximately 0.46 #m, which is oj larger than the size 48 of the main operating area 24 in FIG. 1, and the size 92 of the standard component 50 in FIG. 3 and the size 44 of the standard component 10 in FIG. 1 The same. However, when the semiconductor process is developed to the nanometer level, the size of the standard component is greatly reduced, which weakens the driving capability of the standard component. How to improve the driving capability of the standard component becomes the key to the process improvement. Summary of the Invention: Clouds above the above BACKGROUND OF THE INVENTION With the advancement of semiconductor technology, the scale of semiconductor elements Smaller and smaller, more and more sophisticated integrated circuits, making precise integrated circuit layout occupies a very important position in advanced process control, while the S &
準元件佈局設計方法是目前最常應用的積體電路設計方 法。然而,由於標準元件的尺寸愈來愈小,使得標準元件 的工作效率及驅動能力等大為下降,故此為了在不改變標 準元件之高度和面積下提升標準元件的工作效率,本發明 提供了 一種標準元件之佈局結構。 本發明的主要目的為提供了一種標準元件之佈局結構,係The quasi-component layout design method is the most commonly used integrated circuit design method. However, since the size of the standard component is getting smaller and smaller, the working efficiency and driving ability of the standard component are greatly reduced. Therefore, in order to improve the working efficiency of the standard component without changing the height and area of the standard component, the present invention provides a Layout structure of standard components. The main purpose of the present invention is to provide a layout structure of standard components.
第8頁 200415778 五、發明說明(5) 在不改變標準元件 應用在積體電路佈局的半導體製程上,在不改變標準元件 的高度及尺寸下’讓標準元件内的P型電晶體和N型電晶體 之操作層直接透過接觸插塞,如N型井接觸插塞(n — —Page 8 200415778 V. Description of the invention (5) In the semiconductor process applied to the integrated circuit layout without changing the standard component, the P-type transistor and the N-type in the standard component are not changed without changing the height and size of the standard component The operating layer of the transistor passes directly through the contact plug, such as an N-type contact plug (n — —
Contact Plug)或基材接觸插塞(P — Sub c〇ntact piug)等, 與連接操作電源或連接接地的金屬層作電性連接, 電晶體和N型電晶體的尺寸獲得擴大,p型電晶體和n ,的工作效率便得以提升,從*提高標準元件的工作效 根據以上所述之目的,本發明提供了一種標準元 =構▲係應用在積體電路佈局的半導體製程上 :Contact Plug) or substrate contact plug (P — Subcontact piug), etc., are electrically connected to the metal layer connected to the operating power supply or to the ground. The sizes of transistors and N-type transistors are enlarged, and p-type transistors The working efficiency of the crystal and n is improved, and the working efficiency of the standard component is improved from * According to the above-mentioned purpose, the present invention provides a standard element = structure ▲ which is applied to the semiconductor process of integrated circuit layout:
件之佈局結構至少包括··基材· 此準7G 和第二導電型電晶體操 別:::電工曰體操作層 電型電晶體操作層為M位^基^上’其中第一導 二者中之-者,第二導雷二體曰刼作層㈣型電晶體操作層 作層和N型電晶體操作層二者中0曰體刼作層則為P型電晶體操 電晶體操作層至少包括拓 之另者’而且第一導電型 副操作區域,第二導電^延伸操作區域、主操作區域和 操作區域、主操作層至少包括矩形延伸 型電晶體操作層的副操作1=立於基材上’其中第一導電 第-金屬層下,第一導電型電曰口^延伸操作區域皆位於 透過第一接觸插塞與第— 曰曰呆作層的副操作區域更 晶體操作層的副操作區 f層電性連接,第二導電型電 金屬層下,第二導電型電::形延伸操作區域皆位於第二 電曰曰體操作層的副操作區域更透過 第9頁 200415778 五、發明說明(6) 第二接觸插塞與第二金屬層電性連接 實施方式: 在傳統標準元件的佈局中,P型操作層和N型操作層的延 操作區皆需透過接觸插塞與上方的金屬層作電性連接,又 或是改用L形延伸操作區與上方的金屬層直接電性連接,藉 以增加P型電晶體和N型電晶體的尺寸來提升標準元件的工曰 作效率。 然而,隨著半導體技術的進步,在深次微米甚至奈米等級The layout structure of the components includes at least the base material. This quasi 7G and the second conductive type crystal gymnastics: ::: Electrician operation layer The electric type transistor operation layer is M-bit ^ base ^ on ', where the first two Among the two, the second lead is the P-type transistor operation layer and the N-type transistor operation layer is the P-type transistor gymnastic transistor operation. The layer includes at least extensions, and the first conductive type sub-operation area, the second conductive ^ extended operation area, the main operation area and the operation area, and the main operation layer includes at least a sub-operation of a rectangular extended transistor operation layer. On the substrate, where the first conductive first-metal layer, the first conductive type, the extended operation area are located through the first contact plug and the sub-operation area of the first layer, the more crystalline operation layer. The f operation layer of the secondary operation area is electrically connected, the second conductive type electrical metal layer, the second conductive type electrical :: shape extension operation area is located in the second electrical operation layer, the secondary operation area is more transparent through page 9 200415778 V. Description of the invention (6) Second contact plug and second gold Implementation method of metal layer connection: In the layout of traditional standard components, the extended operation areas of the P-type operation layer and the N-type operation layer need to be electrically connected to the upper metal layer through the contact plug, or they can be replaced by The L-shaped extended operating area is directly and electrically connected to the upper metal layer, thereby increasing the size of the P-type transistor and the N-type transistor to improve the working efficiency of the standard component. However, with the advancement of semiconductor technology, in the sub-micron or even nanometer level
的半導體製程中,此提升的幅度並不能讓標準元件提供足 夠的工作效率。In semiconductor manufacturing processes, this increase does not allow standard components to provide sufficient operating efficiency.
,同時參考第5圖和第6圖,第5圖所繪示為應用本發明之一 貫施例時的標準元件之佈局上視圖,第6圖所繪示為沿著第 5圖中CC’截面線所得之結構示意圖。如第5圖和第6圖°所 示’在本發明提供的標準元件100之佈局中,包括有p型電 晶體和N型電晶體的佈局,由P型井1 6 〇和n型井1 5 〇,以及p 型井16 0中的P+摻雜區162與N+摻雜區164和N型井150中的P + 摻雜區154與N +摻雜區152構成,半導體材料層HO作為閘 極。其中,標準元件1〇〇具有尺寸134,插塞122(如井接觸 插塞或基材接觸插塞)係用以電性連接P型操作層1 〇 2及P型 操作層102上方的金屬層110,插塞126(如井接觸插塞或基 材接觸插塞)係用以電性連接N型操作層11 2及N型操作層11 2 上方的金屬層120。 P型電晶體的P型操作層102中至少包括有主操作區1〇4和矩 形延伸操作區106 ’主操作區104具有尺寸136,而矩形延伸Referring to FIG. 5 and FIG. 6 at the same time, FIG. 5 shows an upper view of the layout of standard components when applying one embodiment of the present invention, and FIG. 6 shows a section along CC ′ in FIG. 5. Schematic structure of the line. As shown in FIG. 5 and FIG. 6 ', in the layout of the standard component 100 provided by the present invention, the layout of the p-type transistor and the N-type transistor is composed of a P-type well 16 and an n-type well 1 50, and P + doped region 162 and N + doped region 164 in p-type well 160 and P + doped region 154 and N + doped region 152 in N-type well 150, and the semiconductor material layer HO serves as a gate pole. Among them, the standard component 100 has a size of 134, and the plug 122 (such as a well contact plug or a substrate contact plug) is used to electrically connect the P-type operation layer 102 and the metal layer above the P-type operation layer 102. 110, the plug 126 (such as a well contact plug or a substrate contact plug) is used to electrically connect the metal layer 120 above the N-type operation layer 11 2 and the N-type operation layer 11 2. The P-type operation layer 102 of the P-type transistor includes at least a main operation area 104 and a rectangular extended operation area 106. The main operation area 104 has a size of 136 and a rectangular extension.
第10頁 200415778 五、發明說明(7) 操作區106係直接與上方的金屬層11()作電性連接, 體的N型操作層112中至少包括有主操作區114和矩形延^曰 作區116,主操作區114具有尺寸138,而矩形延伸操作區” 116係直接與上方的金屬層12〇作電性連接。金屬 屬層二者之一可電性連接至操作電壓(未層U另":: ^可接地(未繪示)。同時,介電層98位於金屬層丨1〇和p型 操作層102之間,金屬層120和N型操作層112之間,以及金 屬線1 3 2與基材1 8 0之間,而P型電晶體和n型電晶體之間的 電性連接係透過金屬線132與插塞182完成。 、 為:·在不改變標準元件的高度及尺寸下,讓標準元件提供 更尚工作效率與驅動能力,將P型操作層丨〇 2之延伸操作區 和N型操作層11 2之延伸操作區以矩形佈局,並且縮^矩^ 延伸操作區106和矩形延伸操作區116的尺寸,使得p型/曰 體和N型電晶體的尺寸增大,經由量測可得知,在第5中= 型操作層102之主操作區104的尺寸136約為〇 8 ,二 圖中主操作區14的尺寸46相比增加了〇.24 _,*第3圖Page 10 200415778 V. Description of the invention (7) The operating area 106 is directly electrically connected to the upper metal layer 11 (). The N-type operating layer 112 of the body includes at least a main operating area 114 and a rectangular extension. The area 116, the main operating area 114 has a size of 138, and the rectangular extended operating area "116" is directly electrically connected to the upper metal layer 120. One of the metal metal layers can be electrically connected to the operating voltage (not layer U). In addition, ":: ^ can be grounded (not shown). At the same time, the dielectric layer 98 is located between the metal layer 10 and the p-type operation layer 102, between the metal layer 120 and the N-type operation layer 112, and the metal line. 1 3 2 and the substrate 180, and the electrical connection between the P-type transistor and the n-type transistor is completed through the metal wire 132 and the plug 182., without changing the height of the standard component Under standard and size, let standard components provide more efficient work efficiency and driving ability, arrange the extended operation area of P-type operation layer 丨 〇2 and extended operation area of N-type operation layer 11 2 with rectangular layout, and reduce the moment ^ extended operation The size of the region 106 and the rectangular extended operating region 116 increase the size of the p-type / N-type transistor and the N-type transistor. According to the measurement, it can be known that the size 136 of the main operation area 104 of the fifth type operation layer 102 is about 〇8, and the size 46 of the main operation area 14 in the second figure is increased by 0.24 _, * Figure 3
主操作區14的尺寸86相比增加了〇.14 ,第5圖中N = #㈣114Mf138約⑽·6❹,與第’中 主細作區24的尺寸48相比增加了〇.24 μ,與 作區24的尺寸88相比增加了 0.14 #m,同時,筮^固占 呆 準元件Π0的尺寸134 ’仍然相等於第i圖中之標準元= 尺寸44及第3圖中之標準元件50的尺寸92。 的 請參考以下表一,表一所示為在傳統標準元件 及標準元件50)和本發明之一實施例+ ’P型電晶型電The size 86 of the main operation area 14 is increased by 0.14, and N = # ㈣114Mf138 in FIG. 5 is approximately ⑽ · 6❹, which is an increase of 0.24 μ compared with the size 48 of the main work area 24 in the middle. The size 88 of the area 24 is increased by 0.14 #m compared with the size 134 of the quasi-quasi element Π0, which is still equal to the standard element in the i-th dimension = the size 44 and the standard element 50 in the third Size 92. Please refer to the following Table 1. Table 1 shows the conventional standard component and standard component 50) and one embodiment of the present invention + ′ P-type transistor
第11頁 200415778 發明說明(8) 晶體之主操作區的尺寸比較表Page 11 200415778 Description of the invention (8) Comparison table of the size of the main operating area of the crystal
i #作區& 尺寸 £播作區之 尺寸 主#作區之 尺寸 _p翌電晶體 〇. 5 6 0.66 \im 0.8 \LiXl N型電晶體 0.3 6 0.46 \Lm 0.6 [im 支操作區之 尺寸為基隼 之提升幅度 1 约提升18% 至27% 约提升40°/〇 至 6 0 0/〇 經由量測傳統標準元件(標準元件1〇及標準元件5〇 明之一實施例在運作時電流的上升及下降速度, 下的表二,表二所示為應用傳統標準元件和本 施例時,電流上升及下降時所需時間的比較表* 73之一;i # 作 区 & Dimensions £ The size of the main cropping area_p 翌 Transistor 0.5. 0.66 \ im 0.8 \ LiXl N-type transistor 0.3 6 0.46 \ Lm 0.6 [im Dimensions are based on the increase of 1 1 about 18% to 27% about 40 ° / 0 to 6 0/0 by measuring traditional standard components (standard component 10 and standard component 50) The current rise and fall speeds are shown in Table II below. Table II shows one of the comparison tables of the time required for current rise and fall when the traditional standard components and this example are applied * 73;
第12頁 200415778 五、發明說明(9)Page 12 200415778 V. Description of the invention (9)
標準·元件1 0 標準·元# 50 標奉元# 100 電流上升所 需時間 69.2 63.1 57.3 電流下降所 需時間 46.1 40.6 34,7 以標準元# 為基率之提 升幅度 1 约提升10% 约提升20% 表二 從表一中可明顯發現,應用本發明之一實施例時,電流上 升所需時間比應用標準元件10時減少了約u. 9 ns,比應用 標準元 其電流 ns,比 在本發 積增加 加快, 本發明 構’係 光罩工 件5 Q時減 下降所需 應用標準 明之一實 ,使得運 於是標準 之優點為 應用在半 具資訊整 時間比應用標準元件1 〇時減少了約1 i4 元件50時減少了約5· 9 ns。由此可得知, 施例中,由於P型操作層和N型操作層的面 作時的速度加快,電流的上升和下降速度 元件1 00的工作效率及驅動能力得以提升。 提供一種積體電路佈局中之標準元件社 :體製程中,藉由本發明自動將各元;的 &為光罩工具資訊資料庫,可大幅提升整Standard · Element 1 0 Standard · Element # 50 Standard Fengyuan # 100 Time required for current rise 69.2 63.1 57.3 Time required for current decrease 46.1 40.6 34,7 Increase rate based on standard element # 1 Increase by about 10% About increase 20% Table 2 It can be clearly found from Table 1 that when one embodiment of the present invention is applied, the time required for current rise is reduced by about u. 9 ns compared with the standard element 10, and the current ns is larger than that in the standard element. The accumulation of the product is accelerated, and the present invention is one of the application standards required to reduce and decrease the photomask workpiece at 5 Q, so that the advantage of the standard is that the entire time of the application of the semi-information is reduced compared to the application of the standard component at 10 o'clock. It is reduced by about 5.9 ns for about 1 i4 element at 50. It can be known from this that, in the embodiment, as the speed of the P-type operation layer and the N-type operation layer is increased, the current rise and fall speed of the element 100 improves the working efficiency and driving ability. Provide a standard component company in integrated circuit layout: In the system process, & is a mask tool information database which can greatly improve the integration
第13頁 200415778 五、發明說明(10) :時:效率及準確度,由於在沒有增加元件面積的 ,就可以提升每個標準元件的P型/N型電晶體的尺十/ 此可大幅降低晶片的面積,$而降低產品電:本體的尺寸,因 =悉此技術之人員戶斤瞭解❾’以上所述僅$本發明之較 tn ’並非用以限定本發明之申請專利範圍;凡 匕未脫離本發明所揭示之精神下所完成之等效改變或佟 飾,均應包含在下述之申請專利範圍内。 ^Page 13 200415778 V. Description of the invention (10): Hours: Efficiency and accuracy. As there is no increase in component area, the ruler of P-type / N-type transistors for each standard component can be improved. This can be greatly reduced. The area of the chip reduces the product's electricity: the size of the body, because the person who knows this technology understands that the above only “the tn of the invention” is not used to limit the scope of the patent application of the invention; Equivalent changes or decorations made without departing from the spirit disclosed by the present invention shall all be included in the scope of patent application described below. ^
第14頁 200415778Page 14 200415778
圖式簡單說明 ,-丰 佈 第1圖係繪示包含有P型電晶體和N型電晶體的標準元彳之 局上視圖; . 第2圖係繪示沿著第1圖中AA,截面線所得之結構示意圖’佈 第3圖係繪示包含有p型電晶體和n型電晶體的標準元件之 局上視圖; 第4圖係繪示沿著第3圖中BB,截面線所得之結構示意圖’ 第5圖係繪示應用本發明之一實施例時的標準元件之佈局上 視圖;以及 第6圖係繪示沿著第5圖中cC,截面線所得之結構示意圖。 表一所示為傳統標準元件和本發明之一實施例中,p型電晶 體和N型電晶體之主操作區的尺寸比較表。 表一所示為應用傳統標準元件和本發明之一實施例時,電 流上升及下降時所需時間的比較表。 圖號對照說明: 10 標準元件 14 主操作區 18 接觸插塞 22 N型操作層 2 6 延伸操作區 30 金屬層 34 操作區 38 操作區 42 金屬線 4 6 尺寸 12 P型操作層 16 延伸操作區 20 金屬層 24 主操作區 Μ 接觸插塞 32 插塞 36 插塞 40 基材 44 尺寸 48 尺寸Brief description of the figure,-Feng Bu Figure 1 shows a top view of a standard element containing a P-type transistor and N-type transistor; Figure 2 shows a cross section along AA in Figure 1 Schematic diagram of the structure obtained from the line. The third figure is a top view of a standard component including a p-type transistor and an n-type transistor. The fourth figure is a diagram obtained along the BB and cross-section line of the third figure. Schematic diagram 'FIG. 5 is a top view of the layout of a standard component when an embodiment of the present invention is applied; and FIG. 6 is a schematic diagram of the structure obtained along the cross-section line cC in FIG. 5. Table 1 shows a comparison table of the sizes of the main operating areas of the p-type transistor and the n-type transistor in the conventional standard device and one embodiment of the present invention. Table 1 shows a comparison table of the time required for the current to rise and fall when the conventional standard component and one embodiment of the present invention are applied. Comparative description of drawing numbers: 10 standard components 14 main operation area 18 contact plug 22 N-type operation layer 2 6 extended operation area 30 metal layer 34 operation area 38 operation area 42 metal wire 4 6 size 12 P-type operation layer 16 extended operation area 20 Metal layer 24 Main operating area M Contact plug 32 Plug 36 Plug 40 Base material 44 Size 48 Size
200415778 圖式簡單說明 5 0 標準元件 60 半導體材料層 72 N+摻雜區 80 P型井 8 4 N +播雜區 88 尺寸 92 尺寸 96 L形延伸操作g 10 0 標準元件 10 4 主操作區 11〇 金屬層 114 主操作區 120 金屬層 124 操作區 12 8 操作區 134 尺寸 13 8 尺寸 15 2 N +摻雜區 160 P型井 164 N+摻雜區 180 基材 58 插塞 70 N型井 74 P+摻雜區 82 P +摻雜區 86 尺寸 90 介電層 94 L形延伸操作區 98 介電層 102 P型操作層 106 矩形延伸操作區 112 N型操作層 116 矩形延伸操作區 122 插塞 126 插塞 132 金屬線 136 尺寸 150 N型井 154 P+摻雜區 162 p+摻雜區 170 半導體材料層 182 插塞200415778 Brief description of the drawing 5 0 Standard element 60 Semiconductor material layer 72 N + doped region 80 P-type well 8 4 N + dopant region 88 Size 92 Size 96 L-shaped extension operation g 10 0 Standard element 10 4 Main operation area 11〇 Metal layer 114 Main operating area 120 Metal layer 124 Operating area 12 8 Operating area 134 Size 13 8 Size 15 2 N + doped region 160 P-well 164 N + doped region 180 Substrate 58 Plug 70 N-well 74 P + doped Miscellaneous region 82 P + doped region 86 Size 90 Dielectric layer 94 L-shaped extension operation region 98 Dielectric layer 102 P-type operation layer 106 Rectangular extension operation region 112 N-type operation layer 116 Rectangular extension operation region 122 Plug 126 Plug 132 metal line 136 size 150 N-type well 154 P + doped region 162 p + doped region 170 semiconductor material layer 182 plug
第16頁Page 16
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US11574901B2 (en) | 2020-04-29 | 2023-02-07 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device and method for manufacturing the same |
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US11574901B2 (en) | 2020-04-29 | 2023-02-07 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device and method for manufacturing the same |
US11942470B2 (en) | 2020-04-29 | 2024-03-26 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device and method for manufacturing the same |
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