TW200414517A - Integrated circuit embedded with single-poly non-volatile memory - Google Patents

Abstract

A system on chip (SOC) contains a core circuit and an input/output (I/O) circuit embedded with an array of single-poly erasable programmable read only memory cells, each of which comprises a first PMOS transistor serially connected to a second PMOS transistor. The first and second PMOS transistors are both formed on an N-well of a P-type substrate. The first PMOS transistor includes a single-poly floating gate, a first P+ doped drain region and a first P+ doped source region, the second PMOS transistor includes a single-poly select gate and a second P+ doped source region, and the first P+ doped source region of the first PMOS transistor serves as a drain of the second PMOS transistor.

Description

200414517

FIELD OF THE INVENTION The present invention relates to a 4 main address virtual m system logic process, which is manufactured by J JJ using f-body circuit USIC) or pass (N VM) integrated circuit. People said that the previous technology of silicon non-volatile memory was based on the design of the past. The electronic system is based on the main design, such as a microprocessor or a microcontroller, a memory device, and a peripheral device. The surface and the bus controller are connected to each other on the motherboard. With today's industrial technology, electronic systems can be integrated on a single chip, a so-called system on chip (S0C chip for short). The SOC chip is an integrated circuit, which includes a processor, embedded memory, various types of peripherals and external bus / interface. This embedded memory can be volatile memory (such as static memory or dynamic memory) or non-volatile memory (read-only memory or flash memory). Peripherals can be counters / timers, universal asynchronous transceivers (UARTs), parallel output / input circuits, interrupt controllers, or LCD controllers, graphics controllers, network controllers, etc., depending on the purpose of implementation. The external bus interface enables the S0C chip to be connected to a memory device or connected to other peripherals. Advances in SOC chip technology allow system designers to reduce the volume and test time occupied by electronic systems, increase reliability, and shorten product time to market.

200414517

For the system w tunnel, the integration of η 肊 into the standard logic process has a great advantage in that ρ, # 二; = ζ changes the single-layer polycrystalline stone used to manufacture logic circuits. S: a mechanism for private integration or simplified Heads. Based on this, the ticket has been issued. ΜII, a single-layer polycrystalline spar-only memory cell on the f base, which has: ^ Original: pole and ㈣ pole and-polyspar safari floating gate. However, Earlier in the early days, it was said that the polycrystalline silicon mere memory cell needs to have a _ expansion region set on the p-type substrate as a control gate, and through a layer of stone dioxide, the capacitor lightly closes the floating gate. This dioxide The silicon layer has a channel window (tunnel ind 〇w) 'open a and close to N' and the pole position for easy electronic penetration. This single-layer complex-crystal silicon read-only memory cell consists of a control gate and a floating gate. A capacitor 'is similar to a traditional stacked-gate or douplex — p0y y erasable programmable read-only memory (EEPR0M). However, the above N-channel single-layer crystalline silicon read-only memory cells must be operated at high voltages up to 20 V

Can only be programmed and erased, but this high voltage requirement limits the possibility of further reducing the component size. In U.S. Patent No. 6,04,018, sung and Wu disclose a single-layer complex silicon memory device that can be manufactured using a conventional complementary metal-oxide-semiconductor (CMOS) process. A complementary cell couples the floating gate of an N-channel metal-oxide-semiconductor (NM0S) device to the floating gate of a P-channel metal-oxide-semiconductor (PM0S) device, where each of the above gates covers at least part of the source and part of the non-electrode . This patent also proposes to use a channel adjacent to the source of the PMOS

Page 7 200414517 V. Description of the invention (3) Stop region to suppress the generation of the channel between the source and the drain, thereby eliminating the occurrence of the drain-to-source current of the PM0S, even if the source and the drain are between, so that The floating gate has a voltage sufficient to turn on the channel. The shortcomings of the single-layer polycrystalline silicon memory device disclosed in the above-mentioned U.S. Patent No. 6,044,0 18 include: first, the memory device consists of a PMOS device and an NMOS device, and a device separating the two components Field oxide layer, so memory devices will occupy a lot of valuable chip area. Second, this memory device requires an additional channel stop area. Thirdly, the memory device needs to be manufactured with a conductor or a wire for connecting two floating gates, which results in extra manufacturing process and cost. SUMMARY OF THE INVENTION Therefore, the main object of the present invention is to provide a single-layer polycrystalline silicon non-volatile memory that can be operated with a lower programming or write voltage and can be manufactured by a conventional logic process combined with a SOC wafer process. The single-layer polycrystalline silicon non-volatile memory device of the present invention can operate at a lower voltage and is a non-volatile memory with low power consumption and low energy consumption. Another object of the present invention is to provide an SOC chip with embedded high-density single-layer polycrystalline silicon non-volatile memory devices that is compatible with logic manufacturing processes, occupies less chip space, and saves power.

200414517 V. Description of the invention (4) Another object of the present invention is to provide a unique embedded high-density single-layer polycrystalline silicon non-volatile memory device and a method for operating the same. According to an embodiment of the present invention, an integrated circuit is provided, which includes a core circuit and an input / output circuit of a non-volatile memory cell array with a single-layered polycrystalline silicon embedded therein, wherein the single-layered polycrystalline silicon The non-volatile memory cell includes a first P-channel metal-oxide-semiconductor transistor sequentially connected to a second P-channel metal-oxide-semiconductor transistor. The first and second P-channel metal-oxide-semiconductor transistors are both disposed in a semiconductor doped well. The first transistor includes a single-layer polycrystalline silicon floating gate, a first drain, and a first source; the second P-channel metal-oxide semiconductor transistor includes a single-layer polycrystalline silicon selective gate and A second source, wherein the first source of the first transistor is used as the drain of the second transistor. In the stylized mode, a doped well voltage is applied to the doped well, and the source of the first transistor is biased with a first voltage, and the source of the first transistor is set to a single-layer polycrystalline silicon floating gate. A second voltage coupling activates a channel under the single-layer polycrystalline silicon floating gate. The advantage of the present invention is that, since the embedded single-layered polycrystalline silicon nonvolatile memory cell has the same transistor and device structure as the input / output circuit device (for example, the embedded single-layered polycrystalline silicon non-volatile silicon) The memory cell line is modified by some I / O circuit devices or made with the same design grid), so they can maintain a relatively high voltage compared to the core circuit device. The core voltage device can operate at lower voltages and faster speeds.

200414517 V. Description of the invention (5) In different process technologies, output and input devices with different operating voltage ranges have the same electronic behavior. At the same time, due to improvements in process technology, the device volume continues to shrink. Therefore, another object of the present invention is to provide a non-volatile memory cell with embedded single-layer polycrystalline silicon. The memory cell can be used in different generation process technologies. Therefore, the embedded #volatile memory cell can shrink in size as process technology advances. Embodiment Please refer to FIG. 1. FIG. 1 is a schematic block diagram of an integrated circuit of a single-layered polycrystalline silicon #volatile memory according to the present invention. As shown in FIG. 1, the integrated circuit 10 includes a core circuit 12 and an output / input (I / O) circuit 14. The core circuit 12 includes a plurality of core circuit components (such as PMOS or NMOS components' not shown in the figure) produced by advanced logic processes, such as 0.25 micron process technology, and the core circuit components have a relatively low voltage. Operate with faster speed. The use of a 0.25 micron process technology to produce a core circuit element refers to a critical dimension (CD) of 0.25 micron and a thin field oxide layer thickness, which enables the core circuit element to operate more quickly. . At present, the wafer process technology has evolved to 0.18 microns, 0.3 microns, or even less than 1,000 nanometers. The implementation of the present invention is not limited to the technical scope of 2.5 microns. The wheel-out input circuit 1 4 contains output-input components, which can withstand relative

Page 10 200414517 V. Description of the invention (6) Higher voltage (such as 3.3V). Part of the 3.3V input and output circuit elements is used to form an array 141 and a memory control circuit 142 with embedded non-volatile memory. Built-in non-volatile memory 141 and core circuit "The connection method of the memory control circuit 142 'is based on a wide range of technologies and technologies used in the industry, which will be briefly described below.' Please refer to FIG. 2 to FIG. One project is to provide a unique non-volatile memory device with embedded high-density monolayer polycrystalline spar and its related operation methods. Please refer to FIG. 2 and FIG. 3 first, and FIG. 2 is a non-volatile memory according to the present invention. The circuit of the body cell 5 means; 'I enlarged top view of the non-volatile memory cell layout of the present invention. As shown in Figures 2 and 2, the' non-volatile memory device 20 contains two serially connected ρ μ 〇 $ Transistor 201 and 202. PM0S Transistor 201 is used as a selection transistor or a switching transistor. Among them, the selection gate of PM 0 S transistor 2 01 is electrically connected to a word line. At this time, a selection gate voltage (v sg) is applied to the selection gate of the PMOS transistor 201 through a selected word line. The PM 0s selection transistor 2 0 1 also includes a source 3 0 1. A power line bias (v sl) and a drain 3 2 2 are used to couple P M 0 S Transistor 2 0 2. In this way, the drain 3 0 2 of the P M 0 S transistor 2 0 is also the source of the P 2 0 transistor 2 0. The P M 0 S transistor 2 0 2 Contains a single-layer polycrystalline spar floating gate 3 06 and a non-pole 3 3. A one-bit line bias (ν bl) is applied. Ρ μ 〇§Drain 3 2 of transistor 201 (also The source of the PM0S transistor 2 0 2) and the drain 3 0 3 are defined as a P channel under the floating gate 3 06.

Page 11 200414517 V. Description of the invention (7) " ^ ---- Please refer to Table 1 in Figure 19 and Figures 4 to 7 for the best mode of operation of Dou Yi low voltage memory. The programming / reading mode of silicon (slngle-P0ly) electronic programmable read-only memory device s yue (E = 0M) is described in Figure 4 "to Figure 7", respectively. As shown in the figure, the logic is written in the stylized mode, and the positive voltage of 5V 'ranges from 3 to 8V. It is better to select a bit line to apply a better vertical line to ground, and not press. The source of crystal 201 is a positive voltage VSL between 3 and 8V. For N-type doped wells (NW), a voltage of 5V is applied, and PMOS selects a transistor 2〇 = t well voltage. The p channel under the above floating gate will open, and Ji will: inject the channel hot electrons into the single layer with the floating ^ 2 of the polycrystalline silicon PMOS transistor 202 of the MOS transistor 202 As shown, p々 and the element line are grounded, and the f-type writing logic "0" is not selected. The selected word is preferably 5V. The range dielectric and the selected bit line apply a source. A positive voltage of about 'approximately' is applied. One of the transistor 201 is doped well voltage of about 5V, and the source line voltage is VSL. The N-type doped well is applied with a floating gate electrode, # Under the above conditions, the PM0S transistor 2 0 2 is injected into the floating gate. 糸 is in the "off" state, and the electrons are not shown in Figure 6, and Lu-Oshi is grounded. When the reading mode is not selected ~, the selected character line is a normal line. A bias voltage of about 2.5V to 5V is applied. Be

200414517

The selected word line is applied with a bias voltage of about 0V to 2.5V. The unselected bit lines are biased at approximately 3.3V. The power line voltage and the N-type doped voltage are about 2.5V to 5V. When a programmed memory cell is read, the floating gate system is charged, and Vfg_Vs < Vthp (v ^ is the threshold voltage of PM 0 2 electric body 0 2), the memory cell Maintain a "On (On)" status. If the floating pole of the unprogrammed memory cell is not charged, then V FG- V s> V THP, the memory cell line is in the "off (0ff)" state, and the energy is not significant. The current I is equal to the floating gate voltage.

Nine .., the PM0S transistor that is not selected (the channel is used in the field: the same non-pole pair N doped well bias V, thermoelectric :; HE gas operation), according to the most c of the present invention. As shown in Figure 8 and Figure 9, V 杓 is -5V to -6V. In the floating gate and the bias of the pole to the N-type doped well i.ox can be further described as a month, such as 1 β m maximum gate current.

The closed pole obtains two phases; = ;: When the voltage ¥ is -5V, the floating I is about 5x 1 〇-11 a A / k is turned on and reaches a maximum gate current. Lei Qing: Brother? In other words, according to the present invention, ^ can be achieved during the input operation-= the ratio (18) is increased. Figure 10 is a top view of the part according to the present invention. As shown in Figure 10 of the non-volatile memory array of single-layer polycrystalline spar, a stylized (write logic

Page 13 200414517 V. Description of the invention (9) 1 M) Memory cell I (part particularly indicated by a dotted circle on the figure), a bit line voltage V b of 5 V to 6 V is applied to the memory cell The drain of the floating gate PM0S transistor. The selection gate of memory cell I is grounded. On the same bit line, other unprogrammed memory cells (memory cells I j, III, IV) will not suffer from source interference that would occur when programming a traditional stacked gate memory device for programming . Please refer to FIG. 11 and FIG. 12, wherein FIG. 11 shows an N-type non-volatile memory cell circuit according to another preferred embodiment of the present invention. FIG. 12 is a non-volatile memory cell shown in FIG. The enlarged top view of the layout. As shown in Fig. 11 and Fig. 12, the non-volatile memory device 20 includes two NMOS transistors 401 and 402 connected in series. The NMOS transistor 40 1 is used as a selection transistor or a switching transistor, and the selection gate of the NMOS transistor 401 is electrically connected to a word line. During operation, a selected gate voltage ν 3 is applied to the NMOS transistor 401 through a selected word line. The NMOS selection transistor 4 0 1 further includes a source line bias ν source 6 0 1 and a coupled NMOS transistor 4 0 2 drain 6 0 2. That is, the drain 602 of the NMOS transistor 401 is also used as the source of the NMOS transistor 402. The NMOS transistor 40 2 further includes an early polycrystalline spar floating gate 6 06 and a non-polar 6 0 3 applied with a bit line bias (V BL). The drain 6 0 2 of the NMOS transistor 4 0 1 (also the source of the NMOS transistor 4 0 2) and the drain 6 0 3 define an N channel under the floating gate 6 6. Please refer to FIGS. 13 to 16 for the single-layer polycrystalline silicon N-type of the present invention.

Page 14 200414517

Description of the best stylized diagram of the non-surface-compressed online volatile memory device. As shown in Thirteen, the Bethel system is used to select the character line system by cutting a range from 3 to 2: 2: Edit " 1. The selected bit line is applied with a positive voltage vSL in the range ^. Under the condition of p-type doped well (Pm application = electrical two-state, choose the gate of transistor 40kN channel 0 ^ to change the voltage of the starting well. In the spleen you will be turned on -β, and the channel heat will be injected. 6Hai early layer polycrystalline silicon NMOS transistor 402 floating gate .., Characters: 'Write logic in stylized mode " 〇 ", a range is selected by the sub-wire system Between 3 and 8V, a voltage of ον is applied to the voltage between 彳 and ^. The nozzle, and electric sinker are applied by the well Γί i =: SL. The p-type doped well (") is applied with -ον Τ ^ ^ Λ P; g ^ NM〇St ^ 11 4〇2 ^ ^ ^ ^ As shown in Fig. 15, the voltage V is applied between about 0V and 2.5V. 0 V to 2.5 V, the comparative doped well voltage system is the operation system according to Figure 17 'select the word line in the data read mode. It is selected as a bias voltage of 1 V. As shown in Figure OV bias voltage. The unselected bit line of 1 V is 0V. When the relationship diagrams shown in Figures 13 to 10 are implemented, a 3 · 3 V selection element line is applied as shown in Figure 16 and is not Select Weifang line to apply > -voltage. Power line voltage Related to Six of Memory Cells

N 200414517 V. Description of the invention (π) To sum up, the present invention provides embedded circuit of integrated circuits that can be applied to different generations of process technology (such as 0.2, 0.5, 1.8, 0.3, etc.). Unique non-volatile memory, such as electronic programmable read-only memory (EPROM) or write-once (0TP) memory cells. No matter the core circuit logic manufacturing process of the integrated circuit is in any generation, a part of the 3.3 V input / output device can be used to generate a non-volatile memory array and memory control circuit. No additional mask is required for this non-volatile memory. Under each logical process generation, the development time for non-volatile memory with embedded logic can be shortened accordingly. In addition, the high electric field used to program the non-volatile memory cell is no longer consumed by the input / output device. In this way, the gate oxide layer of the input / output device and the area from the interface to the well will no longer appear, and Can guarantee the reliability of the device. The above description is only a preferred embodiment of the present invention, and any equivalent changes and modifications made in accordance with the scope of the patent application of the present invention shall fall within the scope of the patent of the present invention.

200414517 Brief description of the diagram Brief description of the diagram Figure 1 is a block diagram of an integrated circuit of a single-layer polycrystalline silicon non-volatile memory according to the present invention. Figure 2 shows a p-type non-volatile memory cell according to the present invention. Figure 3 is an enlarged top view of the non-volatile memory cell layout shown in Figure 2. Figures 4 to 7 are schematic diagrams of the operation of the present invention. Figure 8 shows the relationship between the non-polar current I d and the floating gate voltage.

Figure 9 shows the selected PM0S transistor (operated with channel hot electron (CHE)) under different drain-to-N-doped well bias voltages (Vd = VB "VNW). Its gate current IG versus floating gate The relationship between the gate voltages. Fig. 10 shows a single-layer polycrystalline silicon non-volatile memory array according to the present invention. Fig. 11 shows an N-type non-volatile memory cell according to the present invention. An enlarged top view of the non-volatile memory cell layout is shown. Figures 13 to 16 are schematic diagrams of the operation of the present invention. Figure 17 shows the relationship between the gate current of the NMOS transistor and the floating gate voltage.

FIG. 18 is a single-layer polycrystalline silicon non-volatile memory array (NMOS ce 1 1) according to another preferred embodiment of the present invention. Table 1 in Figure 19 shows the best mode for low voltage memory operation.

Page 17 200414517 Brief description of the drawings Symbols of the drawings

Page 18 10 Integrated circuit 12 Core circuit 14 Input / output circuit 141 Embedded memory array 142 Memory control circuit 20 Non-volatile memory device 201 P-channel metal oxide semiconductor transistor 202 P-channel metal oxide semiconductor transistor 301 source Pole 302 Drain 303 Drain 306 Floating Gate 40 Non-volatile memory device 401 N-channel MOS transistor 402 N-channel MOS transistor 601 Source 602 Drain 603 Drain 606 Floating gate

Claims (1)

200414517 VI. Application Patent Scope 1. An integrated circuit with a single-layer compound silicon non-volatile memory (NVM), the integrated circuit includes: a core circuit; and an output input (I / 0) circuit, the I / 0 circuit embeds an array of single-layer polycrystalline silicon non-volatile memory cells, wherein each of the single-layer polycrystalline silicon non-volatile memory cell lines is disposed in a semiconductor substrate, The single-layer polycrystalline silicon non-volatile memory cell includes: a doped well disposed in a semiconductor substrate and electrically connected to a well voltage; a first metal-oxide-semiconductor (MOS) transistor disposed in the doping In the well; a drain level belonging to the first metal oxide semiconductor transistor, electrically connected to a one-bit line voltage; a second metal oxide semiconductor transistor, disposed in the doped well; a metal oxide semiconductor belonging to the first metal oxide semiconductor The source of the crystal is electrically connected to a drain of the second metal-oxide-semiconductor transistor; and a source of the second metal-oxide-semiconductor transistor is electrically connected to a power line voltage; wherein the first metal Oxygen semiconductor transistor Comprising a floating gate, wherein the floating gate is electrically isolated from other control terminal, and the gate of the second MOS transistor is electrically connected to the electrode line a select gate voltage. 2. The integrated circuit of the embedded single-layer polycrystalline silicon non-volatile memory as described in item 1 of the scope of the patent application, in which the 200414517 6. Under the application patent range voltage, the selection gate voltage is applied to the gate of the second metal-oxide-semiconductor transistor to turn on the second metal-oxide-semiconductor transistor and apply the voltage to the first metal-oxide-semiconductor transistor. A voltage drop is provided between the drain of the second metal oxide semiconductor transistor and the source of the second metal oxide semiconductor transistor, so that a carrier can be injected into the gate of the first metal oxide semiconductor transistor. 3. The integrated circuit of the non-volatile memory with a single-layered polycrystalline silicon embedded as described in item 1 of the scope of the patent application, wherein the first and second metal oxide semiconductor transistors and the metal oxide of the input and output circuits Semiconductor transistors have the same electrical behavior. 4. The integrated circuit of the single-layer polycrystalline silicon non-volatile memory as described in item 1 of the scope of the patent application, wherein the output and input circuit further has a memory control circuit embedded therein. 5. The integrated circuit of the non-volatile memory with a single layer of polycrystalline silicon embedded as described in item 4 of the scope of patent application, wherein the memory control circuit includes a sense amplifier (sense amplifier), one character A line decoder, a bit line decoder, a word line driver, a bit line driver, and a charge charging circuit. 6. The integrated circuit of the embedded single-layer polycrystalline silicon non-volatile memory as described in item 1 of the scope of the patent application, wherein the embedded single-layer polycrystalline silicon non-volatile memory can be applied to different generations Process technology Page 20 200414517 VI. The output and input components of the patent application generation process are each operated at the same operating voltage range. 7. An integrated circuit with embedded single-layer polycrystalline silicon non-volatile memory. The integrated circuit includes: A core circuit; and an input / output circuit, the input / output circuit is embedded with an array of single-layer polycrystalline silicon non-volatile memory cells, wherein each of the single-layer polycrystalline silicon non-volatile memory cell lines is disposed at In a semiconductor substrate, the single-layer polycrystalline silicon non-volatile memory cell includes: a doped well disposed on the semiconductor substrate and coupled to a well voltage; a first gold-oxygen semiconductor transistor disposed on the doped silicon substrate; In a well; a drain electrode belonging to the first metal oxide semiconductor transistor coupled to a bit line voltage; a second metal oxide semiconductor transistor disposed in the doped well; a source electrode belonging to the first metal oxide An oxygen semiconductor transistor is used as a drain of the second metal oxide semiconductor transistor; a source electrode belonging to the second metal oxide semiconductor transistor is coupled to a power line voltage; wherein, the A MOS transistor comprises a floating gate, wherein the floating gate is separated from the other control terminal, and the gate of the semiconductor transistor and the second metal-oxide-based electrode is electrically coupled to a select gate voltage. 200414517 6. Scope of patent application 8. The integrated circuit of the non-volatile memory with embedded single-layer silicon as described in item 7 of the scope of patent application, wherein, in the programming mode, at the well voltage, the The gate voltage is selected to be applied to the gate of the second metal-oxide-semiconductor transistor to turn on the second metal-oxide-semiconductor transistor, and the drain of the first metal-oxide-semiconductor transistor and the second metal-oxide-semiconductor transistor are turned on. A voltage drop is provided between the sources of the transistors, so that carriers can be injected into the gate of the first metal-oxide-semiconductor transistor. 9. The integrated circuit with embedded single-layer polycrystalline silicon non-volatile memory as described in item 7 of the scope of patent application, wherein the first and second metal oxide semiconductor transistors and the metal oxide of the input and output circuits Semiconductor transistors have the same electrical behavior. 10. The integrated circuit of the non-volatile memory with a single layer of polycrystalline silicon embedded as described in item 7 of the scope of the patent application, wherein the output and input circuit further has a memory control circuit embedded therein. 11. The integrated circuit of a non-volatile memory with a single-layered polycrystalline silicon embedded as described in item 10 of the scope of the patent application, wherein the memory control circuit includes a sense amplifier circuit and a word line decoder , A bit line decoder, a word line driver, a bit line driver, and a charge charging circuit. 1 2.Inlined monolayer polycrystalline silicon non-volatile as described in item 7 of the scope of patent application 200414517 VI. Integrated circuit of patent-memory scope memory, in which the embedded single-layer polycrystalline silicon non-volatile memory can be applied to different generation process technologies, among which the input and output elements of each generation process are their own Operates at the same operating voltage range 1 3. —A kind of integrated circuit with a single-layer complex silicon non-volatile memory embedded, the integrated circuit includes: a core circuit; and an output input circuit, the output input circuit A single-layer polycrystalline silicon non-volatile memory cell array is embedded, wherein each of the single-layer polycrystalline silicon non-volatile memory cell lines is disposed in a semiconductor substrate, and the single-layer polycrystalline silicon non-volatile memory cell The cell includes: an N-type well disposed in a semiconductor substrate and electrically coupling a well voltage; a first P-channel metal-oxide-semiconductor (PM0S) transistor disposed in the N-type well; one belonging to the first The drain of the P-channel metal-oxide-semiconductor transistor is set in the N-type well; a second P-channel metal-oxide semiconductor transistor is set in the N-type well; a metal-oxide semiconductor that belongs to the first P-channel A source region of the transistor, is electrically connected to the drain of the second P-channel MOS extreme; and belonging to a source of the second P-channel MOS transistor of region electrically coupled to a power line voltage; 200414517 6. The scope of the patent application, among which the first P-channel metal-oxide-semiconductor transistor includes a floating gate, wherein the floating gate is electrically isolated from other control terminals, and the second P-channel metal-oxide-semiconductor transistor is electrically isolated. The gate is electrically coupled to a selected gate voltage. 1 4. The integrated circuit of a single-layer compound silicon non-volatile memory as described in item 13 of the scope of the patent application, wherein, in the stylized mode, at the well voltage, the selected gate voltage is selected. Is applied to the gate of the second metal oxide semiconductor transistor to turn on the second metal oxide semiconductor transistor, and is applied to the drain of the first metal oxide semiconductor transistor and the source of the second metal oxide semiconductor transistor A voltage drop is provided between the electrodes to allow carriers to be injected into the gate of the first metal-oxide-semiconductor transistor. 15. The integrated circuit of the non-volatile memory with embedded single-layer polycrystalline silicon as described in item 13 of the scope of the patent application, wherein the first and second metal-oxide-semiconductor transistors and the output-input circuit are integrated circuits. Metal-oxide semiconductor transistors have the same electrical behavior. 16. The integrated circuit of the embedded single-layer polycrystalline silicon non-volatile memory as described in item 13 of the scope of the patent application, wherein the embedded single-layer polycrystalline silicon non-volatile memory can be used for Process technology of different generations, in which the input and output elements of each generation process are operated in the same operating voltage range. Page 24 200414517 VI. Scope of patent application 1 7. —Integrated circuit with embedded single-layer polycrystalline silicon non-volatile memory, the integrated circuit includes: a core circuit; and an output input circuit, the output input A single-layer polycrystalline silicon non-volatile memory cell array is embedded in the circuit, wherein each of the single-layer polycrystalline silicon non-volatile memory cells is disposed in a semiconductor substrate, and the single-layer polycrystalline silicon non-volatile memory is The body cell includes: a P-type well disposed in the semiconductor substrate and electrically coupling a well voltage; a first N-channel metal-oxide semiconductor transistor disposed in the P-type well Within; a region of the first N-channel metal-oxide-semiconductor transistor electrically coupled to a one-bit line voltage; a second N-channel metal-oxide-semiconductor transistor disposed in the P-type well; one belonging to the first A drain region of an N-channel metal-oxide-semiconductor transistor, electrically connected to a drain region of the second N-channel metal-oxide-semiconductor transistor; and a source region belonging to the second N-channel metal-oxide-semiconductor transistor, Electrically coupling a power line voltage; The first N-channel metal-oxide-semiconductor transistor includes a floating gate, wherein the floating gate is electrically isolated from other control terminals, and the gate of the second N-channel metal-oxide-semiconductor transistor is electrically coupled. One selects the gate voltage. Page 25 200414517 VI. Scope of patent application 1 8. Integrated circuit of single-layer polycrystalline silicon non-volatile memory as described in item 17 of the scope of patent application, where in the stylized mode, the choice The gate voltage is applied to the gate of the second N-channel metal-oxide-semiconductor transistor to turn on the second N-channel metal-oxide-semiconductor transistor, and the drain of the first N-channel metal-oxide-semiconductor transistor and the A voltage drop is provided between the source regions of the second N-channel metal-oxide-semiconductor transistor to allow holes to be injected into the gate of the first N-channel metal-oxide-semiconductor transistor. 1 9. The integrated circuit with a single-layered compound silicon non-volatile memory as described in item 17 of the scope of the patent application, wherein, in the clear mode, the selection gate voltage is applied to the second N The gate electrode of the channel metal oxide semiconductor transistor is used to turn on the second N channel metal oxide semiconductor transistor, and the drain of the first N channel metal oxide semiconductor transistor and the second N channel metal oxide semiconductor transistor are turned on. A voltage drop is provided between the source regions, so that electrons can be injected into the gate of the first N-channel gold-oxide semiconductor transistor. Guiding the non-semi-silicon crystalline gold multi-layered single-layer and embedded one-layer statement, the net of the network is 1 ±, and the body of the electric circuit of Fanwei Electric Co., Ltd., please apply for the body to remember. • The second phase has crystals in the same phase. Lead the input and output of the semi-oxygen route and lose. With the crystallinity of the body ^ 0 The body of E »ί kr Three broken seconds day aa day B0 Multi-layered layer COLCOLQL σιΒΡ Port BJp Embedded in the statement, the network of China 11 Accumulation of the application of the body Shen Yi Ru Ji 1 sex 2 rounds Page 26 200414517 6. Scope of patent application Generic memory can be applied to process technology of different generations. Among them, the input and output elements of each generation process are operated in the same operating voltage range.路 ^ β Volume body memory memorizing f_L # tr ¥ Crystal multi-layer ·. Includes in-package encapsulation and electric integration • Product 2 2 The crystal multi-layer single 1 in-embedded input and output 43 — and, to Circuit; power input, power output, core output, silicon output, silicon shards, crystals, multi-layers, and one by one, each one in the bottom, the base in the body, the conductor, half a row in the cell body, set memory cell Jifeng = oral memory notes # ^ Non-fat silicon swing well 1 connect-\ gc sex and inner base: the body has a guide containing half of the cell in the body memory design, sex well one > L # kr sex Γ ^ ΠΓ •, in the region Well poles should be placed in the body crystal, electric body crystal guide ^ a '* ΐ integrated oxygen conduction gold semi-oxygen gold first one in the first internal well should be placed in the body crystal i & ioD ^ E body • , The pressure semi-electric oxygen wire gold yuan two first one fc & w electrode electric body drain guide ^ 立 u ^ iu 一 " oxygen crystal oxygen x71 ^ ¾ ^ one ^ one second guide first half The body of oxygen is a metal, the body of the crystal is the body, and the body is used as the domain source. Including inclusion crystals ^ va body conducting semi-oxygen •, gold pressure-electricity, the line, the source, ^ gnp U, which is connected to the power and the pole, and the gate, select the isolation from the coupling to the coupling terminal to control the electricity It is the gate of the pole and the gate of the moving crystal floating electric body, which conducts half of its oxygen, and the gold pole II'—Ml IIII —ί — ^ 1 ί I It- Page 27 200414517 Page 28