TW200414470A - Semiconductor chip scale packaging method - Google Patents

Abstract

A semiconductor chip scale packaging method contains the following steps. First, put a chip on the substrate installation surface to let the pads exposed by the corresponding through holes. Second, use photo-resist (PR) to form a first protection layer covering the chip on the substrate surface and to fix the chip on the substrate. The first part of the first protection layer is exposed to UV light but the second part of the first protection layer not. Through the following chemical clean treatment, only the said first part located on the chip periphery is retained. Third, by wire bonding, the chip pads connect the corresponding circuit layout of the substrate layout surface through the wire of corresponding through holes. Forth, use PR to form a second protection layer on the substrate layout surface. Through similar exposure and chemical clean treatment, only the part covering the wires is retained. Finally, form plural conduction balls that correspond to the circuit layout connection on the substrate circuit layout surface.

Description

200414470 V. Description of the invention (1) [Technology to which the invention belongs The present invention has a more specific packaging method. [Previous technology] The first field of display technology: :: ϋ A method for packaging a semiconductor wafer package. Compared to a semiconductor wafer package with a reduced cost, the wafer package includes 10, a solder pad 110 (A kind of 4 known semiconductor wafer package. The semiconductor has a substrate 5 with a circuit track layout surface 1 0 0 and a number of cores mounted on the mounting surface of the solder pad ... 4 only shows one solder Pad) of the wafer 11, a first protection layer 12, and a second protection layer 丨 3. The substrate 10 has a perforation 1 0 1 1 1 The wafer 11 is exposed in the 101 case (the surface 1 0 0 is not laid out in the figure and the phase 11 0 is connected through a circuit passing through it. There are several uses The corresponding bonding pad 0 of the wafer 丨 is exposed, and the bonding pad 110 of the wafer 10 is pierced by the corresponding perforation of the substrate 10 (not disposed between the wafer 11 and the substrate 10). The day 70 of the pair of the base body 10 and the circuit track is not placed on the surface. The pad 111 of the die 11 corresponds to the lead 111 of the perforation 101 to track the circuit (not shown) on the surface 100 of the substrate 10. The first protected wafer sets the circuit track of the second protection 10 Cloth and other perforations 1 0 1. The layer 12 is covered with the epoxy resin as the material on the substrate 10 to cover the crystal element; [丨. Layer 1 3 is also covered with epoxy resin on the surface 100 of the substrate. It can cover the wires 111 and 200414470. V. One of the description of the invention (2) However, the unit price of adhesive tape and epoxy resin is relatively high. The packaging cost of a semiconductor wafer package is as follows: The door is so [Inventive Content] "Yeah. In view of this, the inventor of this case has worked with him and in the spirit of excellence, actively research and improve the experience "Semiconductor wafer package packaging method" is produced. The present invention "is an object of the present invention is to provide a cost package package method. Low semiconductor crystals according to the invention-feature, a semiconductor wafer sealing method 'Contains the following steps: providing-semiconductor wafer, where = body welding ί = and several solder pads mounted on the surface ;: two 二 set the surface, one and the circuit track two = holes, in the substrate The circuit track layout surface is provided with a predetermined track on the surface, and the book is placed on the wafer mounting surface of the substrate so that the corresponding perforations of the substrate are exposed; A first: protective: covering the crystal element is formed on the crystal mounting surface of the soil body; the crystal element can be fixed on the substrate; by exposing the first part of the first protective layer to ultraviolet light, The second part of it is shielded from being exposed to the outer line of i and it is only located around the wafer by subsequent chemical washing treatment. The first part of the first protective layer is retained; by wire treatment " Haiyuan's welding pad is electrically connected to the corresponding circuit track on the surface of the circuit track layout through the corresponding perforated wire passing through the substrate; a photoresist material is used to form a first on the circuit track layout surface of the substrate. Two 200414470 V. Description of the invention (3) Protective layer; by invitation, only the first !! The similar exposure and chemical washing of the first protective layer on the substrate: the part of the protective layer covering the wires Is retained; and a plurality of corresponding circuits are formed on the guide wiring surface of the electrical connection. According to the present invention, a mounting method includes a stern feature, a semiconductor wafer package, and a solder package installation step. Provides a Semiconductor crystal The wafer is provided with a pad; a welding-first # $ ® of a plurality of crystals on the mounting surface of the welding pad is placed on the surface of a substrate; the first protective layer is formed using a photoresist material: f The surface can be covered with distant crystal elements; by shielding and not exposed to ultraviolet light :: ί f to ultraviolet light and the second part of the surface is protected by 塾 An crack surface system, part of the younger brother is kept and The welding method of the wafer forms a plurality of conductive pads which are printed on the mounting surface of the rugged pad; a first material layer that is two-layered with the first-part layer is in the first protection.

A conductive ball is formed in the female-exposed hole. According to the difference of the present invention, the exposure method of the wound is-4 ± / jUL J method, which includes the following steps: extracting; sealing of the seed crystal package body = trace layout table ... and the substrate has an -electrolytic surface , And several perforations corresponding to the wafer :: two; the perforations corresponding to the wafer's relief pads on the surface,

Description of the invention (4) A pre-material is arranged on the surface of the wafer mounting surface of the substrate on the 2-way track layout surface; the circuit track of the j-circuit is mounted on the substrate; the photoresist is mounted on the mounting surface and several security layers are used. Partially exposed "violet: f a protective layer; by chemical shielding treatment of the first-protective layer ^, which is shielded from being exposed to ultraviolet light and # by = line and the second part of which is only around the wafer A wafer can be formed. The first part is a semiconductor crystal with a pad mounted on the surface retained. The solder on the wafer is held by the substrate = the wafer. The holes are processed by wires, and the bonding pads of the wafer are exposed through the perforations of the teeth; the wires are connected to the corresponding perforations on the surface of the circuit track layout by using wires; the photoresist material is used on the substrate. Electrical circuit track electrical connection second protection > · Launching a rinsing process is formed on the surface of the track layout, only the exposure and chemical retention of the second protection layer is similar; and the A ^ ^ ^ Part of these wires is insured by the insurer AA & Electric ball. &Amp; Forming a number of corresponding and yet another feature according to the present invention, a method for encapsulation of fertile bass, including the following steps m, the body is called "above the package 丨 by putting the first The same tank = a first protective layer on a substrate, second 1 f ^ = π π, the first part of the 4 layer is exposed to ultraviolet light and it should not be exposed to ultraviolet light and treated by chemical washing: : The first part of the 4 layer can form a wafer containing one and the wafer can be placed on the wafer containing == the surface of the welding conductor several conductors, # 一 导 ； = !; 上Forming the electricity-conducting strand mother conductor by printing has a corresponding pad extending to the wafer 1. Page 8 200414470 V. Description of the invention (5) = the first part and a predetermined distance from the first part The second part of the distance; using a photoresist material to form a second protective layer on the first protection ^ ^ can cover the conductors; and by applying the second exposure and chemical processing, the second The second part of the conductive body corresponding to the protective dew is exposed and a conductive ball is formed. A protective layer on a part of the surface is similarly formed into several exposure holes for each exposure hole. [Embodiment] In the detailed description of the present invention, similar elements have clearly disclosed the special dimensions of the present invention and are not The first to sixth figures are drawn to scale. The first preferred embodiment of the display method is shown in the second figure. The element 2 has a pad mounting table pad 21 (only shown in the figure. Then, as shown in the third figure). The body 3 has a perforation 32 corresponding to the wafer mounting surface 30 and the corresponding wafer mounting table. A predetermined circuit trace is provided on the base (the wafer 2 is placed on the base in its case and then Before using a photoresist material, it should be marked with the same reference numerals and drawings. The schematic flow chart of the semiconducting device of the present invention is noted that, on the other hand, it is marked first. · _ 丨 Crystal plane 20 and several solder pads). As shown in the figure, the circuit implementation of one base surface 30, one side 31, and several individuals 3 are not shown in the figure). The bonding pad 21 is mounted by the wafer of the base 3. The base 3 is not provided according to the actual package of the wafer package of the element. The yuan 2 is provided. The solder body 3 having the crystal mounted on the surface 20 is provided. The base and the circuit track layout. Set the table and the pad 21 of the wafer 2 on the surface 31 where the perforations 32 of the cloth body 3 are exposed on the surface 30. Wafer mounting surface 31

Page 9 200414470 5. Description of the invention (6)-Forming a first protective layer 4 covering the wafer 2 allows the wafer 2 to be deposited on the substrate 3. After forming the -protective layer 4 <, the second part 40 of the first sound 4 is exposed to ultraviolet light and the second part is shielded, the heart is exposed to ultraviolet light and by subsequent chemical washing In the treatment, only the first part 40 of the second protective layer 4 around 2 weeks is shown in the second and fourth figures. Geshe step Next, by wire bonding, the pad 21 of the wafer 2 is electrically connected to the corresponding circuit track on the circuit track layout surface 30 through the wire 5 of the corresponding through-hole 32 of t. After the wire bonding process, the photoresist material is used to lay the surface 3 on the Thunder Road J trace of the substrate 3. A second protective layer 6 is formed on the substrate; 5; = 2; == a guarantee; similar exposure and chemistry of layer 4 are retained: ... covering the part of these wires 5 _ spots :: the substrate 3 A conductive ball 7 is formed on the circuit track layout surface 30 to electrically connect the circuit tracks. It should be noted that the following steps may be included in the subsequent strengthening of the lead 5. ㈣ Degree 'in the wire bonding step of the substrate ten: shown, after the wire bonding step, a very thin insulating layer is formed at least from the surface portion of the 2A near the perforation and the insulating material like the wafer resist material. ; =

& S4 Page 10 200414470 V. Description of the invention (7) Reinforced wire 5 and opposite welding 9 1 Ώ It should be noted that; forming the physical connection between the ^ circuit rail ° attached to it, > 2 The Λ ,, Bar, and 彖 layers are the same on the same day, and the wire 5 also has a lambda. The insulation layer 8 # material so that a 5 2 H wire 5 strength reinforcing layer 5 is formed on each of the 5 wires.俾 can avoid the situation where the wire 5 is broken in the subsequent processing. The invention is free from the use of adhesive tape to attach the wafers and the second protective layers 4 and 6, so that the grease to form f-low. The package cost of the Gi body can be effectively reduced. The seventh to eleventh figures show the second preferred embodiment of the lane-touching Θ-α method of the present invention. The + conductor is the package side of the package. Please refer to the seventh figure. Half of the package is on the surface 33 of the substrate 3. Bu Yangyang 2 is first placed on, and then formed with a photoresist material-the first-protection surface 33 can cover the crystal element 2, such as 篦 °; on the 忒 substrate 3 then 'by protecting the first protection Layer 4, H Middle / Kin shown. The second part of the wire is shielded and not exposed = H. The wound is exposed to the ultraviolet washing treatment, and only the second soil is located around the wafer 2. The second soil is chemically washed by 40, which is retained and the wafer 2 The solder pad mounting surface = the first part is shown in the ninth figure. The text surface 20 is exposed. For example, after P is returned, a plurality of conductors 9 are formed on the solder joint of the wafer 2. Each guide; H ° is printed in the first part of the corresponding pad 21 and a second part with a distance of 2 to the wafer. Yidi " stabbing each other

Page 11 200414470

V. Description of the invention (8) Now refer to the tenth figure, and then use a photoresist material to form a second protective layer 6 'on the surface of the first portion 4 of the first protective layer. The electrical conductors 9. Subsequently, the second protective layer 6 is formed with & exposure holes β for exposing the second part of the corresponding conductive body 9 through exposure and chemical processing similar to those applied to the first protective layer. 〇. Next, a conductive ball 61 is formed in each exposure hole 60, as shown in the eleventh figure. Figures 12 to 16 show a third preferred embodiment of a method for packaging a semiconductor wafer package according to the present invention. Please refer to FIG. 12, which is different from the first preferred embodiment. In this preferred embodiment, a first protective layer 4 formed of a photoresist material is first formed on a substrate 3. Mounting surface 31. The structure of the base body 3 is the same as that described in the first preferred embodiment. Then, by exposing a first portion of the first protective layer 4 to ultraviolet rays and shielding a second portion thereof from being exposed to ultraviolet rays, and by subsequent chemical washing treatment, The second part is removed to form a wafer receiving hole 41, as shown in the thirteenth figure. Then, as shown in the fourteenth figure, a wafer 2 is placed in the wafer receiving hole 41 so that the pad 21 of the wafer 2 is exposed through the through hole 32 corresponding to the g of the substrate 3. . Next, a positioning layer formed of a photoresist material is formed on the first portion 40 of the first protective layer to cover the wafer 22. Then, by similar exposure to that applied to the first protective layer, And the subsequent chemical rinsing treatment, the central portion of the gastric positioning layer 42 was removed so that a part of the surface of the crystal TC2 opposite to the welding pad mounting surface was exposed, such as

200414470 V. Description of the invention (9): 5: Go :: No. It should be noted that the step of removing the central part of the positioning layer 42 can be omitted. The τ dog is shown in the fifteenth and sixteenth figures. The wires 5 and the steps described in the embodiment are the same as those of the second embodiment, and will not be repeated here. | Detailed explanation of the eighth bang ^ Ϊ Ϊ Seventh to nineteenth figures show the fourth preferred embodiment of the twisting & method of the semiconductor wafer package of the present invention. The package 3 is shown in FIG. 17 and the second preferred embodiment is not preferred. In the conventional example, a first protective layer made of a photoresist material is formed on the base 3, i. Then, with the same exposure and chemical processing as described in the above: first, the second part of this example is removed, and a wafer receiving hole 41 can be formed, as in = 1.第 中 所 f. Then, a wafer 2 series is placed in the wafer accommodation ^ 8. The pad mounting surface 20 of the wafer 702 is exposed, as shown in the inside. Subsequently, the conductor, the second protective layer, and the conductor: the same steps described in the second preferred embodiment of FIG. 19 and the detailed description thereof are omitted here. It should be noted that, in the above description of the present invention, a pad is provided at the central portion of the wafer pad mounting surface, and a paddle is installed at the wafer pad mounting. The surface of the periphery of the wafer ^ 埤 pad invention. Applicable to the above, the "semiconductor wafer package method" of the present invention can indeed achieve the purpose of pre-installation by the structure and device disclosed above. 200414470 V. Description of the invention (10) and effects, It has not been seen in publications or publicly used before application, which meets the requirements for novelty and progress of invention patents. However, the drawings and descriptions disclosed above are only the embodiments of the present invention, and are not intended to limit the embodiments of the present invention. Anyone who is familiar with the technology can make other things based on the features of the present invention. Equivalent changes or modifications should be covered by the scope of patent application in the following case.

Page 14 200414470 Brief description of the diagram The first diagram is for depicting the view; the second to sixth diagrams are for the method = the first preferred implementation is the seventh to eleventh diagram is the second best practice for the installation method The third preferred seventeenth to nineteenth figures of the six-picture encapsulation method and the fourth preferred twentieth figure of the encapsulation method are schematic cross-sectional views for the insertion step. [The main components of the diagram are 10 base body 101 perforation 110 solder pad 12 ^ a protective layer 2 wafer 21 solder pad 31 wafer installation table $ 32 perforated surface 40 part-60 part 7 conductive ball a conventional semiconductor The schematic cross-section of the wafer package body depicts a schematic flow chart of the sealing example of the semiconductor wafer seal u ,,, of the present invention; the flow chart is a schematic flow chart depicting the twist of the semiconductor wafer n to the body of the present invention ^ Figures T ^ are schematic flowcharts depicting embodiments of the semiconductor wafer package of the present invention;-are schematic flowcharts depicting embodiments of the semiconductor wafer package of the present invention; and the drawings can be applied to the first and third The symbol table of the preferred embodiment] 100 Circuit track layout surface 11 Wafer 111 Wire 13 Second protective layer 20 Solder mounting surface 3 Base 30 Circuit track layout surface 4 First protective layer 6 Second protective layer 5 Wire 3, the substrate

Page 15 200414470 Brief description of the drawings 33 Surface 4, first protective layer 40 ’first part 9 conductive body 6, second protective layer 61 conductive ball 41 crystal receiving hole 42 positioning layer 50 reinforcing layer 8 insulating layer

Claims (1)

200414470 6. Application Patent Scope 1 · A semiconductor crystal is provided with half of it installed on the welding pad surface of the wafer that provides a base and the circuit performs the placement of the welding pad of the wafer wafer using photoresist The first part of the chip is covered by a part of the brother to be processed, and the other part is reserved. The circuit trace of the corresponding perforated wire is used to electrically use a photoresist. A second protective layer is used and treated only. The second is placed on the crystal surface of the base circuit track electrical element package conductor crystal body. The predetermined placement corresponding to the layout table is placed by the base material in a protective first shield and is only located in the processing, the wire is connected; the material is, The encapsulation element of the circuit connected body added to the first protective layer, the pad of the crystal; the substrate has a perforation facing the surface, and the circuit corresponds to the layer of the substrate. The four methods of exposing the wafer include the following steps: The wafer has a pad mounting surface and a circuit track layout surface, a wafer mounting surface, and several substrates. The electric decoration; the surface of the wafer is mounted on the wafer mounting surface so that the perforation is exposed; the wafer mounting surface is formed to cover the wafer fixed to the substrate; part of the wafer is exposed to ultraviolet light and it is exposed to Ultraviolet rays and the first, day-to-day pads of the first protective layer through subsequent chemical cycles are arranged on the surface of the substrate through the path of the substrate / the path of the substrate corresponding to the electrical traces The formation of the ::: layer is similar to that of exposure and chemical processing. ί = part is reserved; and conductive balls. There are several corresponding Page 17 200414470 ----- Patent Application Scope 1 Application Patent Scope Item No. 1 method, the packaging of the wire-processed Bufeng Conductor Package is at least less than the circuit layout of the substrate, and the following steps are included: ·· The soldering of the wafer and the wafer are safe, and the surface near the perforation is made of epoxy resin or photoresist material. 1 = cheng-very thin insulation ^ ^ ^ ^ ^ 1.1, ^ ^ ^ 0; J ^ ^ ^ The material of the insulating layer will be attached to form a reinforcing layer with a strength of 3. The V-line is a hardened wire -A method for packaging a conductor wafer package, including the following: for a semiconductor wafer, the wafer having a plurality of materials mounted on the mounting surface of the pad; the surface and the wafer are placed Placed on the surface of a substrate; 俾 can form a first protective layer on the surface of the substrate By exposing a first part of the first protective layer to ultraviolet light and a part of it is not exposed to ultraviolet light and by chemical washing, the first protective layer located only around the wafer 妁The first part is reserved and the pad mounting surface of the wafer is exposed; ^ On the pad mounting surface of the wafer, a plurality of conductors are formed by printing, and each conductor has an extension to the wafer The corresponding first part of the welding pad and a second part separated by a predetermined distance from the first part. [2] using a photoresist material to form a second protective layer on the first-protecting ^ 'the first part俾 can be covered on the surface of the conductive body; Sixth, the scope of the patent application is to expose each of the exposure holes with the exposure to the second protection two parts. A semiconductor wafer is sealed for a substrate, and the pads arranged on the track are provided with a predetermined photoresist material layer; By masking the first part, only the position is reserved. A protective layer of a photoresist material for electrical connection with a conductive semiconductor wire which is perforated by wire bonding on the substrate may be used; The first part of the second study is to protect the circuit and the second part of the wafer. The second part is to use the pads of the solder pads to hunt the corresponding circuit rails-the second is formed by the first layer. Exposure of the layer and chemically exposed dew holes. There are several ^ m ^ ^ electric balls formed in the corresponding conductive for exposure. The base body of the body has a method including the following steps: The surface phase includes: a circuit track layout surface, a perforation, a wafer mounting surface, and a number of bands & The circuit trajectory of the substrate is arranged. The circuit trace of the table is formed on the 7L mounting surface of the substrate. The first part of the spread layer is exposed to ultraviolet light without being exposed to ultraviolet light. The first protective layer surrounding the wafer forms a wafer receiving hole first; a mounting surface and several wafers mounted on the surface are placed in the wafer receiving hole so that the wafer The corresponding through-hole exposure; 'The pad of the crystal 7L is passed through the substrate to the corresponding parameter on the circuit track layout surface. Forming a first protective layer on the substrate's circuit track layout surface similar to the exposure and chemical washing place 200414470 VI. Scope of patent application and management 'Only the part of the second protective layer covering the wires is retained; a plurality of conductive balls electrically connected to the corresponding circuit tracks are formed on the circuit track layout surface of the substrate. According to the method for packaging a semiconductor wafer package described in item 4 of the scope of patent application, before the wire bonding process, the method further includes the following steps: using a photoresist material to form a positioning layer on the first portion of the first protective layer The upper part can cover the wafer; the central part of the positioning layer is similar to the surface opposite to the mounting surface of the positioning layer by exposure and subsequent chemical processing similar to that applied to the first protective layer— The part is the "two eyes": the package of the semiconductor wafer package as described in the fourth item of the scope, after the wire bonding process step, it also includes + at least near the perforation of the circuit layout surface of the substrate. ^ Adjacent to the surface and the mounting surface of the welding pad of the crystal S, the surface portion of the welding pad is covered with a ring 4 日 日 匕 τ1. The surface part of the surface is coated with an insulating material-like edge layer such as a photoresist material. The reinforcing wire is connected to the name of _ Fei ^. While forming the insulating layer, the material of the physical rim layer is such that the reinforcing layer of the strength formed will be attached to each wire system. / Into a reinforced wire • -Species: = Packaging method of the body crystal element sealing body, > forming a first protective layer on a substrate. 3D steps: by masking the second part of the first-protective layer Without exposure; when exposed to ultraviolet light and its reasoning, the first part of the first-protective layer is transferred to the chemical washing place ___ ^ ~ the wafer receiving hole; page 20 200414470 Sixth, the scope of patent application A pad mounting surface and a plurality of wafers mounted on the pad mounting surface are placed in the wafer receiving hole so that the wafer's pad mounting surface is exposed; on the wafer A plurality of electrical conductors are formed by printing on the mounting surface of the solder pad, and each of the electrical conductors has a first portion of the corresponding pad extending to the wafer and a predetermined distance from the first portion. Two parts, a photoresist material is used to form a second protective layer on the surface of the first part of the first protective layer, so as to cover the conductors; by exposure similar to that applied to the first protective layer and Chemical cleaning treatment, the second protective layer is formed with a plurality of The second portion of the exposed electrode bore; ^ and exposed to each hole is formed with a conductive balls. Page